src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat
   6 from nmigen.cli import main, verilog
   7
   8 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase
   9
  10
  11 class FPADD(FPBase):
  12
  13     def __init__(self, width, single_cycle=False):
  14         FPBase.__init__(self)
  15         self.width = width
  16         self.single_cycle = single_cycle
  17
  18         self.in_a  = FPOp(width)
  19         self.in_b  = FPOp(width)
  20         self.out_z = FPOp(width)
  21
  22     def get_fragment(self, platform=None):
  23         """ creates the HDL code-fragment for FPAdd
  24         """
  25         m = Module()
  26
  27         # Latches
  28         a = FPNumIn(self.in_a, self.width)
  29         b = FPNumIn(self.in_b, self.width)
  30         z = FPNumOut(self.width, False)
  31
  32         m.submodules.fpnum_a = a
  33         m.submodules.fpnum_b = b
  34         m.submodules.fpnum_z = z
  35
  36         m.d.comb += a.v.eq(self.in_a.v)
  37         m.d.comb += b.v.eq(self.in_b.v)
  38
  39         w = z.m_width + 4
  40         tot = Signal(w, reset_less=True) # sticky/round/guard, {mantissa} result, 1 overflow
  41
  42         of = Overflow()
  43
  44         m.submodules.overflow = of
  45
  46         with m.FSM() as fsm:
  47
  48             # ******
  49             # gets operand a
  50
  51             with m.State("get_a"):
  52                 self.get_op(m, self.in_a, a, "get_b")
  53
  54             # ******
  55             # gets operand b
  56
  57             with m.State("get_b"):
  58                 self.get_op(m, self.in_b, b, "special_cases")
  59
  60             # ******
  61             # special cases: NaNs, infs, zeros, denormalised
  62             # NOTE: some of these are unique to add.  see "Special Operations"
  63             # https://steve.hollasch.net/cgindex/coding/ieeefloat.html
  64
  65             with m.State("special_cases"):
  66
  67                 s_nomatch = Signal()
  68                 m.d.comb += s_nomatch.eq(a.s != b.s)
  69
  70                 m_match = Signal()
  71                 m.d.comb += m_match.eq(a.m == b.m)
  72
  73                 # if a is NaN or b is NaN return NaN
  74                 with m.If(a.is_nan | b.is_nan):
  75                     m.next = "put_z"
  76                     m.d.sync += z.nan(1)
  77
  78                 # XXX WEIRDNESS for FP16 non-canonical NaN handling
  79                 # under review
  80
  81                 ## if a is zero and b is NaN return -b
  82                 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
  83                 #    m.next = "put_z"
  84                 #    m.d.sync += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
  85
  86                 ## if b is zero and a is NaN return -a
  87                 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
  88                 #    m.next = "put_z"
  89                 #    m.d.sync += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
  90
  91                 ## if a is -zero and b is NaN return -b
  92                 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
  93                 #    m.next = "put_z"
  94                 #    m.d.sync += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
  95
  96                 ## if b is -zero and a is NaN return -a
  97                 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
  98                 #    m.next = "put_z"
  99                 #    m.d.sync += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
 100
 101                 # if a is inf return inf (or NaN)
 102                 with m.Elif(a.is_inf):
 103                     m.next = "put_z"
 104                     m.d.sync += z.inf(a.s)
 105                     # if a is inf and signs don't match return NaN
 106                     with m.If(b.exp_128 & s_nomatch):
 107                         m.d.sync += z.nan(1)
 108
 109                 # if b is inf return inf
 110                 with m.Elif(b.is_inf):
 111                     m.next = "put_z"
 112                     m.d.sync += z.inf(b.s)
 113
 114                 # if a is zero and b zero return signed-a/b
 115                 with m.Elif(a.is_zero & b.is_zero):
 116                     m.next = "put_z"
 117                     m.d.sync += z.create(a.s & b.s, b.e, b.m[3:-1])
 118
 119                 # if a is zero return b
 120                 with m.Elif(a.is_zero):
 121                     m.next = "put_z"
 122                     m.d.sync += z.create(b.s, b.e, b.m[3:-1])
 123
 124                 # if b is zero return a
 125                 with m.Elif(b.is_zero):
 126                     m.next = "put_z"
 127                     m.d.sync += z.create(a.s, a.e, a.m[3:-1])
 128
 129                 # if a equal to -b return zero (+ve zero)
 130                 with m.Elif(s_nomatch & m_match & (a.e == b.e)):
 131                     m.next = "put_z"
 132                     m.d.sync += z.zero(0)
 133
 134                 # Denormalised Number checks
 135                 with m.Else():
 136                     m.next = "denormalise"
 137
 138             # ******
 139             # denormalise.
 140
 141             with m.State("denormalise"):
 142                 # Denormalised Number checks
 143                 m.next = "align"
 144                 self.denormalise(m, a)
 145                 self.denormalise(m, b)
 146
 147             # ******
 148             # align.
 149
 150             with m.State("align"):
 151                 if not self.single_cycle:
 152                     # NOTE: this does *not* do single-cycle multi-shifting,
 153                     #       it *STAYS* in the align state until exponents match
 154
 155                     # exponent of a greater than b: shift b down
 156                     with m.If(a.e > b.e):
 157                         m.d.sync += b.shift_down()
 158                     # exponent of b greater than a: shift a down
 159                     with m.Elif(a.e < b.e):
 160                         m.d.sync += a.shift_down()
 161                     # exponents equal: move to next stage.
 162                     with m.Else():
 163                         m.next = "add_0"
 164                 else:
 165                     # This one however (single-cycle) will do the shift
 166                     # in one go.
 167
 168                     # XXX TODO: the shifter used here is quite expensive
 169                     # having only one would be better
 170
 171                     ediff = Signal((len(a.e), True), reset_less=True)
 172                     ediffr = Signal((len(a.e), True), reset_less=True)
 173                     m.d.comb += ediff.eq(a.e - b.e)
 174                     m.d.comb += ediffr.eq(b.e - a.e)
 175                     with m.If(ediff > 0):
 176                         m.d.sync += b.shift_down_multi(ediff)
 177                     # exponent of b greater than a: shift a down
 178                     with m.Elif(ediff < 0):
 179                         m.d.sync += a.shift_down_multi(ediffr)
 180
 181                     m.next = "add_0"
 182
 183             # ******
 184             # First stage of add.  covers same-sign (add) and subtract
 185             # special-casing when mantissas are greater or equal, to
 186             # give greatest accuracy.
 187
 188             with m.State("add_0"):
 189                 m.next = "add_1"
 190                 m.d.sync += z.e.eq(a.e)
 191                 # same-sign (both negative or both positive) add mantissas
 192                 with m.If(a.s == b.s):
 193                     m.d.sync += [
 194                         tot.eq(Cat(a.m, 0) + Cat(b.m, 0)),
 195                         z.s.eq(a.s)
 196                     ]
 197                 # a mantissa greater than b, use a
 198                 with m.Elif(a.m >= b.m):
 199                     m.d.sync += [
 200                         tot.eq(Cat(a.m, 0) - Cat(b.m, 0)),
 201                         z.s.eq(a.s)
 202                     ]
 203                 # b mantissa greater than a, use b
 204                 with m.Else():
 205                     m.d.sync += [
 206                         tot.eq(Cat(b.m, 0) - Cat(a.m, 0)),
 207                         z.s.eq(b.s)
 208                 ]
 209
 210             # ******
 211             # Second stage of add: preparation for normalisation.
 212             # detects when tot sum is too big (tot[27] is kinda a carry bit)
 213
 214             with m.State("add_1"):
 215                 m.next = "normalise_1"
 216                 # tot[27] gets set when the sum overflows. shift result down
 217                 with m.If(tot[-1]):
 218                     m.d.sync += [
 219                         z.m.eq(tot[4:]),
 220                         of.m0.eq(tot[4]),
 221                         of.guard.eq(tot[3]),
 222                         of.round_bit.eq(tot[2]),
 223                         of.sticky.eq(tot[1] | tot[0]),
 224                         z.e.eq(z.e + 1)
 225                 ]
 226                 # tot[27] zero case
 227                 with m.Else():
 228                     m.d.sync += [
 229                         z.m.eq(tot[3:]),
 230                         of.m0.eq(tot[3]),
 231                         of.guard.eq(tot[2]),
 232                         of.round_bit.eq(tot[1]),
 233                         of.sticky.eq(tot[0])
 234                 ]
 235
 236             # ******
 237             # First stage of normalisation.
 238
 239             with m.State("normalise_1"):
 240                 self.normalise_1(m, z, of, "normalise_2")
 241
 242             # ******
 243             # Second stage of normalisation.
 244
 245             with m.State("normalise_2"):
 246                 self.normalise_2(m, z, of, "round")
 247
 248             # ******
 249             # rounding stage
 250
 251             with m.State("round"):
 252                 self.roundz(m, z, of, "corrections")
 253
 254             # ******
 255             # correction stage
 256
 257             with m.State("corrections"):
 258                 self.corrections(m, z, "pack")
 259
 260             # ******
 261             # pack stage
 262
 263             with m.State("pack"):
 264                 self.pack(m, z, "put_z")
 265
 266             # ******
 267             # put_z stage
 268
 269             with m.State("put_z"):
 270                 self.put_z(m, z, self.out_z, "get_a")
 271
 272         return m
 273
 274
 275 if __name__ == "__main__":
 276     alu = FPADD(width=32)
 277     main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
 278
 279
 280     # works... but don't use, just do "python fname.py convert -t v"
 281     #print (verilog.convert(alu, ports=[
 282     #                        ports=alu.in_a.ports() + \
 283     #                              alu.in_b.ports() + \
 284     #                              alu.out_z.ports())