e9464ce23f7407965023ae094ad673f423efe75b
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
, Cat
6 from nmigen
.cli
import main
, verilog
8 from fpbase
import FPNumIn
, FPNumOut
, FPOp
, Overflow
, FPBase
, FPNumBase
11 class FPState(FPBase
):
12 def __init__(self
, state_from
):
13 self
.state_from
= state_from
15 def set_inputs(self
, inputs
):
17 for k
,v
in inputs
.items():
20 def set_outputs(self
, outputs
):
21 self
.outputs
= outputs
22 for k
,v
in outputs
.items():
27 def __init__(self
, width
):
28 self
.in_op
= FPOp(width
)
29 self
.out_op
= FPNumIn(self
.in_op
, width
)
30 self
.out_decode
= Signal(reset_less
=True)
32 def setup(self
, m
, in_op
, out_op
, out_decode
):
33 """ links module to inputs and outputs
35 m
.d
.comb
+= self
.in_op
.copy(in_op
)
36 m
.d
.comb
+= out_op
.v
.eq(self
.out_op
.v
)
37 m
.d
.comb
+= out_decode
.eq(self
.out_decode
)
39 def elaborate(self
, platform
):
41 m
.d
.comb
+= self
.out_decode
.eq((self
.in_op
.ack
) & (self
.in_op
.stb
))
42 #m.submodules.get_op_in = self.in_op
43 m
.submodules
.get_op_out
= self
.out_op
44 with m
.If(self
.out_decode
):
46 self
.out_op
.decode(self
.in_op
.v
),
51 class FPGetOp(FPState
):
55 def __init__(self
, in_state
, out_state
, in_op
, width
):
56 FPState
.__init
__(self
, in_state
)
57 self
.out_state
= out_state
58 self
.mod
= FPGetOpMod(width
)
60 self
.out_op
= FPNumIn(in_op
, width
)
61 self
.out_decode
= Signal(reset_less
=True)
64 with m
.If(self
.out_decode
):
65 m
.next
= self
.out_state
68 self
.out_op
.copy(self
.mod
.out_op
)
71 m
.d
.sync
+= self
.in_op
.ack
.eq(1)
74 class FPGetOpB(FPState
):
78 def __init__(self
, in_b
, width
):
79 FPState
.__init
__(self
, "get_b")
81 self
.b
= FPNumIn(self
.in_b
, width
)
84 self
.get_op(m
, self
.in_b
, self
.b
, "special_cases")
87 class FPAddSpecialCasesMod
:
88 """ special cases: NaNs, infs, zeros, denormalised
89 NOTE: some of these are unique to add. see "Special Operations"
90 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
93 def __init__(self
, width
):
94 self
.in_a
= FPNumBase(width
)
95 self
.in_b
= FPNumBase(width
)
96 self
.out_z
= FPNumOut(width
, False)
97 self
.out_do_z
= Signal(reset_less
=True)
99 def setup(self
, m
, in_a
, in_b
, out_z
, out_do_z
):
100 """ links module to inputs and outputs
102 m
.d
.comb
+= self
.in_a
.copy(in_a
)
103 m
.d
.comb
+= self
.in_b
.copy(in_b
)
104 #m.d.comb += out_z.v.eq(self.out_z.v)
105 m
.d
.comb
+= out_do_z
.eq(self
.out_do_z
)
107 def elaborate(self
, platform
):
110 m
.submodules
.sc_in_a
= self
.in_a
111 m
.submodules
.sc_in_b
= self
.in_b
112 m
.submodules
.sc_out_z
= self
.out_z
115 m
.d
.comb
+= s_nomatch
.eq(self
.in_a
.s
!= self
.in_b
.s
)
118 m
.d
.comb
+= m_match
.eq(self
.in_a
.m
== self
.in_b
.m
)
120 # if a is NaN or b is NaN return NaN
121 with m
.If(self
.in_a
.is_nan | self
.in_b
.is_nan
):
122 m
.d
.comb
+= self
.out_do_z
.eq(1)
123 m
.d
.comb
+= self
.out_z
.nan(0)
125 # XXX WEIRDNESS for FP16 non-canonical NaN handling
128 ## if a is zero and b is NaN return -b
129 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
130 # m.d.comb += self.out_do_z.eq(1)
131 # m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
133 ## if b is zero and a is NaN return -a
134 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
135 # m.d.comb += self.out_do_z.eq(1)
136 # m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
138 ## if a is -zero and b is NaN return -b
139 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
140 # m.d.comb += self.out_do_z.eq(1)
141 # m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
143 ## if b is -zero and a is NaN return -a
144 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
145 # m.d.comb += self.out_do_z.eq(1)
146 # m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
148 # if a is inf return inf (or NaN)
149 with m
.Elif(self
.in_a
.is_inf
):
150 m
.d
.comb
+= self
.out_do_z
.eq(1)
151 m
.d
.comb
+= self
.out_z
.inf(self
.in_a
.s
)
152 # if a is inf and signs don't match return NaN
153 with m
.If(self
.in_b
.exp_128
& s_nomatch
):
154 m
.d
.comb
+= self
.out_z
.nan(0)
156 # if b is inf return inf
157 with m
.Elif(self
.in_b
.is_inf
):
158 m
.d
.comb
+= self
.out_do_z
.eq(1)
159 m
.d
.comb
+= self
.out_z
.inf(self
.in_b
.s
)
161 # if a is zero and b zero return signed-a/b
162 with m
.Elif(self
.in_a
.is_zero
& self
.in_b
.is_zero
):
163 m
.d
.comb
+= self
.out_do_z
.eq(1)
164 m
.d
.comb
+= self
.out_z
.create(self
.in_a
.s
& self
.in_b
.s
,
168 # if a is zero return b
169 with m
.Elif(self
.in_a
.is_zero
):
170 m
.d
.comb
+= self
.out_do_z
.eq(1)
171 m
.d
.comb
+= self
.out_z
.create(self
.in_b
.s
, self
.in_b
.e
,
174 # if b is zero return a
175 with m
.Elif(self
.in_b
.is_zero
):
176 m
.d
.comb
+= self
.out_do_z
.eq(1)
177 m
.d
.comb
+= self
.out_z
.create(self
.in_a
.s
, self
.in_a
.e
,
180 # if a equal to -b return zero (+ve zero)
181 with m
.Elif(s_nomatch
& m_match
& (self
.in_a
.e
== self
.in_b
.e
)):
182 m
.d
.comb
+= self
.out_do_z
.eq(1)
183 m
.d
.comb
+= self
.out_z
.zero(0)
185 # Denormalised Number checks
187 m
.d
.comb
+= self
.out_do_z
.eq(0)
192 class FPAddSpecialCases(FPState
):
193 """ special cases: NaNs, infs, zeros, denormalised
194 NOTE: some of these are unique to add. see "Special Operations"
195 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
198 def __init__(self
, width
):
199 FPState
.__init
__(self
, "special_cases")
200 self
.mod
= FPAddSpecialCasesMod(width
)
201 self
.out_z
= FPNumOut(width
, False)
202 self
.out_do_z
= Signal(reset_less
=True)
205 with m
.If(self
.out_do_z
):
206 m
.d
.sync
+= self
.out_z
.v
.eq(self
.mod
.out_z
.v
) # only take the output
209 m
.next
= "denormalise"
212 class FPAddDeNormMod(FPState
):
214 def __init__(self
, width
):
215 self
.in_a
= FPNumBase(width
)
216 self
.in_b
= FPNumBase(width
)
217 self
.out_a
= FPNumBase(width
)
218 self
.out_b
= FPNumBase(width
)
220 def setup(self
, m
, in_a
, in_b
, out_a
, out_b
):
221 """ links module to inputs and outputs
223 m
.d
.comb
+= self
.in_a
.copy(in_a
)
224 m
.d
.comb
+= self
.in_b
.copy(in_b
)
225 m
.d
.comb
+= out_a
.copy(self
.out_a
)
226 m
.d
.comb
+= out_b
.copy(self
.out_b
)
228 def elaborate(self
, platform
):
230 m
.submodules
.denorm_in_a
= self
.in_a
231 m
.submodules
.denorm_in_b
= self
.in_b
232 m
.submodules
.denorm_out_a
= self
.out_a
233 m
.submodules
.denorm_out_b
= self
.out_b
234 # hmmm, don't like repeating identical code
235 m
.d
.comb
+= self
.out_a
.copy(self
.in_a
)
236 with m
.If(self
.in_a
.exp_n127
):
237 m
.d
.comb
+= self
.out_a
.e
.eq(self
.in_a
.N126
) # limit a exponent
239 m
.d
.comb
+= self
.out_a
.m
[-1].eq(1) # set top mantissa bit
241 m
.d
.comb
+= self
.out_b
.copy(self
.in_b
)
242 with m
.If(self
.in_b
.exp_n127
):
243 m
.d
.comb
+= self
.out_b
.e
.eq(self
.in_b
.N126
) # limit a exponent
245 m
.d
.comb
+= self
.out_b
.m
[-1].eq(1) # set top mantissa bit
250 class FPAddDeNorm(FPState
):
252 def __init__(self
, width
):
253 FPState
.__init
__(self
, "denormalise")
254 self
.mod
= FPAddDeNormMod(width
)
255 self
.out_a
= FPNumBase(width
)
256 self
.out_b
= FPNumBase(width
)
259 # Denormalised Number checks
261 m
.d
.sync
+= self
.a
.copy(self
.out_a
)
262 m
.d
.sync
+= self
.b
.copy(self
.out_b
)
265 class FPAddAlignMultiMod(FPState
):
267 def __init__(self
, width
):
268 self
.in_a
= FPNumBase(width
)
269 self
.in_b
= FPNumBase(width
)
270 self
.out_a
= FPNumIn(None, width
)
271 self
.out_b
= FPNumIn(None, width
)
272 self
.exp_eq
= Signal(reset_less
=True)
274 def setup(self
, m
, in_a
, in_b
, out_a
, out_b
, exp_eq
):
275 """ links module to inputs and outputs
277 m
.d
.comb
+= self
.in_a
.copy(in_a
)
278 m
.d
.comb
+= self
.in_b
.copy(in_b
)
279 m
.d
.comb
+= out_a
.copy(self
.out_a
)
280 m
.d
.comb
+= out_b
.copy(self
.out_b
)
281 m
.d
.comb
+= exp_eq
.eq(self
.exp_eq
)
283 def elaborate(self
, platform
):
284 # This one however (single-cycle) will do the shift
289 #m.submodules.align_in_a = self.in_a
290 #m.submodules.align_in_b = self.in_b
291 m
.submodules
.align_out_a
= self
.out_a
292 m
.submodules
.align_out_b
= self
.out_b
294 # NOTE: this does *not* do single-cycle multi-shifting,
295 # it *STAYS* in the align state until exponents match
297 # exponent of a greater than b: shift b down
298 m
.d
.comb
+= self
.exp_eq
.eq(0)
299 m
.d
.comb
+= self
.out_a
.copy(self
.in_a
)
300 m
.d
.comb
+= self
.out_b
.copy(self
.in_b
)
301 agtb
= Signal(reset_less
=True)
302 altb
= Signal(reset_less
=True)
303 m
.d
.comb
+= agtb
.eq(self
.in_a
.e
> self
.in_b
.e
)
304 m
.d
.comb
+= altb
.eq(self
.in_a
.e
< self
.in_b
.e
)
306 m
.d
.comb
+= self
.out_b
.shift_down(self
.in_b
)
307 # exponent of b greater than a: shift a down
309 m
.d
.comb
+= self
.out_a
.shift_down(self
.in_a
)
310 # exponents equal: move to next stage.
312 m
.d
.comb
+= self
.exp_eq
.eq(1)
316 class FPAddAlignMulti(FPState
):
318 def __init__(self
, width
):
319 FPState
.__init
__(self
, "align")
320 self
.mod
= FPAddAlignMultiMod(width
)
321 self
.out_a
= FPNumIn(None, width
)
322 self
.out_b
= FPNumIn(None, width
)
323 self
.exp_eq
= Signal(reset_less
=True)
326 m
.d
.sync
+= self
.a
.copy(self
.out_a
)
327 m
.d
.sync
+= self
.b
.copy(self
.out_b
)
328 with m
.If(self
.exp_eq
):
332 class FPAddAlignSingleMod
:
334 def __init__(self
, width
):
335 self
.in_a
= FPNumBase(width
)
336 self
.in_b
= FPNumBase(width
)
337 self
.out_a
= FPNumIn(None, width
)
338 self
.out_b
= FPNumIn(None, width
)
339 #self.out_a = FPNumBase(width)
340 #self.out_b = FPNumBase(width)
342 def setup(self
, m
, in_a
, in_b
, out_a
, out_b
):
343 """ links module to inputs and outputs
345 m
.d
.comb
+= self
.in_a
.copy(in_a
)
346 m
.d
.comb
+= self
.in_b
.copy(in_b
)
347 m
.d
.comb
+= out_a
.copy(self
.out_a
)
348 m
.d
.comb
+= out_b
.copy(self
.out_b
)
350 def elaborate(self
, platform
):
351 # This one however (single-cycle) will do the shift
356 m
.submodules
.align_in_a
= self
.in_a
357 m
.submodules
.align_in_b
= self
.in_b
358 m
.submodules
.align_out_a
= self
.out_a
359 m
.submodules
.align_out_b
= self
.out_b
361 # XXX TODO: the shifter used here is quite expensive
362 # having only one would be better
364 ediff
= Signal((len(self
.in_a
.e
), True), reset_less
=True)
365 ediffr
= Signal((len(self
.in_a
.e
), True), reset_less
=True)
367 m
.d
.comb
+= ediff
.eq(self
.in_a
.e
- self
.in_b
.e
)
368 m
.d
.comb
+= ediffr
.eq(self
.in_b
.e
- self
.in_a
.e
)
369 m
.d
.comb
+= self
.out_a
.copy(self
.in_a
)
370 m
.d
.comb
+= self
.out_b
.copy(self
.in_b
)
371 with m
.If(ediff
> 0):
372 m
.d
.comb
+= self
.out_b
.shift_down_multi(ediff
, self
.in_b
)
373 # exponent of b greater than a: shift a down
374 with m
.Elif(ediff
< 0):
375 m
.d
.comb
+= self
.out_a
.shift_down_multi(ediffr
, self
.in_a
)
379 class FPAddAlignSingle(FPState
):
381 def __init__(self
, width
):
382 FPState
.__init
__(self
, "align")
383 self
.mod
= FPAddAlignSingleMod(width
)
384 self
.out_a
= FPNumIn(None, width
)
385 self
.out_b
= FPNumIn(None, width
)
388 m
.d
.sync
+= self
.a
.copy(self
.out_a
)
389 m
.d
.sync
+= self
.b
.copy(self
.out_b
)
393 class FPAddStage0Mod
:
395 def __init__(self
, width
):
396 self
.in_a
= FPNumBase(width
)
397 self
.in_b
= FPNumBase(width
)
398 self
.in_z
= FPNumBase(width
, False)
399 self
.out_z
= FPNumBase(width
, False)
400 self
.out_tot
= Signal(self
.out_z
.m_width
+ 4, reset_less
=True)
402 def elaborate(self
, platform
):
404 m
.submodules
.add0_in_a
= self
.in_a
405 m
.submodules
.add0_in_b
= self
.in_b
406 m
.submodules
.add0_out_z
= self
.out_z
408 m
.d
.comb
+= self
.out_z
.e
.eq(self
.in_a
.e
)
410 # store intermediate tests (and zero-extended mantissas)
411 seq
= Signal(reset_less
=True)
412 mge
= Signal(reset_less
=True)
413 am0
= Signal(len(self
.in_a
.m
)+1, reset_less
=True)
414 bm0
= Signal(len(self
.in_b
.m
)+1, reset_less
=True)
415 m
.d
.comb
+= [seq
.eq(self
.in_a
.s
== self
.in_b
.s
),
416 mge
.eq(self
.in_a
.m
>= self
.in_b
.m
),
417 am0
.eq(Cat(self
.in_a
.m
, 0)),
418 bm0
.eq(Cat(self
.in_b
.m
, 0))
420 # same-sign (both negative or both positive) add mantissas
423 self
.out_tot
.eq(am0
+ bm0
),
424 self
.out_z
.s
.eq(self
.in_a
.s
)
426 # a mantissa greater than b, use a
429 self
.out_tot
.eq(am0
- bm0
),
430 self
.out_z
.s
.eq(self
.in_a
.s
)
432 # b mantissa greater than a, use b
435 self
.out_tot
.eq(bm0
- am0
),
436 self
.out_z
.s
.eq(self
.in_b
.s
)
441 class FPAddStage0(FPState
):
442 """ First stage of add. covers same-sign (add) and subtract
443 special-casing when mantissas are greater or equal, to
444 give greatest accuracy.
447 def __init__(self
, width
):
448 FPState
.__init
__(self
, "add_0")
449 self
.mod
= FPAddStage0Mod(width
)
450 self
.out_z
= FPNumBase(width
, False)
451 self
.out_tot
= Signal(self
.out_z
.m_width
+ 4, reset_less
=True)
453 def setup(self
, m
, in_a
, in_b
):
454 """ links module to inputs and outputs
456 m
.submodules
.add0
= self
.mod
458 m
.d
.comb
+= self
.mod
.in_a
.copy(in_a
)
459 m
.d
.comb
+= self
.mod
.in_b
.copy(in_b
)
463 # NOTE: these could be done as combinatorial (merge add0+add1)
464 m
.d
.sync
+= self
.out_z
.copy(self
.mod
.out_z
)
465 m
.d
.sync
+= self
.out_tot
.eq(self
.mod
.out_tot
)
468 class FPAddStage1Mod(FPState
):
469 """ Second stage of add: preparation for normalisation.
470 detects when tot sum is too big (tot[27] is kinda a carry bit)
473 def __init__(self
, width
):
474 self
.out_norm
= Signal(reset_less
=True)
475 self
.in_z
= FPNumBase(width
, False)
476 self
.in_tot
= Signal(self
.in_z
.m_width
+ 4, reset_less
=True)
477 self
.out_z
= FPNumBase(width
, False)
478 self
.out_of
= Overflow()
480 def elaborate(self
, platform
):
482 #m.submodules.norm1_in_overflow = self.in_of
483 #m.submodules.norm1_out_overflow = self.out_of
484 #m.submodules.norm1_in_z = self.in_z
485 #m.submodules.norm1_out_z = self.out_z
486 m
.d
.comb
+= self
.out_z
.copy(self
.in_z
)
487 # tot[27] gets set when the sum overflows. shift result down
488 with m
.If(self
.in_tot
[-1]):
490 self
.out_z
.m
.eq(self
.in_tot
[4:]),
491 self
.out_of
.m0
.eq(self
.in_tot
[4]),
492 self
.out_of
.guard
.eq(self
.in_tot
[3]),
493 self
.out_of
.round_bit
.eq(self
.in_tot
[2]),
494 self
.out_of
.sticky
.eq(self
.in_tot
[1] | self
.in_tot
[0]),
495 self
.out_z
.e
.eq(self
.in_z
.e
+ 1)
500 self
.out_z
.m
.eq(self
.in_tot
[3:]),
501 self
.out_of
.m0
.eq(self
.in_tot
[3]),
502 self
.out_of
.guard
.eq(self
.in_tot
[2]),
503 self
.out_of
.round_bit
.eq(self
.in_tot
[1]),
504 self
.out_of
.sticky
.eq(self
.in_tot
[0])
509 class FPAddStage1(FPState
):
511 def __init__(self
, width
):
512 FPState
.__init
__(self
, "add_1")
513 self
.mod
= FPAddStage1Mod(width
)
514 self
.out_z
= FPNumBase(width
, False)
515 self
.out_of
= Overflow()
516 self
.norm_stb
= Signal()
518 def setup(self
, m
, in_tot
, in_z
):
519 """ links module to inputs and outputs
521 m
.submodules
.add1
= self
.mod
523 m
.d
.comb
+= self
.mod
.in_z
.copy(in_z
)
524 m
.d
.comb
+= self
.mod
.in_tot
.eq(in_tot
)
526 m
.d
.sync
+= self
.norm_stb
.eq(0) # sets to zero when not in add1 state
529 m
.submodules
.add1_out_overflow
= self
.out_of
530 m
.d
.sync
+= self
.out_of
.copy(self
.mod
.out_of
)
531 m
.d
.sync
+= self
.out_z
.copy(self
.mod
.out_z
)
532 m
.d
.sync
+= self
.norm_stb
.eq(1)
533 m
.next
= "normalise_1"
538 def __init__(self
, width
):
540 self
.in_select
= Signal(reset_less
=True)
541 self
.out_norm
= Signal(reset_less
=True)
542 self
.in_z
= FPNumBase(width
, False)
543 self
.in_of
= Overflow()
544 self
.temp_z
= FPNumBase(width
, False)
545 self
.temp_of
= Overflow()
546 self
.out_z
= FPNumBase(width
, False)
547 self
.out_of
= Overflow()
549 def elaborate(self
, platform
):
551 m
.submodules
.norm1_out_z
= self
.out_z
552 m
.submodules
.norm1_out_overflow
= self
.out_of
553 m
.submodules
.norm1_temp_z
= self
.temp_z
554 m
.submodules
.norm1_temp_of
= self
.temp_of
555 m
.submodules
.norm1_in_z
= self
.in_z
556 m
.submodules
.norm1_in_overflow
= self
.in_of
557 in_z
= FPNumBase(self
.width
, False)
559 m
.submodules
.norm1_insel_z
= in_z
560 m
.submodules
.norm1_insel_overflow
= in_of
561 # select which of temp or in z/of to use
562 with m
.If(self
.in_select
):
563 m
.d
.comb
+= in_z
.copy(self
.in_z
)
564 m
.d
.comb
+= in_of
.copy(self
.in_of
)
566 m
.d
.comb
+= in_z
.copy(self
.temp_z
)
567 m
.d
.comb
+= in_of
.copy(self
.temp_of
)
568 # initialise out from in (overridden below)
569 m
.d
.comb
+= self
.out_z
.copy(in_z
)
570 m
.d
.comb
+= self
.out_of
.copy(in_of
)
571 # normalisation increase/decrease conditions
572 decrease
= Signal(reset_less
=True)
573 increase
= Signal(reset_less
=True)
574 m
.d
.comb
+= decrease
.eq(in_z
.m_msbzero
& in_z
.exp_gt_n126
)
575 m
.d
.comb
+= increase
.eq(in_z
.exp_lt_n126
)
576 m
.d
.comb
+= self
.out_norm
.eq(decrease | increase
) # loop-end condition
580 self
.out_z
.e
.eq(in_z
.e
- 1), # DECREASE exponent
581 self
.out_z
.m
.eq(in_z
.m
<< 1), # shift mantissa UP
582 self
.out_z
.m
[0].eq(in_of
.guard
), # steal guard (was tot[2])
583 self
.out_of
.guard
.eq(in_of
.round_bit
), # round (was tot[1])
584 self
.out_of
.round_bit
.eq(0), # reset round bit
585 self
.out_of
.m0
.eq(in_of
.guard
),
590 self
.out_z
.e
.eq(in_z
.e
+ 1), # INCREASE exponent
591 self
.out_z
.m
.eq(in_z
.m
>> 1), # shift mantissa DOWN
592 self
.out_of
.guard
.eq(in_z
.m
[0]),
593 self
.out_of
.m0
.eq(in_z
.m
[1]),
594 self
.out_of
.round_bit
.eq(in_of
.guard
),
595 self
.out_of
.sticky
.eq(in_of
.sticky | in_of
.round_bit
)
601 class FPNorm1(FPState
):
603 def __init__(self
, width
):
604 FPState
.__init
__(self
, "normalise_1")
605 self
.mod
= FPNorm1Mod(width
)
606 self
.stb
= Signal(reset_less
=True)
607 self
.ack
= Signal(reset
=0, reset_less
=True)
608 self
.out_norm
= Signal(reset_less
=True)
609 self
.in_accept
= Signal(reset_less
=True)
610 self
.temp_z
= FPNumBase(width
)
611 self
.temp_of
= Overflow()
612 self
.out_z
= FPNumBase(width
)
613 self
.out_roundz
= Signal(reset_less
=True)
615 def setup(self
, m
, in_z
, in_of
, norm_stb
):
616 """ links module to inputs and outputs
618 m
.submodules
.normalise_1
= self
.mod
620 m
.d
.comb
+= self
.mod
.in_z
.copy(in_z
)
621 m
.d
.comb
+= self
.mod
.in_of
.copy(in_of
)
623 m
.d
.comb
+= self
.mod
.in_select
.eq(self
.in_accept
)
624 m
.d
.comb
+= self
.mod
.temp_z
.copy(self
.temp_z
)
625 m
.d
.comb
+= self
.mod
.temp_of
.copy(self
.temp_of
)
627 m
.d
.comb
+= self
.out_z
.copy(self
.mod
.out_z
)
628 m
.d
.comb
+= self
.out_norm
.eq(self
.mod
.out_norm
)
630 m
.d
.comb
+= self
.stb
.eq(norm_stb
)
631 m
.d
.sync
+= self
.ack
.eq(0) # sets to zero when not in normalise_1 state
635 m
.d
.comb
+= self
.in_accept
.eq((~self
.ack
) & (self
.stb
))
636 m
.d
.sync
+= self
.temp_of
.copy(self
.mod
.out_of
)
637 m
.d
.sync
+= self
.temp_z
.copy(self
.out_z
)
638 with m
.If(self
.out_norm
):
639 with m
.If(self
.in_accept
):
644 m
.d
.sync
+= self
.ack
.eq(0)
646 # normalisation not required (or done).
648 m
.d
.sync
+= self
.ack
.eq(1)
649 m
.d
.sync
+= self
.out_roundz
.eq(self
.mod
.out_of
.roundz
)
654 def __init__(self
, width
):
655 self
.in_roundz
= Signal(reset_less
=True)
656 self
.in_z
= FPNumBase(width
, False)
657 self
.out_z
= FPNumBase(width
, False)
659 def elaborate(self
, platform
):
661 m
.d
.comb
+= self
.out_z
.copy(self
.in_z
)
662 with m
.If(self
.in_roundz
):
663 m
.d
.comb
+= self
.out_z
.m
.eq(self
.in_z
.m
+ 1) # mantissa rounds up
664 with m
.If(self
.in_z
.m
== self
.in_z
.m1s
): # all 1s
665 m
.d
.comb
+= self
.out_z
.e
.eq(self
.in_z
.e
+ 1) # exponent up
669 class FPRound(FPState
):
671 def __init__(self
, width
):
672 FPState
.__init
__(self
, "round")
673 self
.mod
= FPRoundMod(width
)
674 self
.out_z
= FPNumBase(width
)
676 def setup(self
, m
, in_z
, roundz
):
677 """ links module to inputs and outputs
679 m
.submodules
.roundz
= self
.mod
681 m
.d
.comb
+= self
.mod
.in_z
.copy(in_z
)
682 m
.d
.comb
+= self
.mod
.in_roundz
.eq(roundz
)
685 m
.d
.sync
+= self
.out_z
.copy(self
.mod
.out_z
)
686 m
.next
= "corrections"
689 class FPCorrectionsMod
:
691 def __init__(self
, width
):
692 self
.in_z
= FPNumOut(width
, False)
693 self
.out_z
= FPNumOut(width
, False)
695 def elaborate(self
, platform
):
697 m
.submodules
.corr_in_z
= self
.in_z
698 m
.submodules
.corr_out_z
= self
.out_z
699 m
.d
.comb
+= self
.out_z
.copy(self
.in_z
)
700 with m
.If(self
.in_z
.is_denormalised
):
701 m
.d
.comb
+= self
.out_z
.e
.eq(self
.in_z
.N127
)
703 # with m.If(self.in_z.is_overflowed):
704 # m.d.comb += self.out_z.inf(self.in_z.s)
706 # m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
710 class FPCorrections(FPState
):
712 def __init__(self
, width
):
713 FPState
.__init
__(self
, "corrections")
714 self
.mod
= FPCorrectionsMod(width
)
715 self
.out_z
= FPNumBase(width
)
717 def setup(self
, m
, in_z
):
718 """ links module to inputs and outputs
720 m
.submodules
.corrections
= self
.mod
721 m
.d
.comb
+= self
.mod
.in_z
.copy(in_z
)
724 m
.d
.sync
+= self
.out_z
.copy(self
.mod
.out_z
)
730 def __init__(self
, width
):
731 self
.in_z
= FPNumOut(width
, False)
732 self
.out_z
= FPNumOut(width
, False)
734 def elaborate(self
, platform
):
736 m
.submodules
.pack_in_z
= self
.in_z
737 with m
.If(self
.in_z
.is_overflowed
):
738 m
.d
.comb
+= self
.out_z
.inf(self
.in_z
.s
)
740 m
.d
.comb
+= self
.out_z
.create(self
.in_z
.s
, self
.in_z
.e
, self
.in_z
.m
)
744 class FPPack(FPState
):
746 def __init__(self
, width
):
747 FPState
.__init
__(self
, "pack")
748 self
.mod
= FPPackMod(width
)
749 self
.out_z
= FPNumOut(width
, False)
751 def setup(self
, m
, in_z
):
752 """ links module to inputs and outputs
754 m
.submodules
.pack
= self
.mod
755 m
.d
.comb
+= self
.mod
.in_z
.copy(in_z
)
758 m
.d
.sync
+= self
.out_z
.v
.eq(self
.mod
.out_z
.v
)
759 m
.next
= "pack_put_z"
762 class FPPutZ(FPState
):
764 def __init__(self
, state
, in_z
, out_z
):
765 FPState
.__init
__(self
, state
)
771 self
.out_z
.v
.eq(self
.in_z
.v
)
773 with m
.If(self
.out_z
.stb
& self
.out_z
.ack
):
774 m
.d
.sync
+= self
.out_z
.stb
.eq(0)
777 m
.d
.sync
+= self
.out_z
.stb
.eq(1)
782 def __init__(self
, width
, single_cycle
=False):
784 self
.single_cycle
= single_cycle
786 self
.in_a
= FPOp(width
)
787 self
.in_b
= FPOp(width
)
788 self
.out_z
= FPOp(width
)
792 def add_state(self
, state
):
793 self
.states
.append(state
)
796 def get_fragment(self
, platform
=None):
797 """ creates the HDL code-fragment for FPAdd
800 m
.submodules
.in_a
= self
.in_a
801 m
.submodules
.in_b
= self
.in_b
802 m
.submodules
.out_z
= self
.out_z
804 geta
= self
.add_state(FPGetOp("get_a", "get_b",
805 self
.in_a
, self
.width
))
807 geta
.mod
.setup(m
, self
.in_a
, geta
.out_op
, geta
.out_decode
)
808 m
.submodules
.get_a
= geta
.mod
810 getb
= self
.add_state(FPGetOp("get_b", "special_cases",
811 self
.in_b
, self
.width
))
813 getb
.mod
.setup(m
, self
.in_b
, getb
.out_op
, getb
.out_decode
)
814 m
.submodules
.get_b
= getb
.mod
816 sc
= self
.add_state(FPAddSpecialCases(self
.width
))
817 sc
.mod
.setup(m
, a
, b
, sc
.out_z
, sc
.out_do_z
)
818 m
.submodules
.specialcases
= sc
.mod
820 dn
= self
.add_state(FPAddDeNorm(self
.width
))
821 dn
.set_inputs({"a": a
, "b": b
})
822 #dn.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
823 dn
.mod
.setup(m
, a
, b
, dn
.out_a
, dn
.out_b
)
824 m
.submodules
.denormalise
= dn
.mod
826 if self
.single_cycle
:
827 alm
= self
.add_state(FPAddAlignSingle(self
.width
))
828 alm
.set_inputs({"a": a
, "b": b
})
829 alm
.set_outputs({"a": a
, "b": b
}) # XXX outputs same as inputs
830 alm
.mod
.setup(m
, a
, b
, alm
.out_a
, alm
.out_b
)
832 alm
= self
.add_state(FPAddAlignMulti(self
.width
))
833 alm
.set_inputs({"a": a
, "b": b
})
834 #alm.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
835 alm
.mod
.setup(m
, a
, b
, alm
.out_a
, alm
.out_b
, alm
.exp_eq
)
836 m
.submodules
.align
= alm
.mod
838 add0
= self
.add_state(FPAddStage0(self
.width
))
839 add0
.setup(m
, alm
.out_a
, alm
.out_b
)
841 add1
= self
.add_state(FPAddStage1(self
.width
))
842 add1
.setup(m
, add0
.out_tot
, add0
.out_z
)
844 n1
= self
.add_state(FPNorm1(self
.width
))
845 n1
.setup(m
, add1
.out_z
, add1
.out_of
, add1
.norm_stb
)
847 rn
= self
.add_state(FPRound(self
.width
))
848 rn
.setup(m
, n1
.out_z
, n1
.out_roundz
)
850 cor
= self
.add_state(FPCorrections(self
.width
))
851 cor
.setup(m
, rn
.out_z
)
853 pa
= self
.add_state(FPPack(self
.width
))
854 pa
.setup(m
, cor
.out_z
)
856 ppz
= self
.add_state(FPPutZ("pack_put_z", pa
.out_z
, self
.out_z
))
858 pz
= self
.add_state(FPPutZ("put_z", sc
.out_z
, self
.out_z
))
862 for state
in self
.states
:
863 with m
.State(state
.state_from
):
869 if __name__
== "__main__":
870 alu
= FPADD(width
=32)
871 main(alu
, ports
=alu
.in_a
.ports() + alu
.in_b
.ports() + alu
.out_z
.ports())
874 # works... but don't use, just do "python fname.py convert -t v"
875 #print (verilog.convert(alu, ports=[
876 # ports=alu.in_a.ports() + \
877 # alu.in_b.ports() + \