1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
, Cat
6 from nmigen
.cli
import main
, verilog
8 from fpbase
import FPNumIn
, FPNumOut
, FPOp
, Overflow
, FPBase
, FPNumBase
11 class FPState(FPBase
):
12 def __init__(self
, state_from
):
13 self
.state_from
= state_from
15 def set_inputs(self
, inputs
):
17 for k
,v
in inputs
.items():
20 def set_outputs(self
, outputs
):
21 self
.outputs
= outputs
22 for k
,v
in outputs
.items():
26 class FPGetOpA(FPState
):
30 def __init__(self
, in_a
, width
):
31 FPState
.__init
__(self
, "get_a")
33 self
.a
= FPNumIn(in_a
, width
)
36 self
.get_op(m
, self
.in_a
, self
.a
, "get_b")
39 class FPGetOpB(FPState
):
44 self
.get_op(m
, self
.in_b
, self
.b
, "special_cases")
47 class FPAddSpecialCasesMod
:
48 """ special cases: NaNs, infs, zeros, denormalised
49 NOTE: some of these are unique to add. see "Special Operations"
50 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
53 def __init__(self
, width
):
54 self
.in_a
= FPNumBase(width
)
55 self
.in_b
= FPNumBase(width
)
56 self
.out_z
= FPNumOut(width
, False)
57 self
.out_do_z
= Signal(reset_less
=True)
59 def setup(self
, m
, in_a
, in_b
, out_z
, out_do_z
):
60 """ links module to inputs and outputs
62 m
.d
.comb
+= self
.in_a
.copy(in_a
)
63 m
.d
.comb
+= self
.in_b
.copy(in_b
)
64 m
.d
.comb
+= out_z
.v
.eq(self
.out_z
.v
)
65 m
.d
.comb
+= out_do_z
.eq(self
.out_do_z
)
67 def elaborate(self
, platform
):
70 m
.submodules
.sc_in_a
= self
.in_a
71 m
.submodules
.sc_in_b
= self
.in_b
72 m
.submodules
.sc_out_z
= self
.out_z
75 m
.d
.comb
+= s_nomatch
.eq(self
.in_a
.s
!= self
.in_b
.s
)
78 m
.d
.comb
+= m_match
.eq(self
.in_a
.m
== self
.in_b
.m
)
80 # if a is NaN or b is NaN return NaN
81 with m
.If(self
.in_a
.is_nan | self
.in_b
.is_nan
):
82 m
.d
.comb
+= self
.out_do_z
.eq(1)
83 m
.d
.comb
+= self
.out_z
.nan(1)
85 # XXX WEIRDNESS for FP16 non-canonical NaN handling
88 ## if a is zero and b is NaN return -b
89 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
90 # m.d.comb += self.out_do_z.eq(1)
91 # m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
93 ## if b is zero and a is NaN return -a
94 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
95 # m.d.comb += self.out_do_z.eq(1)
96 # m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
98 ## if a is -zero and b is NaN return -b
99 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
100 # m.d.comb += self.out_do_z.eq(1)
101 # m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
103 ## if b is -zero and a is NaN return -a
104 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
105 # m.d.comb += self.out_do_z.eq(1)
106 # m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
108 # if a is inf return inf (or NaN)
109 with m
.Elif(self
.in_a
.is_inf
):
110 m
.d
.comb
+= self
.out_do_z
.eq(1)
111 m
.d
.comb
+= self
.out_z
.inf(self
.in_a
.s
)
112 # if a is inf and signs don't match return NaN
113 with m
.If(self
.in_b
.exp_128
& s_nomatch
):
114 m
.d
.comb
+= self
.out_z
.nan(1)
116 # if b is inf return inf
117 with m
.Elif(self
.in_b
.is_inf
):
118 m
.d
.comb
+= self
.out_do_z
.eq(1)
119 m
.d
.comb
+= self
.out_z
.inf(self
.in_b
.s
)
121 # if a is zero and b zero return signed-a/b
122 with m
.Elif(self
.in_a
.is_zero
& self
.in_b
.is_zero
):
123 m
.d
.comb
+= self
.out_do_z
.eq(1)
124 m
.d
.comb
+= self
.out_z
.create(self
.in_a
.s
& self
.in_b
.s
,
128 # if a is zero return b
129 with m
.Elif(self
.in_a
.is_zero
):
130 m
.d
.comb
+= self
.out_do_z
.eq(1)
131 m
.d
.comb
+= self
.out_z
.create(self
.in_b
.s
, self
.in_b
.e
,
134 # if b is zero return a
135 with m
.Elif(self
.in_b
.is_zero
):
136 m
.d
.comb
+= self
.out_do_z
.eq(1)
137 m
.d
.comb
+= self
.out_z
.create(self
.in_a
.s
, self
.in_a
.e
,
140 # if a equal to -b return zero (+ve zero)
141 with m
.Elif(s_nomatch
& m_match
& (self
.in_a
.e
== self
.in_b
.e
)):
142 m
.d
.comb
+= self
.out_do_z
.eq(1)
143 m
.d
.comb
+= self
.out_z
.zero(0)
145 # Denormalised Number checks
147 m
.d
.comb
+= self
.out_do_z
.eq(0)
152 class FPAddSpecialCases(FPState
):
153 """ special cases: NaNs, infs, zeros, denormalised
154 NOTE: some of these are unique to add. see "Special Operations"
155 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
158 def __init__(self
, width
):
159 FPState
.__init
__(self
, "special_cases")
160 self
.mod
= FPAddSpecialCasesMod(width
)
161 self
.out_z
= FPNumOut(width
, False)
162 self
.out_do_z
= Signal(reset_less
=True)
165 with m
.If(self
.out_do_z
):
166 m
.d
.sync
+= self
.z
.v
.eq(self
.out_z
.v
) # only take the output
169 m
.next
= "denormalise"
172 class FPAddDeNorm(FPState
):
175 # Denormalised Number checks
177 self
.denormalise(m
, self
.a
)
178 self
.denormalise(m
, self
.b
)
181 class FPAddAlignMultiMod(FPState
):
183 def __init__(self
, width
):
184 self
.in_a
= FPNumBase(width
)
185 self
.in_b
= FPNumBase(width
)
186 self
.out_a
= FPNumIn(None, width
)
187 self
.out_b
= FPNumIn(None, width
)
188 self
.exp_eq
= Signal(reset_less
=True)
190 def setup(self
, m
, in_a
, in_b
, out_a
, out_b
, exp_eq
):
191 """ links module to inputs and outputs
193 m
.d
.comb
+= self
.in_a
.copy(in_a
)
194 m
.d
.comb
+= self
.in_b
.copy(in_b
)
195 m
.d
.comb
+= out_a
.copy(self
.out_a
)
196 m
.d
.comb
+= out_b
.copy(self
.out_b
)
197 m
.d
.comb
+= exp_eq
.eq(self
.exp_eq
)
199 def elaborate(self
, platform
):
200 # This one however (single-cycle) will do the shift
205 #m.submodules.align_in_a = self.in_a
206 #m.submodules.align_in_b = self.in_b
207 m
.submodules
.align_out_a
= self
.out_a
208 m
.submodules
.align_out_b
= self
.out_b
210 # NOTE: this does *not* do single-cycle multi-shifting,
211 # it *STAYS* in the align state until exponents match
213 # exponent of a greater than b: shift b down
214 m
.d
.comb
+= self
.exp_eq
.eq(0)
215 m
.d
.comb
+= self
.out_a
.copy(self
.in_a
)
216 m
.d
.comb
+= self
.out_b
.copy(self
.in_b
)
217 with m
.If(self
.in_a
.e
> self
.in_b
.e
):
218 m
.d
.comb
+= self
.out_b
.shift_down(self
.in_b
)
219 # exponent of b greater than a: shift a down
220 with m
.Elif(self
.in_a
.e
< self
.in_b
.e
):
221 m
.d
.comb
+= self
.out_a
.shift_down(self
.in_a
)
222 # exponents equal: move to next stage.
224 m
.d
.comb
+= self
.exp_eq
.eq(1)
228 class FPAddAlignMulti(FPState
):
230 def __init__(self
, width
):
231 FPState
.__init
__(self
, "align")
232 self
.mod
= FPAddAlignMultiMod(width
)
233 self
.out_a
= FPNumIn(None, width
)
234 self
.out_b
= FPNumIn(None, width
)
235 self
.exp_eq
= Signal(reset_less
=True)
238 m
.d
.sync
+= self
.a
.copy(self
.out_a
)
239 m
.d
.sync
+= self
.b
.copy(self
.out_b
)
240 with m
.If(self
.exp_eq
):
244 class FPAddAlignSingleMod
:
246 def __init__(self
, width
):
247 self
.in_a
= FPNumBase(width
)
248 self
.in_b
= FPNumBase(width
)
249 self
.out_a
= FPNumIn(None, width
)
250 self
.out_b
= FPNumIn(None, width
)
251 #self.out_a = FPNumBase(width)
252 #self.out_b = FPNumBase(width)
254 def setup(self
, m
, in_a
, in_b
, out_a
, out_b
):
255 """ links module to inputs and outputs
257 m
.d
.comb
+= self
.in_a
.copy(in_a
)
258 m
.d
.comb
+= self
.in_b
.copy(in_b
)
259 m
.d
.comb
+= out_a
.copy(self
.out_a
)
260 m
.d
.comb
+= out_b
.copy(self
.out_b
)
262 def elaborate(self
, platform
):
263 # This one however (single-cycle) will do the shift
268 #m.submodules.align_in_a = self.in_a
269 #m.submodules.align_in_b = self.in_b
270 m
.submodules
.align_out_a
= self
.out_a
271 m
.submodules
.align_out_b
= self
.out_b
273 # XXX TODO: the shifter used here is quite expensive
274 # having only one would be better
276 ediff
= Signal((len(self
.in_a
.e
), True), reset_less
=True)
277 ediffr
= Signal((len(self
.in_a
.e
), True), reset_less
=True)
278 m
.d
.comb
+= ediff
.eq(self
.in_a
.e
- self
.in_b
.e
)
279 m
.d
.comb
+= ediffr
.eq(self
.in_b
.e
- self
.in_a
.e
)
280 m
.d
.comb
+= self
.out_a
.copy(self
.in_a
)
281 m
.d
.comb
+= self
.out_b
.copy(self
.in_b
)
282 with m
.If(ediff
> 0):
283 m
.d
.comb
+= self
.out_b
.shift_down_multi(ediff
)
284 # exponent of b greater than a: shift a down
285 with m
.Elif(ediff
< 0):
286 m
.d
.comb
+= self
.out_a
.shift_down_multi(ediffr
)
290 class FPAddAlignSingle(FPState
):
292 def __init__(self
, width
):
293 FPState
.__init
__(self
, "align")
294 self
.mod
= FPAddAlignSingleMod(width
)
295 self
.out_a
= FPNumIn(None, width
)
296 self
.out_b
= FPNumIn(None, width
)
299 m
.d
.sync
+= self
.a
.copy(self
.out_a
)
300 m
.d
.sync
+= self
.b
.copy(self
.out_b
)
304 class FPAddStage0Mod
:
306 def __init__(self
, width
):
307 self
.in_a
= FPNumBase(width
)
308 self
.in_b
= FPNumBase(width
)
309 self
.in_z
= FPNumBase(width
, False)
310 self
.out_z
= FPNumBase(width
, False)
311 self
.out_tot
= Signal(self
.out_z
.m_width
+ 4, reset_less
=True)
313 def setup(self
, m
, in_a
, in_b
, in_z
, out_z
, out_tot
):
314 """ links module to inputs and outputs
316 m
.d
.comb
+= self
.in_a
.copy(in_a
)
317 m
.d
.comb
+= self
.in_b
.copy(in_b
)
318 m
.d
.comb
+= self
.in_z
.copy(in_z
)
319 m
.d
.comb
+= out_z
.copy(self
.out_z
)
320 m
.d
.comb
+= out_tot
.eq(self
.out_tot
)
322 def elaborate(self
, platform
):
324 #m.submodules.add0_in_a = self.in_a
325 #m.submodules.add0_in_b = self.in_b
326 #m.submodules.add0_in_z = self.in_z
327 #m.submodules.add0_out_z = self.out_z
329 m
.d
.comb
+= self
.out_z
.e
.eq(self
.in_a
.e
)
330 # same-sign (both negative or both positive) add mantissas
331 with m
.If(self
.in_a
.s
== self
.in_b
.s
):
333 self
.out_tot
.eq(Cat(self
.in_a
.m
, 0) + Cat(self
.in_b
.m
, 0)),
334 self
.out_z
.s
.eq(self
.in_a
.s
)
336 # a mantissa greater than b, use a
337 with m
.Elif(self
.in_a
.m
>= self
.in_b
.m
):
339 self
.out_tot
.eq(Cat(self
.in_a
.m
, 0) - Cat(self
.in_b
.m
, 0)),
340 self
.out_z
.s
.eq(self
.in_a
.s
)
342 # b mantissa greater than a, use b
345 self
.out_tot
.eq(Cat(self
.in_b
.m
, 0) - Cat(self
.in_a
.m
, 0)),
346 self
.out_z
.s
.eq(self
.in_b
.s
)
351 class FPAddStage0(FPState
):
352 """ First stage of add. covers same-sign (add) and subtract
353 special-casing when mantissas are greater or equal, to
354 give greatest accuracy.
357 def __init__(self
, width
):
358 FPState
.__init
__(self
, "add_0")
359 self
.mod
= FPAddStage0Mod(width
)
360 self
.out_z
= FPNumBase(width
, False)
361 self
.out_tot
= Signal(self
.out_z
.m_width
+ 4, reset_less
=True)
365 m
.d
.sync
+= self
.z
.copy(self
.out_z
)
368 class FPAddStage1Mod(FPState
):
369 """ Second stage of add: preparation for normalisation.
370 detects when tot sum is too big (tot[27] is kinda a carry bit)
373 def __init__(self
, width
):
374 self
.out_norm
= Signal(reset_less
=True)
375 self
.in_z
= FPNumBase(width
, False)
376 self
.in_tot
= Signal(self
.in_z
.m_width
+ 4, reset_less
=True)
377 self
.out_z
= FPNumBase(width
, False)
378 self
.out_of
= Overflow()
380 def setup(self
, m
, in_tot
, in_z
, out_z
, out_of
):
381 """ links module to inputs and outputs
383 m
.d
.comb
+= self
.in_z
.copy(in_z
)
384 m
.d
.comb
+= self
.in_tot
.eq(in_tot
)
385 m
.d
.comb
+= out_z
.copy(self
.out_z
)
386 m
.d
.comb
+= out_of
.copy(self
.out_of
)
388 def elaborate(self
, platform
):
390 m
.submodules
.add1_out_overflow
= self
.out_of
391 #m.submodules.norm1_in_overflow = self.in_of
392 #m.submodules.norm1_in_z = self.in_z
393 #m.submodules.norm1_out_z = self.out_z
394 m
.d
.comb
+= self
.out_z
.copy(self
.in_z
)
395 # tot[27] gets set when the sum overflows. shift result down
396 with m
.If(self
.in_tot
[-1]):
398 self
.out_z
.m
.eq(self
.in_tot
[4:]),
399 self
.out_of
.m0
.eq(self
.in_tot
[4]),
400 self
.out_of
.guard
.eq(self
.in_tot
[3]),
401 self
.out_of
.round_bit
.eq(self
.in_tot
[2]),
402 self
.out_of
.sticky
.eq(self
.in_tot
[1] | self
.in_tot
[0]),
403 self
.out_z
.e
.eq(self
.in_z
.e
+ 1)
408 self
.out_z
.m
.eq(self
.in_tot
[3:]),
409 self
.out_of
.m0
.eq(self
.in_tot
[3]),
410 self
.out_of
.guard
.eq(self
.in_tot
[2]),
411 self
.out_of
.round_bit
.eq(self
.in_tot
[1]),
412 self
.out_of
.sticky
.eq(self
.in_tot
[0])
417 class FPAddStage1(FPState
):
419 def __init__(self
, width
):
420 FPState
.__init
__(self
, "add_1")
421 self
.mod
= FPAddStage1Mod(width
)
422 self
.out_z
= FPNumBase(width
, False)
423 self
.out_of
= Overflow()
426 #m.d.sync += self.of.copy(self.out_of)
427 m
.d
.sync
+= self
.z
.copy(self
.out_z
)
428 m
.next
= "normalise_1"
433 def __init__(self
, width
):
434 self
.out_norm
= Signal(reset_less
=True)
435 self
.in_z
= FPNumBase(width
, False)
436 self
.out_z
= FPNumBase(width
, False)
437 self
.in_of
= Overflow()
438 self
.out_of
= Overflow()
440 def setup(self
, m
, in_z
, out_z
, in_of
, out_of
, out_norm
):
441 """ links module to inputs and outputs
443 m
.d
.comb
+= self
.in_z
.copy(in_z
)
444 m
.d
.comb
+= out_z
.copy(self
.out_z
)
445 m
.d
.comb
+= self
.in_of
.copy(in_of
)
446 m
.d
.comb
+= out_of
.copy(self
.out_of
)
447 m
.d
.comb
+= out_norm
.eq(self
.out_norm
)
449 def elaborate(self
, platform
):
451 m
.submodules
.norm1_in_overflow
= self
.in_of
452 m
.submodules
.norm1_out_overflow
= self
.out_of
453 m
.submodules
.norm1_in_z
= self
.in_z
454 m
.submodules
.norm1_out_z
= self
.out_z
455 m
.d
.comb
+= self
.out_z
.copy(self
.in_z
)
456 m
.d
.comb
+= self
.out_of
.copy(self
.in_of
)
457 m
.d
.comb
+= self
.out_norm
.eq((self
.in_z
.m_msbzero
) & \
458 (self
.in_z
.exp_gt_n126
))
459 with m
.If(self
.out_norm
):
461 self
.out_z
.e
.eq(self
.in_z
.e
- 1), # DECREASE exponent
462 self
.out_z
.m
.eq(self
.in_z
.m
<< 1), # shift mantissa UP
463 self
.out_z
.m
[0].eq(self
.in_of
.guard
), # steal guard (was tot[2])
464 self
.out_of
.guard
.eq(self
.in_of
.round_bit
), # round (was tot[1])
465 self
.out_of
.round_bit
.eq(0), # reset round bit
466 self
.out_of
.m0
.eq(self
.in_of
.guard
),
472 class FPNorm1(FPState
):
474 def __init__(self
, width
):
475 FPState
.__init
__(self
, "normalise_1")
476 self
.mod
= FPNorm1Mod(width
)
477 self
.out_norm
= Signal(reset_less
=True)
478 self
.out_z
= FPNumBase(width
)
479 self
.out_of
= Overflow()
482 #m.d.sync += self.of.copy(self.out_of)
483 m
.d
.sync
+= self
.z
.copy(self
.out_z
)
484 with m
.If(~self
.out_norm
):
485 m
.next
= "normalise_2"
490 def __init__(self
, width
):
491 self
.out_norm
= Signal(reset_less
=True)
492 self
.in_z
= FPNumBase(width
, False)
493 self
.out_z
= FPNumBase(width
, False)
494 self
.in_of
= Overflow()
495 self
.out_of
= Overflow()
497 def setup(self
, m
, in_z
, out_z
, in_of
, out_of
, out_norm
):
498 """ links module to inputs and outputs
500 m
.d
.comb
+= self
.in_z
.copy(in_z
)
501 m
.d
.comb
+= out_z
.copy(self
.out_z
)
502 m
.d
.comb
+= self
.in_of
.copy(in_of
)
503 m
.d
.comb
+= out_of
.copy(self
.out_of
)
504 m
.d
.comb
+= out_norm
.eq(self
.out_norm
)
506 def elaborate(self
, platform
):
508 m
.submodules
.norm2_in_overflow
= self
.in_of
509 m
.submodules
.norm2_out_overflow
= self
.out_of
510 m
.submodules
.norm2_in_z
= self
.in_z
511 m
.submodules
.norm2_out_z
= self
.out_z
512 m
.d
.comb
+= self
.out_z
.copy(self
.in_z
)
513 m
.d
.comb
+= self
.out_of
.copy(self
.in_of
)
514 m
.d
.comb
+= self
.out_norm
.eq(self
.in_z
.exp_lt_n126
)
515 with m
.If(self
.out_norm
):
517 self
.out_z
.e
.eq(self
.in_z
.e
+ 1), # INCREASE exponent
518 self
.out_z
.m
.eq(self
.in_z
.m
>> 1), # shift mantissa DOWN
519 self
.out_of
.guard
.eq(self
.in_z
.m
[0]),
520 self
.out_of
.m0
.eq(self
.in_z
.m
[1]),
521 self
.out_of
.round_bit
.eq(self
.in_of
.guard
),
522 self
.out_of
.sticky
.eq(self
.in_of
.sticky | self
.in_of
.round_bit
)
528 class FPNorm2(FPState
):
530 def __init__(self
, width
):
531 FPState
.__init
__(self
, "normalise_2")
532 self
.mod
= FPNorm2Mod(width
)
533 self
.out_norm
= Signal(reset_less
=True)
534 self
.out_z
= FPNumBase(width
)
535 self
.out_of
= Overflow()
538 m
.submodules
.norm_of
= self
.out_of
539 #m.d.sync += self.of.copy(self.out_of)
540 m
.d
.sync
+= self
.z
.copy(self
.out_z
)
541 with m
.If(~self
.out_norm
):
547 def __init__(self
, width
):
548 self
.in_roundz
= Signal(reset_less
=True)
549 self
.in_z
= FPNumBase(width
, False)
550 self
.out_z
= FPNumBase(width
, False)
552 def setup(self
, m
, in_z
, out_z
, in_of
):
553 """ links module to inputs and outputs
555 m
.d
.comb
+= self
.in_z
.copy(in_z
)
556 m
.d
.comb
+= out_z
.copy(self
.out_z
)
557 m
.d
.comb
+= self
.in_roundz
.eq(in_of
.roundz
)
559 def elaborate(self
, platform
):
561 m
.d
.comb
+= self
.out_z
.copy(self
.in_z
)
562 m
.submodules
.round_in_z
= self
.in_z
563 m
.submodules
.round_out_z
= self
.out_z
564 with m
.If(self
.in_roundz
):
565 m
.d
.comb
+= self
.out_z
.m
.eq(self
.in_z
.m
+ 1) # mantissa rounds up
566 with m
.If(self
.in_z
.m
== self
.in_z
.m1s
): # all 1s
567 m
.d
.comb
+= self
.out_z
.e
.eq(self
.in_z
.e
+ 1) # exponent up
571 class FPRound(FPState
):
573 def __init__(self
, width
):
574 FPState
.__init
__(self
, "round")
575 self
.mod
= FPRoundMod(width
)
576 self
.out_z
= FPNumBase(width
)
579 m
.d
.sync
+= self
.z
.copy(self
.out_z
)
580 m
.next
= "corrections"
583 class FPCorrectionsMod
:
585 def __init__(self
, width
):
586 self
.in_z
= FPNumOut(width
, False)
587 self
.out_z
= FPNumOut(width
, False)
589 def setup(self
, m
, in_z
, out_z
):
590 """ links module to inputs and outputs
592 m
.d
.comb
+= self
.in_z
.copy(in_z
)
593 m
.d
.comb
+= out_z
.copy(self
.out_z
)
595 def elaborate(self
, platform
):
597 m
.submodules
.corr_in_z
= self
.in_z
598 m
.submodules
.corr_out_z
= self
.out_z
599 m
.d
.comb
+= self
.out_z
.copy(self
.in_z
)
600 with m
.If(self
.in_z
.is_denormalised
):
601 m
.d
.comb
+= self
.out_z
.e
.eq(self
.in_z
.N127
)
603 # with m.If(self.in_z.is_overflowed):
604 # m.d.comb += self.out_z.inf(self.in_z.s)
606 # m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
610 class FPCorrections(FPState
):
612 def __init__(self
, width
):
613 FPState
.__init
__(self
, "corrections")
614 self
.mod
= FPCorrectionsMod(width
)
615 self
.out_z
= FPNumBase(width
)
618 m
.d
.sync
+= self
.z
.copy(self
.out_z
)
624 def __init__(self
, width
):
625 self
.in_z
= FPNumOut(width
, False)
626 self
.out_z
= FPNumOut(width
, False)
628 def setup(self
, m
, in_z
, out_z
):
629 """ links module to inputs and outputs
631 m
.d
.comb
+= self
.in_z
.copy(in_z
)
632 m
.d
.comb
+= out_z
.v
.eq(self
.out_z
.v
)
634 def elaborate(self
, platform
):
636 m
.submodules
.pack_in_z
= self
.in_z
637 with m
.If(self
.in_z
.is_overflowed
):
638 m
.d
.comb
+= self
.out_z
.inf(self
.in_z
.s
)
640 m
.d
.comb
+= self
.out_z
.create(self
.in_z
.s
, self
.in_z
.e
, self
.in_z
.m
)
644 class FPPack(FPState
):
646 def __init__(self
, width
):
647 FPState
.__init
__(self
, "pack")
648 self
.mod
= FPPackMod(width
)
649 self
.out_z
= FPNumOut(width
, False)
652 m
.d
.sync
+= self
.z
.v
.eq(self
.out_z
.v
)
656 class FPPutZ(FPState
):
659 self
.put_z(m
, self
.z
, self
.out_z
, "get_a")
664 def __init__(self
, width
, single_cycle
=False):
666 self
.single_cycle
= single_cycle
668 self
.in_a
= FPOp(width
)
669 self
.in_b
= FPOp(width
)
670 self
.out_z
= FPOp(width
)
674 def add_state(self
, state
):
675 self
.states
.append(state
)
678 def get_fragment(self
, platform
=None):
679 """ creates the HDL code-fragment for FPAdd
684 #a = FPNumIn(self.in_a, self.width)
685 b
= FPNumIn(self
.in_b
, self
.width
)
686 z
= FPNumOut(self
.width
, False)
688 m
.submodules
.fpnum_b
= b
689 m
.submodules
.fpnum_z
= z
693 geta
= self
.add_state(FPGetOpA(self
.in_a
, self
.width
))
694 #geta.set_inputs({"in_a": self.in_a})
695 #geta.set_outputs({"a": a})
697 # XXX m.d.comb += a.v.eq(self.in_a.v) # links in_a to a
698 m
.submodules
.fpnum_a
= a
700 getb
= self
.add_state(FPGetOpB("get_b"))
701 getb
.set_inputs({"in_b": self
.in_b
})
702 getb
.set_outputs({"b": b
})
703 # XXX m.d.comb += b.v.eq(self.in_b.v) # links in_b to b
705 sc
= self
.add_state(FPAddSpecialCases(self
.width
))
706 sc
.set_inputs({"a": a
, "b": b
})
707 sc
.set_outputs({"z": z
})
708 sc
.mod
.setup(m
, a
, b
, sc
.out_z
, sc
.out_do_z
)
709 m
.submodules
.specialcases
= sc
.mod
711 dn
= self
.add_state(FPAddDeNorm("denormalise"))
712 dn
.set_inputs({"a": a
, "b": b
})
713 dn
.set_outputs({"a": a
, "b": b
}) # XXX outputs same as inputs
715 if self
.single_cycle
:
716 alm
= self
.add_state(FPAddAlignSingle(self
.width
))
717 alm
.set_inputs({"a": a
, "b": b
})
718 alm
.set_outputs({"a": a
, "b": b
}) # XXX outputs same as inputs
719 alm
.mod
.setup(m
, a
, b
, alm
.out_a
, alm
.out_b
)
721 alm
= self
.add_state(FPAddAlignMulti(self
.width
))
722 alm
.set_inputs({"a": a
, "b": b
})
723 alm
.set_outputs({"a": a
, "b": b
}) # XXX outputs same as inputs
724 alm
.mod
.setup(m
, a
, b
, alm
.out_a
, alm
.out_b
, alm
.exp_eq
)
725 m
.submodules
.align
= alm
.mod
727 add0
= self
.add_state(FPAddStage0(self
.width
))
728 add0
.set_inputs({"a": a
, "b": b
})
729 add0
.set_outputs({"z": z
})
730 add0
.mod
.setup(m
, a
, b
, z
, add0
.out_z
, add0
.out_tot
)
731 m
.submodules
.add0
= add0
.mod
733 add1
= self
.add_state(FPAddStage1(self
.width
))
734 add1
.set_inputs({"tot": add0
.out_tot
, "z": add0
.out_z
})
735 add1
.set_outputs({"z": z
}) # XXX Z as output
736 add1
.mod
.setup(m
, add0
.out_tot
, add0
.out_z
, add1
.out_z
, add1
.out_of
)
737 m
.submodules
.add1
= add1
.mod
739 n1
= self
.add_state(FPNorm1(self
.width
))
740 n1
.set_inputs({"z": z
, "of": add1
.out_of
}) # XXX Z as output
741 n1
.set_outputs({"z": z
}) # XXX Z as output
742 n1
.mod
.setup(m
, z
, n1
.out_z
, add1
.out_of
, n1
.out_of
, n1
.out_norm
)
743 m
.submodules
.normalise_1
= n1
.mod
745 n2
= self
.add_state(FPNorm2(self
.width
))
746 n2
.set_inputs({"z": n1
.out_z
, "of": n1
.out_of
})
747 n2
.set_outputs({"z": z
})
748 n2
.mod
.setup(m
, n1
.out_z
, n2
.out_z
, n1
.out_of
, n2
.out_of
, n2
.out_norm
)
749 m
.submodules
.normalise_2
= n2
.mod
751 rn
= self
.add_state(FPRound(self
.width
))
752 rn
.set_inputs({"z": n2
.out_z
, "of": n2
.out_of
})
753 rn
.set_outputs({"z": z
})
754 rn
.mod
.setup(m
, n2
.out_z
, rn
.out_z
, n2
.out_of
)
755 m
.submodules
.roundz
= rn
.mod
757 cor
= self
.add_state(FPCorrections(self
.width
))
758 cor
.set_inputs({"z": rn
.out_z
}) # XXX Z as output
759 cor
.set_outputs({"z": z
}) # XXX Z as output
760 cor
.mod
.setup(m
, z
, cor
.out_z
)
761 m
.submodules
.corrections
= cor
.mod
763 pa
= self
.add_state(FPPack(self
.width
))
764 pa
.set_inputs({"z": cor
.out_z
}) # XXX Z as output
765 pa
.set_outputs({"z": z
}) # XXX Z as output
766 pa
.mod
.setup(m
, cor
.out_z
, pa
.out_z
)
767 m
.submodules
.pack
= pa
.mod
769 pz
= self
.add_state(FPPutZ("put_z"))
770 pz
.set_inputs({"z": z
})
771 pz
.set_outputs({"out_z": self
.out_z
})
775 for state
in self
.states
:
776 with m
.State(state
.state_from
):
782 if __name__
== "__main__":
783 alu
= FPADD(width
=32)
784 main(alu
, ports
=alu
.in_a
.ports() + alu
.in_b
.ports() + alu
.out_z
.ports())
787 # works... but don't use, just do "python fname.py convert -t v"
788 #print (verilog.convert(alu, ports=[
789 # ports=alu.in_a.ports() + \
790 # alu.in_b.ports() + \