src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat
   6 from nmigen.cli import main, verilog
   7
   8 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase
   9
  10
  11 class FPState(FPBase):
  12     def __init__(self, state_from):
  13         self.state_from = state_from
  14
  15     def set_inputs(self, inputs):
  16         self.inputs = inputs
  17         for k,v in inputs.items():
  18             setattr(self, k, v)
  19
  20     def set_outputs(self, outputs):
  21         self.outputs = outputs
  22         for k,v in outputs.items():
  23             setattr(self, k, v)
  24
  25
  26 class FPGetOpA(FPState):
  27
  28     def action(self, m):
  29         self.get_op(m, self.in_a, self.a, "get_b")
  30
  31
  32 class FPGetOpB(FPState):
  33
  34     def action(self, m):
  35         self.get_op(m, self.in_b, self.b, "special_cases")
  36
  37
  38 class FPAddSpecialCases(FPState):
  39
  40     def action(self, m):
  41         s_nomatch = Signal()
  42         m.d.comb += s_nomatch.eq(self.a.s != self.b.s)
  43
  44         m_match = Signal()
  45         m.d.comb += m_match.eq(self.a.m == self.b.m)
  46
  47         # if a is NaN or b is NaN return NaN
  48         with m.If(self.a.is_nan | self.b.is_nan):
  49             m.next = "put_z"
  50             m.d.sync += self.z.nan(1)
  51
  52         # XXX WEIRDNESS for FP16 non-canonical NaN handling
  53         # under review
  54
  55         ## if a is zero and b is NaN return -b
  56         #with m.If(a.is_zero & (a.s==0) & b.is_nan):
  57         #    m.next = "put_z"
  58         #    m.d.sync += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
  59
  60         ## if b is zero and a is NaN return -a
  61         #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
  62         #    m.next = "put_z"
  63         #    m.d.sync += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
  64
  65         ## if a is -zero and b is NaN return -b
  66         #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
  67         #    m.next = "put_z"
  68         #    m.d.sync += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
  69
  70         ## if b is -zero and a is NaN return -a
  71         #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
  72         #    m.next = "put_z"
  73         #    m.d.sync += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
  74
  75         # if a is inf return inf (or NaN)
  76         with m.Elif(self.a.is_inf):
  77             m.next = "put_z"
  78             m.d.sync += self.z.inf(self.a.s)
  79             # if a is inf and signs don't match return NaN
  80             with m.If(self.b.exp_128 & s_nomatch):
  81                 m.d.sync += self.z.nan(1)
  82
  83         # if b is inf return inf
  84         with m.Elif(self.b.is_inf):
  85             m.next = "put_z"
  86             m.d.sync += self.z.inf(self.b.s)
  87
  88         # if a is zero and b zero return signed-a/b
  89         with m.Elif(self.a.is_zero & self.b.is_zero):
  90             m.next = "put_z"
  91             m.d.sync += self.z.create(self.a.s & self.b.s, self.b.e,
  92                                       self.b.m[3:-1])
  93
  94         # if a is zero return b
  95         with m.Elif(self.a.is_zero):
  96             m.next = "put_z"
  97             m.d.sync += self.z.create(self.b.s, self.b.e, self.b.m[3:-1])
  98
  99         # if b is zero return a
 100         with m.Elif(self.b.is_zero):
 101             m.next = "put_z"
 102             m.d.sync += self.z.create(self.a.s, self.a.e, self.a.m[3:-1])
 103
 104         # if a equal to -b return zero (+ve zero)
 105         with m.Elif(s_nomatch & m_match & (self.a.e == self.b.e)):
 106             m.next = "put_z"
 107             m.d.sync += self.z.zero(0)
 108
 109         # Denormalised Number checks
 110         with m.Else():
 111             m.next = "denormalise"
 112
 113
 114 class FPADD(FPBase):
 115
 116     def __init__(self, width, single_cycle=False):
 117         FPBase.__init__(self)
 118         self.width = width
 119         self.single_cycle = single_cycle
 120
 121         self.in_a  = FPOp(width)
 122         self.in_b  = FPOp(width)
 123         self.out_z = FPOp(width)
 124
 125     def get_fragment(self, platform=None):
 126         """ creates the HDL code-fragment for FPAdd
 127         """
 128         m = Module()
 129
 130         # Latches
 131         a = FPNumIn(self.in_a, self.width)
 132         b = FPNumIn(self.in_b, self.width)
 133         z = FPNumOut(self.width, False)
 134
 135         m.submodules.fpnum_a = a
 136         m.submodules.fpnum_b = b
 137         m.submodules.fpnum_z = z
 138
 139         w = z.m_width + 4
 140         tot = Signal(w, reset_less=True) # sticky/round/guard, {mantissa} result, 1 overflow
 141
 142         of = Overflow()
 143         m.submodules.overflow = of
 144
 145         geta = FPGetOpA("get_a")
 146         geta.set_inputs({"in_a": self.in_a})
 147         geta.set_outputs({"a": a})
 148         m.d.comb += a.v.eq(self.in_a.v) # links in_a to a
 149
 150         getb = FPGetOpB("get_b")
 151         getb.set_inputs({"in_b": self.in_b})
 152         getb.set_outputs({"b": b})
 153         m.d.comb += b.v.eq(self.in_b.v) # links in_b to b
 154
 155         sc = FPAddSpecialCases("special_cases")
 156         sc.set_inputs({"a": a, "b": b})
 157         sc.set_outputs({"z": z})
 158
 159         with m.FSM() as fsm:
 160
 161             # ******
 162             # gets operand a
 163
 164             with m.State("get_a"):
 165                 geta.action(m)
 166
 167             # ******
 168             # gets operand b
 169
 170             with m.State("get_b"):
 171                 #self.get_op(m, self.in_b, b, "special_cases")
 172                 getb.action(m)
 173
 174             # ******
 175             # special cases: NaNs, infs, zeros, denormalised
 176             # NOTE: some of these are unique to add.  see "Special Operations"
 177             # https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 178
 179             with m.State("special_cases"):
 180                 sc.action(m)
 181
 182             # ******
 183             # denormalise.
 184
 185             with m.State("denormalise"):
 186                 # Denormalised Number checks
 187                 m.next = "align"
 188                 self.denormalise(m, a)
 189                 self.denormalise(m, b)
 190
 191             # ******
 192             # align.
 193
 194             with m.State("align"):
 195                 if not self.single_cycle:
 196                     # NOTE: this does *not* do single-cycle multi-shifting,
 197                     #       it *STAYS* in the align state until exponents match
 198
 199                     # exponent of a greater than b: shift b down
 200                     with m.If(a.e > b.e):
 201                         m.d.sync += b.shift_down()
 202                     # exponent of b greater than a: shift a down
 203                     with m.Elif(a.e < b.e):
 204                         m.d.sync += a.shift_down()
 205                     # exponents equal: move to next stage.
 206                     with m.Else():
 207                         m.next = "add_0"
 208                 else:
 209                     # This one however (single-cycle) will do the shift
 210                     # in one go.
 211
 212                     # XXX TODO: the shifter used here is quite expensive
 213                     # having only one would be better
 214
 215                     ediff = Signal((len(a.e), True), reset_less=True)
 216                     ediffr = Signal((len(a.e), True), reset_less=True)
 217                     m.d.comb += ediff.eq(a.e - b.e)
 218                     m.d.comb += ediffr.eq(b.e - a.e)
 219                     with m.If(ediff > 0):
 220                         m.d.sync += b.shift_down_multi(ediff)
 221                     # exponent of b greater than a: shift a down
 222                     with m.Elif(ediff < 0):
 223                         m.d.sync += a.shift_down_multi(ediffr)
 224
 225                     m.next = "add_0"
 226
 227             # ******
 228             # First stage of add.  covers same-sign (add) and subtract
 229             # special-casing when mantissas are greater or equal, to
 230             # give greatest accuracy.
 231
 232             with m.State("add_0"):
 233                 m.next = "add_1"
 234                 m.d.sync += z.e.eq(a.e)
 235                 # same-sign (both negative or both positive) add mantissas
 236                 with m.If(a.s == b.s):
 237                     m.d.sync += [
 238                         tot.eq(Cat(a.m, 0) + Cat(b.m, 0)),
 239                         z.s.eq(a.s)
 240                     ]
 241                 # a mantissa greater than b, use a
 242                 with m.Elif(a.m >= b.m):
 243                     m.d.sync += [
 244                         tot.eq(Cat(a.m, 0) - Cat(b.m, 0)),
 245                         z.s.eq(a.s)
 246                     ]
 247                 # b mantissa greater than a, use b
 248                 with m.Else():
 249                     m.d.sync += [
 250                         tot.eq(Cat(b.m, 0) - Cat(a.m, 0)),
 251                         z.s.eq(b.s)
 252                 ]
 253
 254             # ******
 255             # Second stage of add: preparation for normalisation.
 256             # detects when tot sum is too big (tot[27] is kinda a carry bit)
 257
 258             with m.State("add_1"):
 259                 m.next = "normalise_1"
 260                 # tot[27] gets set when the sum overflows. shift result down
 261                 with m.If(tot[-1]):
 262                     m.d.sync += [
 263                         z.m.eq(tot[4:]),
 264                         of.m0.eq(tot[4]),
 265                         of.guard.eq(tot[3]),
 266                         of.round_bit.eq(tot[2]),
 267                         of.sticky.eq(tot[1] | tot[0]),
 268                         z.e.eq(z.e + 1)
 269                 ]
 270                 # tot[27] zero case
 271                 with m.Else():
 272                     m.d.sync += [
 273                         z.m.eq(tot[3:]),
 274                         of.m0.eq(tot[3]),
 275                         of.guard.eq(tot[2]),
 276                         of.round_bit.eq(tot[1]),
 277                         of.sticky.eq(tot[0])
 278                 ]
 279
 280             # ******
 281             # First stage of normalisation.
 282
 283             with m.State("normalise_1"):
 284                 self.normalise_1(m, z, of, "normalise_2")
 285
 286             # ******
 287             # Second stage of normalisation.
 288
 289             with m.State("normalise_2"):
 290                 self.normalise_2(m, z, of, "round")
 291
 292             # ******
 293             # rounding stage
 294
 295             with m.State("round"):
 296                 self.roundz(m, z, of, "corrections")
 297
 298             # ******
 299             # correction stage
 300
 301             with m.State("corrections"):
 302                 self.corrections(m, z, "pack")
 303
 304             # ******
 305             # pack stage
 306
 307             with m.State("pack"):
 308                 self.pack(m, z, "put_z")
 309
 310             # ******
 311             # put_z stage
 312
 313             with m.State("put_z"):
 314                 self.put_z(m, z, self.out_z, "get_a")
 315
 316         return m
 317
 318
 319 if __name__ == "__main__":
 320     alu = FPADD(width=32)
 321     main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
 322
 323
 324     # works... but don't use, just do "python fname.py convert -t v"
 325     #print (verilog.convert(alu, ports=[
 326     #                        ports=alu.in_a.ports() + \
 327     #                              alu.in_b.ports() + \
 328     #                              alu.out_z.ports())