src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat
   6 from nmigen.cli import main, verilog
   7
   8 from fpbase import FPNum, FPOp, Overflow, FPBase
   9
  10
  11 class FPADD(FPBase):
  12
  13     def __init__(self, width, single_cycle=False):
  14         FPBase.__init__(self)
  15         self.width = width
  16         self.single_cycle = single_cycle
  17
  18         self.in_a  = FPOp(width)
  19         self.in_b  = FPOp(width)
  20         self.out_z = FPOp(width)
  21
  22     def get_fragment(self, platform=None):
  23         """ creates the HDL code-fragment for FPAdd
  24         """
  25         m = Module()
  26
  27         # Latches
  28         a = FPNum(self.width)
  29         b = FPNum(self.width)
  30         z = FPNum(self.width, False)
  31
  32         m.submodules.fpnum_a = a
  33         m.submodules.fpnum_b = b
  34         m.submodules.fpnum_z = z
  35
  36         w = z.m_width + 4
  37         tot = Signal(w, reset_less=True) # sticky/round/guard, {mantissa} result, 1 overflow
  38
  39         of = Overflow()
  40
  41         with m.FSM() as fsm:
  42
  43             # ******
  44             # gets operand a
  45
  46             with m.State("get_a"):
  47                 self.get_op(m, self.in_a, a, "get_b")
  48
  49             # ******
  50             # gets operand b
  51
  52             with m.State("get_b"):
  53                 self.get_op(m, self.in_b, b, "special_cases")
  54
  55             # ******
  56             # special cases: NaNs, infs, zeros, denormalised
  57             # NOTE: some of these are unique to add.  see "Special Operations"
  58             # https://steve.hollasch.net/cgindex/coding/ieeefloat.html
  59
  60             with m.State("special_cases"):
  61
  62                 s_nomatch = Signal()
  63                 m.d.comb += s_nomatch.eq(a.s != b.s)
  64
  65                 m_match = Signal()
  66                 m.d.comb += m_match.eq(a.m == b.m)
  67
  68                 # if a is NaN or b is NaN return NaN
  69                 with m.If(a.is_nan | b.is_nan):
  70                     m.next = "put_z"
  71                     m.d.sync += z.nan(1)
  72
  73                 # XXX WEIRDNESS for FP16 non-canonical NaN handling
  74                 # under review
  75
  76                 ## if a is zero and b is NaN return -b
  77                 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
  78                 #    m.next = "put_z"
  79                 #    m.d.sync += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
  80
  81                 ## if b is zero and a is NaN return -a
  82                 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
  83                 #    m.next = "put_z"
  84                 #    m.d.sync += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
  85
  86                 ## if a is -zero and b is NaN return -b
  87                 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
  88                 #    m.next = "put_z"
  89                 #    m.d.sync += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
  90
  91                 ## if b is -zero and a is NaN return -a
  92                 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
  93                 #    m.next = "put_z"
  94                 #    m.d.sync += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
  95
  96                 # if a is inf return inf (or NaN)
  97                 with m.Elif(a.is_inf):
  98                     m.next = "put_z"
  99                     m.d.sync += z.inf(a.s)
 100                     # if a is inf and signs don't match return NaN
 101                     with m.If(b.exp_128 & s_nomatch):
 102                         m.d.sync += z.nan(1)
 103
 104                 # if b is inf return inf
 105                 with m.Elif(b.is_inf):
 106                     m.next = "put_z"
 107                     m.d.sync += z.inf(b.s)
 108
 109                 # if a is zero and b zero return signed-a/b
 110                 with m.Elif(a.is_zero & b.is_zero):
 111                     m.next = "put_z"
 112                     m.d.sync += z.create(a.s & b.s, b.e, b.m[3:-1])
 113
 114                 # if a is zero return b
 115                 with m.Elif(a.is_zero):
 116                     m.next = "put_z"
 117                     m.d.sync += z.create(b.s, b.e, b.m[3:-1])
 118
 119                 # if b is zero return a
 120                 with m.Elif(b.is_zero):
 121                     m.next = "put_z"
 122                     m.d.sync += z.create(a.s, a.e, a.m[3:-1])
 123
 124                 # if a equal to -b return zero (+ve zero)
 125                 with m.Elif(s_nomatch & m_match & (a.e == b.e)):
 126                     m.next = "put_z"
 127                     m.d.sync += z.zero(0)
 128
 129                 # Denormalised Number checks
 130                 with m.Else():
 131                     m.next = "align"
 132                     self.denormalise(m, a)
 133                     self.denormalise(m, b)
 134
 135             # ******
 136             # align.
 137
 138             with m.State("align"):
 139                 if not self.single_cycle:
 140                     # NOTE: this does *not* do single-cycle multi-shifting,
 141                     #       it *STAYS* in the align state until exponents match
 142
 143                     # exponent of a greater than b: shift b down
 144                     with m.If(a.e > b.e):
 145                         m.d.sync += b.shift_down()
 146                     # exponent of b greater than a: shift a down
 147                     with m.Elif(a.e < b.e):
 148                         m.d.sync += a.shift_down()
 149                     # exponents equal: move to next stage.
 150                     with m.Else():
 151                         m.next = "add_0"
 152                 else:
 153                     # This one however (single-cycle) will do the shift
 154                     # in one go.
 155
 156                     # XXX TODO: the shifter used here is quite expensive
 157                     # having only one would be better
 158
 159                     ediff = Signal((len(a.e), True), reset_less=True)
 160                     ediffr = Signal((len(a.e), True), reset_less=True)
 161                     m.d.comb += ediff.eq(a.e - b.e)
 162                     m.d.comb += ediffr.eq(b.e - a.e)
 163                     with m.If(ediff > 0):
 164                         m.d.sync += b.shift_down_multi(ediff)
 165                     # exponent of b greater than a: shift a down
 166                     with m.Elif(ediff < 0):
 167                         m.d.sync += a.shift_down_multi(ediffr)
 168
 169                     m.next = "add_0"
 170
 171             # ******
 172             # First stage of add.  covers same-sign (add) and subtract
 173             # special-casing when mantissas are greater or equal, to
 174             # give greatest accuracy.
 175
 176             with m.State("add_0"):
 177                 m.next = "add_1"
 178                 m.d.sync += z.e.eq(a.e)
 179                 # same-sign (both negative or both positive) add mantissas
 180                 with m.If(a.s == b.s):
 181                     m.d.sync += [
 182                         tot.eq(Cat(a.m, 0) + Cat(b.m, 0)),
 183                         z.s.eq(a.s)
 184                     ]
 185                 # a mantissa greater than b, use a
 186                 with m.Elif(a.m >= b.m):
 187                     m.d.sync += [
 188                         tot.eq(Cat(a.m, 0) - Cat(b.m, 0)),
 189                         z.s.eq(a.s)
 190                     ]
 191                 # b mantissa greater than a, use b
 192                 with m.Else():
 193                     m.d.sync += [
 194                         tot.eq(Cat(b.m, 0) - Cat(a.m, 0)),
 195                         z.s.eq(b.s)
 196                 ]
 197
 198             # ******
 199             # Second stage of add: preparation for normalisation.
 200             # detects when tot sum is too big (tot[27] is kinda a carry bit)
 201
 202             with m.State("add_1"):
 203                 m.next = "normalise_1"
 204                 # tot[27] gets set when the sum overflows. shift result down
 205                 with m.If(tot[-1]):
 206                     m.d.sync += [
 207                         z.m.eq(tot[4:]),
 208                         of.guard.eq(tot[3]),
 209                         of.round_bit.eq(tot[2]),
 210                         of.sticky.eq(tot[1] | tot[0]),
 211                         z.e.eq(z.e + 1)
 212                 ]
 213                 # tot[27] zero case
 214                 with m.Else():
 215                     m.d.sync += [
 216                         z.m.eq(tot[3:]),
 217                         of.guard.eq(tot[2]),
 218                         of.round_bit.eq(tot[1]),
 219                         of.sticky.eq(tot[0])
 220                 ]
 221
 222             # ******
 223             # First stage of normalisation.
 224
 225             with m.State("normalise_1"):
 226                 self.normalise_1(m, z, of, "normalise_2")
 227
 228             # ******
 229             # Second stage of normalisation.
 230
 231             with m.State("normalise_2"):
 232                 self.normalise_2(m, z, of, "round")
 233
 234             # ******
 235             # rounding stage
 236
 237             with m.State("round"):
 238                 self.roundz(m, z, of, "corrections")
 239
 240             # ******
 241             # correction stage
 242
 243             with m.State("corrections"):
 244                 self.corrections(m, z, "pack")
 245
 246             # ******
 247             # pack stage
 248
 249             with m.State("pack"):
 250                 self.pack(m, z, "put_z")
 251
 252             # ******
 253             # put_z stage
 254
 255             with m.State("put_z"):
 256                 self.put_z(m, z, self.out_z, "get_a")
 257
 258         return m
 259
 260
 261 if __name__ == "__main__":
 262     alu = FPADD(width=32)
 263     main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
 264
 265
 266     # works... but don't use, just do "python fname.py convert -t v"
 267     #print (verilog.convert(alu, ports=[
 268     #                        ports=alu.in_a.ports() + \
 269     #                              alu.in_b.ports() + \
 270     #                              alu.out_z.ports())