src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat, Mux, Array, Const
   6 from nmigen.lib.coding import PriorityEncoder
   7 from nmigen.cli import main, verilog
   8 from math import log
   9
  10 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
  11 from fpbase import MultiShiftRMerge, Trigger
  12 #from fpbase import FPNumShiftMultiRight
  13
  14
  15 class FPState(FPBase):
  16     def __init__(self, state_from):
  17         self.state_from = state_from
  18
  19     def set_inputs(self, inputs):
  20         self.inputs = inputs
  21         for k,v in inputs.items():
  22             setattr(self, k, v)
  23
  24     def set_outputs(self, outputs):
  25         self.outputs = outputs
  26         for k,v in outputs.items():
  27             setattr(self, k, v)
  28
  29
  30 class FPGetSyncOpsMod:
  31     def __init__(self, width, num_ops=2):
  32         self.width = width
  33         self.num_ops = num_ops
  34         inops = []
  35         outops = []
  36         for i in range(num_ops):
  37             inops.append(Signal(width, reset_less=True))
  38             outops.append(Signal(width, reset_less=True))
  39         self.in_op = inops
  40         self.out_op = outops
  41         self.stb = Signal(num_ops)
  42         self.ack = Signal()
  43         self.ready = Signal(reset_less=True)
  44         self.out_decode = Signal(reset_less=True)
  45
  46     def elaborate(self, platform):
  47         m = Module()
  48         m.d.comb += self.ready.eq(self.stb == Const(-1, (self.num_ops, False)))
  49         m.d.comb += self.out_decode.eq(self.ack & self.ready)
  50         with m.If(self.out_decode):
  51             for i in range(self.num_ops):
  52                 m.d.comb += [
  53                         self.out_op[i].eq(self.in_op[i]),
  54                 ]
  55         return m
  56
  57     def ports(self):
  58         return self.in_op + self.out_op + [self.stb, self.ack]
  59
  60
  61 class FPOps(Trigger):
  62     def __init__(self, width, num_ops):
  63         Trigger.__init__(self)
  64         self.width = width
  65         self.num_ops = num_ops
  66
  67         res = []
  68         for i in range(num_ops):
  69             res.append(Signal(width))
  70         self.v  = Array(res)
  71
  72     def ports(self):
  73         res = []
  74         for i in range(self.num_ops):
  75             res.append(self.v[i])
  76         res.append(self.ack)
  77         res.append(self.stb)
  78         return res
  79
  80
  81 class InputGroup:
  82     def __init__(self, width, num_ops=2, num_rows=4):
  83         self.width = width
  84         self.num_ops = num_ops
  85         self.num_rows = num_rows
  86         self.mmax = int(log(self.num_rows) / log(2))
  87         self.rs = []
  88         self.mid = Signal(self.mmax, reset_less=True) # multiplex id
  89         for i in range(num_rows):
  90             self.rs.append(FPGetSyncOpsMod(width, num_ops))
  91         self.rs = Array(self.rs)
  92
  93         self.out_op = FPOps(width, num_ops)
  94
  95     def elaborate(self, platform):
  96         m = Module()
  97
  98         pe = PriorityEncoder(self.num_rows)
  99         m.submodules.selector = pe
 100         m.submodules.out_op = self.out_op
 101         m.submodules += self.rs
 102
 103         # connect priority encoder
 104         in_ready = []
 105         for i in range(self.num_rows):
 106             in_ready.append(self.rs[i].ready)
 107         m.d.comb += pe.i.eq(Cat(*in_ready))
 108
 109         active = Signal(reset_less=True)
 110         out_en = Signal(reset_less=True)
 111         m.d.comb += active.eq(~pe.n) # encoder active
 112         m.d.comb += out_en.eq(active & self.out_op.trigger)
 113
 114         # encoder active: ack relevant input, record MID, pass output
 115         with m.If(out_en):
 116             rs = self.rs[pe.o]
 117             m.d.sync += self.mid.eq(pe.o)
 118             m.d.sync += rs.ack.eq(0)
 119             m.d.sync += self.out_op.stb.eq(0)
 120             for j in range(self.num_ops):
 121                 m.d.sync += self.out_op.v[j].eq(rs.out_op[j])
 122         with m.Else():
 123             m.d.sync += self.out_op.stb.eq(1)
 124             # acks all default to zero
 125             for i in range(self.num_rows):
 126                 m.d.sync += self.rs[i].ack.eq(1)
 127
 128         return m
 129
 130     def ports(self):
 131         res = []
 132         for i in range(self.num_rows):
 133             inop = self.rs[i]
 134             res += inop.in_op + [inop.stb]
 135         return self.out_op.ports() + res + [self.mid]
 136
 137
 138 class FPGetOpMod:
 139     def __init__(self, width):
 140         self.in_op = FPOp(width)
 141         self.out_op = Signal(width)
 142         self.out_decode = Signal(reset_less=True)
 143
 144     def elaborate(self, platform):
 145         m = Module()
 146         m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
 147         m.submodules.get_op_in = self.in_op
 148         #m.submodules.get_op_out = self.out_op
 149         with m.If(self.out_decode):
 150             m.d.comb += [
 151                 self.out_op.eq(self.in_op.v),
 152             ]
 153         return m
 154
 155
 156 class FPGetOp(FPState):
 157     """ gets operand
 158     """
 159
 160     def __init__(self, in_state, out_state, in_op, width):
 161         FPState.__init__(self, in_state)
 162         self.out_state = out_state
 163         self.mod = FPGetOpMod(width)
 164         self.in_op = in_op
 165         self.out_op = Signal(width)
 166         self.out_decode = Signal(reset_less=True)
 167
 168     def setup(self, m, in_op):
 169         """ links module to inputs and outputs
 170         """
 171         setattr(m.submodules, self.state_from, self.mod)
 172         m.d.comb += self.mod.in_op.eq(in_op)
 173         #m.d.comb += self.out_op.eq(self.mod.out_op)
 174         m.d.comb += self.out_decode.eq(self.mod.out_decode)
 175
 176     def action(self, m):
 177         with m.If(self.out_decode):
 178             m.next = self.out_state
 179             m.d.sync += [
 180                 self.in_op.ack.eq(0),
 181                 self.out_op.eq(self.mod.out_op)
 182             ]
 183         with m.Else():
 184             m.d.sync += self.in_op.ack.eq(1)
 185
 186
 187 class FPGet2OpMod(Trigger):
 188     def __init__(self, width, id_wid):
 189         Trigger.__init__(self)
 190         self.width = width
 191         self.id_wid = id_wid
 192         self.i = self.ispec()
 193         self.o = self.ospec()
 194
 195     def ispec(self):
 196         return FPADDBaseData(self.width, self.id_wid)
 197
 198     def ospec(self):
 199         return FPNumBase2Ops(self.width, self.id_wid)
 200
 201     def elaborate(self, platform):
 202         m = Trigger.elaborate(self, platform)
 203         #m.submodules.get_op_in = self.in_op
 204         m.submodules.get_op1_out = self.o.a
 205         m.submodules.get_op2_out = self.o.b
 206         out_op1 = FPNumIn(None, self.width)
 207         out_op2 = FPNumIn(None, self.width)
 208         with m.If(self.trigger):
 209             m.d.comb += [
 210                 out_op1.decode(self.i.a),
 211                 out_op2.decode(self.i.b),
 212                 self.o.a.eq(out_op1),
 213                 self.o.b.eq(out_op2),
 214             ]
 215         return m
 216
 217
 218 class FPGet2Op(FPState):
 219     """ gets operands
 220     """
 221
 222     def __init__(self, in_state, out_state, in_op1, in_op2, width, id_wid):
 223         FPState.__init__(self, in_state)
 224         self.out_state = out_state
 225         self.mod = FPGet2OpMod(width, id_wid)
 226         self.in_op1 = in_op1
 227         self.in_op2 = in_op2
 228         self.o = self.mod.ospec()
 229         self.in_stb = Signal(reset_less=True)
 230         self.out_ack = Signal(reset_less=True)
 231         self.out_decode = Signal(reset_less=True)
 232
 233     def setup(self, m, in_op1, in_op2, in_stb, in_ack):
 234         """ links module to inputs and outputs
 235         """
 236         m.submodules.get_ops = self.mod
 237         m.d.comb += self.mod.i.a.eq(in_op1)
 238         m.d.comb += self.mod.i.b.eq(in_op2)
 239         m.d.comb += self.mod.stb.eq(in_stb)
 240         m.d.comb += self.out_ack.eq(self.mod.ack)
 241         m.d.comb += self.out_decode.eq(self.mod.trigger)
 242         m.d.comb += in_ack.eq(self.mod.ack)
 243
 244     def action(self, m):
 245         with m.If(self.out_decode):
 246             m.next = self.out_state
 247             m.d.sync += [
 248                 self.mod.ack.eq(0),
 249                 self.o.eq(self.mod.o),
 250             ]
 251         with m.Else():
 252             m.d.sync += self.mod.ack.eq(1)
 253
 254
 255 class FPNumBase2Ops:
 256
 257     def __init__(self, width, id_wid, m_extra=True):
 258         self.a = FPNumBase(width, m_extra)
 259         self.b = FPNumBase(width, m_extra)
 260         self.mid = Signal(id_wid, reset_less=True)
 261
 262     def eq(self, i):
 263         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 264
 265
 266 class FPAddSpecialCasesMod:
 267     """ special cases: NaNs, infs, zeros, denormalised
 268         NOTE: some of these are unique to add.  see "Special Operations"
 269         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 270     """
 271
 272     def __init__(self, width, id_wid):
 273         self.width = width
 274         self.id_wid = id_wid
 275         self.i = self.ispec()
 276         self.o = self.ospec()
 277         self.out_do_z = Signal(reset_less=True)
 278
 279     def ispec(self):
 280         return FPNumBase2Ops(self.width, self.id_wid)
 281
 282     def ospec(self):
 283         return FPPackData(self.width, self.id_wid)
 284
 285     def setup(self, m, i, out_do_z):
 286         """ links module to inputs and outputs
 287         """
 288         m.submodules.specialcases = self
 289         m.d.comb += self.i.eq(i)
 290         m.d.comb += out_do_z.eq(self.out_do_z)
 291
 292     def elaborate(self, platform):
 293         m = Module()
 294
 295         m.submodules.sc_in_a = self.i.a
 296         m.submodules.sc_in_b = self.i.b
 297         m.submodules.sc_out_z = self.o.z
 298
 299         s_nomatch = Signal()
 300         m.d.comb += s_nomatch.eq(self.i.a.s != self.i.b.s)
 301
 302         m_match = Signal()
 303         m.d.comb += m_match.eq(self.i.a.m == self.i.b.m)
 304
 305         # if a is NaN or b is NaN return NaN
 306         with m.If(self.i.a.is_nan | self.i.b.is_nan):
 307             m.d.comb += self.out_do_z.eq(1)
 308             m.d.comb += self.o.z.nan(0)
 309
 310         # XXX WEIRDNESS for FP16 non-canonical NaN handling
 311         # under review
 312
 313         ## if a is zero and b is NaN return -b
 314         #with m.If(a.is_zero & (a.s==0) & b.is_nan):
 315         #    m.d.comb += self.out_do_z.eq(1)
 316         #    m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
 317
 318         ## if b is zero and a is NaN return -a
 319         #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
 320         #    m.d.comb += self.out_do_z.eq(1)
 321         #    m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
 322
 323         ## if a is -zero and b is NaN return -b
 324         #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
 325         #    m.d.comb += self.out_do_z.eq(1)
 326         #    m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
 327
 328         ## if b is -zero and a is NaN return -a
 329         #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
 330         #    m.d.comb += self.out_do_z.eq(1)
 331         #    m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
 332
 333         # if a is inf return inf (or NaN)
 334         with m.Elif(self.i.a.is_inf):
 335             m.d.comb += self.out_do_z.eq(1)
 336             m.d.comb += self.o.z.inf(self.i.a.s)
 337             # if a is inf and signs don't match return NaN
 338             with m.If(self.i.b.exp_128 & s_nomatch):
 339                 m.d.comb += self.o.z.nan(0)
 340
 341         # if b is inf return inf
 342         with m.Elif(self.i.b.is_inf):
 343             m.d.comb += self.out_do_z.eq(1)
 344             m.d.comb += self.o.z.inf(self.i.b.s)
 345
 346         # if a is zero and b zero return signed-a/b
 347         with m.Elif(self.i.a.is_zero & self.i.b.is_zero):
 348             m.d.comb += self.out_do_z.eq(1)
 349             m.d.comb += self.o.z.create(self.i.a.s & self.i.b.s,
 350                                           self.i.b.e,
 351                                           self.i.b.m[3:-1])
 352
 353         # if a is zero return b
 354         with m.Elif(self.i.a.is_zero):
 355             m.d.comb += self.out_do_z.eq(1)
 356             m.d.comb += self.o.z.create(self.i.b.s, self.i.b.e,
 357                                       self.i.b.m[3:-1])
 358
 359         # if b is zero return a
 360         with m.Elif(self.i.b.is_zero):
 361             m.d.comb += self.out_do_z.eq(1)
 362             m.d.comb += self.o.z.create(self.i.a.s, self.i.a.e,
 363                                       self.i.a.m[3:-1])
 364
 365         # if a equal to -b return zero (+ve zero)
 366         with m.Elif(s_nomatch & m_match & (self.i.a.e == self.i.b.e)):
 367             m.d.comb += self.out_do_z.eq(1)
 368             m.d.comb += self.o.z.zero(0)
 369
 370         # Denormalised Number checks
 371         with m.Else():
 372             m.d.comb += self.out_do_z.eq(0)
 373
 374         return m
 375
 376
 377 class FPID:
 378     def __init__(self, id_wid):
 379         self.id_wid = id_wid
 380         if self.id_wid:
 381             self.in_mid = Signal(id_wid, reset_less=True)
 382             self.out_mid = Signal(id_wid, reset_less=True)
 383         else:
 384             self.in_mid = None
 385             self.out_mid = None
 386
 387     def idsync(self, m):
 388         if self.id_wid is not None:
 389             m.d.sync += self.out_mid.eq(self.in_mid)
 390
 391
 392 class FPAddSpecialCases(FPState, FPID):
 393     """ special cases: NaNs, infs, zeros, denormalised
 394         NOTE: some of these are unique to add.  see "Special Operations"
 395         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 396     """
 397
 398     def __init__(self, width, id_wid):
 399         FPState.__init__(self, "special_cases")
 400         FPID.__init__(self, id_wid)
 401         self.mod = FPAddSpecialCasesMod(width)
 402         self.out_z = self.mod.ospec()
 403         self.out_do_z = Signal(reset_less=True)
 404
 405     def setup(self, m, in_a, in_b, in_mid):
 406         """ links module to inputs and outputs
 407         """
 408         self.mod.setup(m, in_a, in_b, self.out_do_z)
 409         if self.in_mid is not None:
 410             m.d.comb += self.in_mid.eq(in_mid)
 411
 412     def action(self, m):
 413         self.idsync(m)
 414         with m.If(self.out_do_z):
 415             m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
 416             m.next = "put_z"
 417         with m.Else():
 418             m.next = "denormalise"
 419
 420
 421 class FPAddSpecialCasesDeNorm(FPState, FPID):
 422     """ special cases: NaNs, infs, zeros, denormalised
 423         NOTE: some of these are unique to add.  see "Special Operations"
 424         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 425     """
 426
 427     def __init__(self, width, id_wid):
 428         FPState.__init__(self, "special_cases")
 429         FPID.__init__(self, id_wid)
 430         self.smod = FPAddSpecialCasesMod(width, id_wid)
 431         self.out_z = self.smod.ospec()
 432         self.out_do_z = Signal(reset_less=True)
 433
 434         self.dmod = FPAddDeNormMod(width, id_wid)
 435         self.o = self.dmod.ospec()
 436
 437     def setup(self, m, i, in_mid):
 438         """ links module to inputs and outputs
 439         """
 440         self.smod.setup(m, i, self.out_do_z)
 441         self.dmod.setup(m, i)
 442         if self.in_mid is not None:
 443             m.d.comb += self.in_mid.eq(in_mid)
 444
 445     def action(self, m):
 446         self.idsync(m)
 447         with m.If(self.out_do_z):
 448             m.d.sync += self.out_z.z.v.eq(self.smod.o.z.v) # only take output
 449             m.next = "put_z"
 450         with m.Else():
 451             m.next = "align"
 452             m.d.sync += self.o.a.eq(self.dmod.o.a)
 453             m.d.sync += self.o.b.eq(self.dmod.o.b)
 454
 455
 456 class FPAddDeNormMod(FPState):
 457
 458     def __init__(self, width, id_wid):
 459         self.width = width
 460         self.id_wid = id_wid
 461         self.i = self.ispec()
 462         self.o = self.ospec()
 463
 464     def ispec(self):
 465         return FPNumBase2Ops(self.width, self.id_wid)
 466
 467     def ospec(self):
 468         return FPNumBase2Ops(self.width, self.id_wid)
 469
 470     def setup(self, m, i):
 471         """ links module to inputs and outputs
 472         """
 473         m.submodules.denormalise = self
 474         m.d.comb += self.i.eq(i)
 475
 476     def elaborate(self, platform):
 477         m = Module()
 478         m.submodules.denorm_in_a = self.i.a
 479         m.submodules.denorm_in_b = self.i.b
 480         m.submodules.denorm_out_a = self.o.a
 481         m.submodules.denorm_out_b = self.o.b
 482         # hmmm, don't like repeating identical code
 483         m.d.comb += self.o.a.eq(self.i.a)
 484         with m.If(self.i.a.exp_n127):
 485             m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
 486         with m.Else():
 487             m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
 488
 489         m.d.comb += self.o.b.eq(self.i.b)
 490         with m.If(self.i.b.exp_n127):
 491             m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
 492         with m.Else():
 493             m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
 494
 495         return m
 496
 497
 498 class FPAddDeNorm(FPState, FPID):
 499
 500     def __init__(self, width, id_wid):
 501         FPState.__init__(self, "denormalise")
 502         FPID.__init__(self, id_wid)
 503         self.mod = FPAddDeNormMod(width)
 504         self.out_a = FPNumBase(width)
 505         self.out_b = FPNumBase(width)
 506
 507     def setup(self, m, in_a, in_b, in_mid):
 508         """ links module to inputs and outputs
 509         """
 510         self.mod.setup(m, in_a, in_b)
 511         if self.in_mid is not None:
 512             m.d.comb += self.in_mid.eq(in_mid)
 513
 514     def action(self, m):
 515         self.idsync(m)
 516         # Denormalised Number checks
 517         m.next = "align"
 518         m.d.sync += self.out_a.eq(self.mod.out_a)
 519         m.d.sync += self.out_b.eq(self.mod.out_b)
 520
 521
 522 class FPAddAlignMultiMod(FPState):
 523
 524     def __init__(self, width):
 525         self.in_a = FPNumBase(width)
 526         self.in_b = FPNumBase(width)
 527         self.out_a = FPNumIn(None, width)
 528         self.out_b = FPNumIn(None, width)
 529         self.exp_eq = Signal(reset_less=True)
 530
 531     def elaborate(self, platform):
 532         # This one however (single-cycle) will do the shift
 533         # in one go.
 534
 535         m = Module()
 536
 537         m.submodules.align_in_a = self.in_a
 538         m.submodules.align_in_b = self.in_b
 539         m.submodules.align_out_a = self.out_a
 540         m.submodules.align_out_b = self.out_b
 541
 542         # NOTE: this does *not* do single-cycle multi-shifting,
 543         #       it *STAYS* in the align state until exponents match
 544
 545         # exponent of a greater than b: shift b down
 546         m.d.comb += self.exp_eq.eq(0)
 547         m.d.comb += self.out_a.eq(self.in_a)
 548         m.d.comb += self.out_b.eq(self.in_b)
 549         agtb = Signal(reset_less=True)
 550         altb = Signal(reset_less=True)
 551         m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
 552         m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
 553         with m.If(agtb):
 554             m.d.comb += self.out_b.shift_down(self.in_b)
 555         # exponent of b greater than a: shift a down
 556         with m.Elif(altb):
 557             m.d.comb += self.out_a.shift_down(self.in_a)
 558         # exponents equal: move to next stage.
 559         with m.Else():
 560             m.d.comb += self.exp_eq.eq(1)
 561         return m
 562
 563
 564 class FPAddAlignMulti(FPState, FPID):
 565
 566     def __init__(self, width, id_wid):
 567         FPID.__init__(self, id_wid)
 568         FPState.__init__(self, "align")
 569         self.mod = FPAddAlignMultiMod(width)
 570         self.out_a = FPNumIn(None, width)
 571         self.out_b = FPNumIn(None, width)
 572         self.exp_eq = Signal(reset_less=True)
 573
 574     def setup(self, m, in_a, in_b, in_mid):
 575         """ links module to inputs and outputs
 576         """
 577         m.submodules.align = self.mod
 578         m.d.comb += self.mod.in_a.eq(in_a)
 579         m.d.comb += self.mod.in_b.eq(in_b)
 580         #m.d.comb += self.out_a.eq(self.mod.out_a)
 581         #m.d.comb += self.out_b.eq(self.mod.out_b)
 582         m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
 583         if self.in_mid is not None:
 584             m.d.comb += self.in_mid.eq(in_mid)
 585
 586     def action(self, m):
 587         self.idsync(m)
 588         m.d.sync += self.out_a.eq(self.mod.out_a)
 589         m.d.sync += self.out_b.eq(self.mod.out_b)
 590         with m.If(self.exp_eq):
 591             m.next = "add_0"
 592
 593
 594 class FPNumIn2Ops:
 595
 596     def __init__(self, width, id_wid):
 597         self.a = FPNumIn(None, width)
 598         self.b = FPNumIn(None, width)
 599         self.mid = Signal(id_wid, reset_less=True)
 600
 601     def eq(self, i):
 602         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 603
 604
 605 class FPAddAlignSingleMod:
 606
 607     def __init__(self, width, id_wid):
 608         self.width = width
 609         self.id_wid = id_wid
 610         self.i = self.ispec()
 611         self.o = self.ospec()
 612
 613     def ispec(self):
 614         return FPNumBase2Ops(self.width, self.id_wid)
 615
 616     def ospec(self):
 617         return FPNumIn2Ops(self.width, self.id_wid)
 618
 619     def setup(self, m, i):
 620         """ links module to inputs and outputs
 621         """
 622         m.submodules.align = self
 623         m.d.comb += self.i.eq(i)
 624
 625     def elaborate(self, platform):
 626         """ Aligns A against B or B against A, depending on which has the
 627             greater exponent.  This is done in a *single* cycle using
 628             variable-width bit-shift
 629
 630             the shifter used here is quite expensive in terms of gates.
 631             Mux A or B in (and out) into temporaries, as only one of them
 632             needs to be aligned against the other
 633         """
 634         m = Module()
 635
 636         m.submodules.align_in_a = self.i.a
 637         m.submodules.align_in_b = self.i.b
 638         m.submodules.align_out_a = self.o.a
 639         m.submodules.align_out_b = self.o.b
 640
 641         # temporary (muxed) input and output to be shifted
 642         t_inp = FPNumBase(self.width)
 643         t_out = FPNumIn(None, self.width)
 644         espec = (len(self.i.a.e), True)
 645         msr = MultiShiftRMerge(self.i.a.m_width, espec)
 646         m.submodules.align_t_in = t_inp
 647         m.submodules.align_t_out = t_out
 648         m.submodules.multishift_r = msr
 649
 650         ediff = Signal(espec, reset_less=True)
 651         ediffr = Signal(espec, reset_less=True)
 652         tdiff = Signal(espec, reset_less=True)
 653         elz = Signal(reset_less=True)
 654         egz = Signal(reset_less=True)
 655
 656         # connect multi-shifter to t_inp/out mantissa (and tdiff)
 657         m.d.comb += msr.inp.eq(t_inp.m)
 658         m.d.comb += msr.diff.eq(tdiff)
 659         m.d.comb += t_out.m.eq(msr.m)
 660         m.d.comb += t_out.e.eq(t_inp.e + tdiff)
 661         m.d.comb += t_out.s.eq(t_inp.s)
 662
 663         m.d.comb += ediff.eq(self.i.a.e - self.i.b.e)
 664         m.d.comb += ediffr.eq(self.i.b.e - self.i.a.e)
 665         m.d.comb += elz.eq(self.i.a.e < self.i.b.e)
 666         m.d.comb += egz.eq(self.i.a.e > self.i.b.e)
 667
 668         # default: A-exp == B-exp, A and B untouched (fall through)
 669         m.d.comb += self.o.a.eq(self.i.a)
 670         m.d.comb += self.o.b.eq(self.i.b)
 671         # only one shifter (muxed)
 672         #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
 673         # exponent of a greater than b: shift b down
 674         with m.If(egz):
 675             m.d.comb += [t_inp.eq(self.i.b),
 676                          tdiff.eq(ediff),
 677                          self.o.b.eq(t_out),
 678                          self.o.b.s.eq(self.i.b.s), # whoops forgot sign
 679                         ]
 680         # exponent of b greater than a: shift a down
 681         with m.Elif(elz):
 682             m.d.comb += [t_inp.eq(self.i.a),
 683                          tdiff.eq(ediffr),
 684                          self.o.a.eq(t_out),
 685                          self.o.a.s.eq(self.i.a.s), # whoops forgot sign
 686                         ]
 687         return m
 688
 689
 690 class FPAddAlignSingle(FPState, FPID):
 691
 692     def __init__(self, width, id_wid):
 693         FPState.__init__(self, "align")
 694         FPID.__init__(self, id_wid)
 695         self.mod = FPAddAlignSingleMod(width, id_wid)
 696         self.out_a = FPNumIn(None, width)
 697         self.out_b = FPNumIn(None, width)
 698
 699     def setup(self, m, in_a, in_b, in_mid):
 700         """ links module to inputs and outputs
 701         """
 702         self.mod.setup(m, in_a, in_b)
 703         if self.in_mid is not None:
 704             m.d.comb += self.in_mid.eq(in_mid)
 705
 706     def action(self, m):
 707         self.idsync(m)
 708         # NOTE: could be done as comb
 709         m.d.sync += self.out_a.eq(self.mod.out_a)
 710         m.d.sync += self.out_b.eq(self.mod.out_b)
 711         m.next = "add_0"
 712
 713
 714 class FPAddAlignSingleAdd(FPState, FPID):
 715
 716     def __init__(self, width, id_wid):
 717         FPState.__init__(self, "align")
 718         FPID.__init__(self, id_wid)
 719         self.mod = FPAddAlignSingleMod(width, id_wid)
 720         self.o = self.mod.ospec()
 721
 722         self.a0mod = FPAddStage0Mod(width, id_wid)
 723         self.a0o = self.a0mod.ospec()
 724
 725         self.a1mod = FPAddStage1Mod(width, id_wid)
 726         self.a1o = self.a1mod.ospec()
 727
 728     def setup(self, m, i, in_mid):
 729         """ links module to inputs and outputs
 730         """
 731         self.mod.setup(m, i)
 732         m.d.comb += self.o.eq(self.mod.o)
 733
 734         self.a0mod.setup(m, self.o)
 735         m.d.comb += self.a0o.eq(self.a0mod.o)
 736
 737         self.a1mod.setup(m, self.a0o.tot, self.a0o.z)
 738
 739         if self.in_mid is not None:
 740             m.d.comb += self.in_mid.eq(in_mid)
 741
 742     def action(self, m):
 743         self.idsync(m)
 744         m.d.sync += self.a1o.eq(self.a1mod.o)
 745         m.next = "normalise_1"
 746
 747
 748 class FPAddStage0Data:
 749
 750     def __init__(self, width, id_wid):
 751         self.z = FPNumBase(width, False)
 752         self.tot = Signal(self.z.m_width + 4, reset_less=True)
 753         self.mid = Signal(id_wid, reset_less=True)
 754
 755     def eq(self, i):
 756         return [self.z.eq(i.z), self.tot.eq(i.tot), self.mid.eq(i.mid)]
 757
 758
 759 class FPAddStage0Mod:
 760
 761     def __init__(self, width, id_wid):
 762         self.width = width
 763         self.id_wid = id_wid
 764         self.i = self.ispec()
 765         self.o = self.ospec()
 766
 767     def ispec(self):
 768         return FPNumBase2Ops(self.width, self.id_wid)
 769
 770     def ospec(self):
 771         return FPAddStage0Data(self.width, self.id_wid)
 772
 773     def setup(self, m, i):
 774         """ links module to inputs and outputs
 775         """
 776         m.submodules.add0 = self
 777         m.d.comb += self.i.eq(i)
 778
 779     def elaborate(self, platform):
 780         m = Module()
 781         m.submodules.add0_in_a = self.i.a
 782         m.submodules.add0_in_b = self.i.b
 783         m.submodules.add0_out_z = self.o.z
 784
 785         m.d.comb += self.o.z.e.eq(self.i.a.e)
 786
 787         # store intermediate tests (and zero-extended mantissas)
 788         seq = Signal(reset_less=True)
 789         mge = Signal(reset_less=True)
 790         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
 791         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
 792         m.d.comb += [seq.eq(self.i.a.s == self.i.b.s),
 793                      mge.eq(self.i.a.m >= self.i.b.m),
 794                      am0.eq(Cat(self.i.a.m, 0)),
 795                      bm0.eq(Cat(self.i.b.m, 0))
 796                     ]
 797         # same-sign (both negative or both positive) add mantissas
 798         with m.If(seq):
 799             m.d.comb += [
 800                 self.o.tot.eq(am0 + bm0),
 801                 self.o.z.s.eq(self.i.a.s)
 802             ]
 803         # a mantissa greater than b, use a
 804         with m.Elif(mge):
 805             m.d.comb += [
 806                 self.o.tot.eq(am0 - bm0),
 807                 self.o.z.s.eq(self.i.a.s)
 808             ]
 809         # b mantissa greater than a, use b
 810         with m.Else():
 811             m.d.comb += [
 812                 self.o.tot.eq(bm0 - am0),
 813                 self.o.z.s.eq(self.i.b.s)
 814         ]
 815         return m
 816
 817
 818 class FPAddStage0(FPState, FPID):
 819     """ First stage of add.  covers same-sign (add) and subtract
 820         special-casing when mantissas are greater or equal, to
 821         give greatest accuracy.
 822     """
 823
 824     def __init__(self, width, id_wid):
 825         FPState.__init__(self, "add_0")
 826         FPID.__init__(self, id_wid)
 827         self.mod = FPAddStage0Mod(width)
 828         self.o = self.mod.ospec()
 829
 830     def setup(self, m, in_a, in_b, in_mid):
 831         """ links module to inputs and outputs
 832         """
 833         self.mod.setup(m, in_a, in_b)
 834         if self.in_mid is not None:
 835             m.d.comb += self.in_mid.eq(in_mid)
 836
 837     def action(self, m):
 838         self.idsync(m)
 839         # NOTE: these could be done as combinatorial (merge add0+add1)
 840         m.d.sync += self.o.eq(self.mod.o)
 841         m.next = "add_1"
 842
 843
 844 class FPAddStage1Data:
 845
 846     def __init__(self, width, id_wid):
 847         self.z = FPNumBase(width, False)
 848         self.of = Overflow()
 849         self.mid = Signal(id_wid, reset_less=True)
 850
 851     def eq(self, i):
 852         return [self.z.eq(i.z), self.of.eq(i.of), self.mid.eq(i.mid)]
 853
 854
 855
 856 class FPAddStage1Mod(FPState):
 857     """ Second stage of add: preparation for normalisation.
 858         detects when tot sum is too big (tot[27] is kinda a carry bit)
 859     """
 860
 861     def __init__(self, width, id_wid):
 862         self.width = width
 863         self.id_wid = id_wid
 864         self.i = self.ispec()
 865         self.o = self.ospec()
 866
 867     def ispec(self):
 868         return FPAddStage0Data(self.width, self.id_wid)
 869
 870     def ospec(self):
 871         return FPAddStage1Data(self.width, self.id_wid)
 872
 873     def setup(self, m, in_tot, in_z):
 874         """ links module to inputs and outputs
 875         """
 876         m.submodules.add1 = self
 877         m.submodules.add1_out_overflow = self.o.of
 878
 879         m.d.comb += self.i.z.eq(in_z)
 880         m.d.comb += self.i.tot.eq(in_tot)
 881
 882     def elaborate(self, platform):
 883         m = Module()
 884         #m.submodules.norm1_in_overflow = self.in_of
 885         #m.submodules.norm1_out_overflow = self.out_of
 886         #m.submodules.norm1_in_z = self.in_z
 887         #m.submodules.norm1_out_z = self.out_z
 888         m.d.comb += self.o.z.eq(self.i.z)
 889         # tot[-1] (MSB) gets set when the sum overflows. shift result down
 890         with m.If(self.i.tot[-1]):
 891             m.d.comb += [
 892                 self.o.z.m.eq(self.i.tot[4:]),
 893                 self.o.of.m0.eq(self.i.tot[4]),
 894                 self.o.of.guard.eq(self.i.tot[3]),
 895                 self.o.of.round_bit.eq(self.i.tot[2]),
 896                 self.o.of.sticky.eq(self.i.tot[1] | self.i.tot[0]),
 897                 self.o.z.e.eq(self.i.z.e + 1)
 898         ]
 899         # tot[-1] (MSB) zero case
 900         with m.Else():
 901             m.d.comb += [
 902                 self.o.z.m.eq(self.i.tot[3:]),
 903                 self.o.of.m0.eq(self.i.tot[3]),
 904                 self.o.of.guard.eq(self.i.tot[2]),
 905                 self.o.of.round_bit.eq(self.i.tot[1]),
 906                 self.o.of.sticky.eq(self.i.tot[0])
 907         ]
 908         return m
 909
 910
 911 class FPAddStage1(FPState, FPID):
 912
 913     def __init__(self, width, id_wid):
 914         FPState.__init__(self, "add_1")
 915         FPID.__init__(self, id_wid)
 916         self.mod = FPAddStage1Mod(width)
 917         self.out_z = FPNumBase(width, False)
 918         self.out_of = Overflow()
 919         self.norm_stb = Signal()
 920
 921     def setup(self, m, in_tot, in_z, in_mid):
 922         """ links module to inputs and outputs
 923         """
 924         self.mod.setup(m, in_tot, in_z)
 925
 926         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
 927
 928         if self.in_mid is not None:
 929             m.d.comb += self.in_mid.eq(in_mid)
 930
 931     def action(self, m):
 932         self.idsync(m)
 933         m.d.sync += self.out_of.eq(self.mod.out_of)
 934         m.d.sync += self.out_z.eq(self.mod.out_z)
 935         m.d.sync += self.norm_stb.eq(1)
 936         m.next = "normalise_1"
 937
 938
 939 class FPNormaliseModSingle:
 940
 941     def __init__(self, width):
 942         self.width = width
 943         self.in_z = self.ispec()
 944         self.out_z = self.ospec()
 945
 946     def ispec(self):
 947         return FPNumBase(self.width, False)
 948
 949     def ospec(self):
 950         return FPNumBase(self.width, False)
 951
 952     def setup(self, m, in_z, out_z):
 953         """ links module to inputs and outputs
 954         """
 955         m.submodules.normalise = self
 956         m.d.comb += self.in_z.eq(in_z)
 957         m.d.comb += out_z.eq(self.out_z)
 958
 959     def elaborate(self, platform):
 960         m = Module()
 961
 962         mwid = self.out_z.m_width+2
 963         pe = PriorityEncoder(mwid)
 964         m.submodules.norm_pe = pe
 965
 966         m.submodules.norm1_out_z = self.out_z
 967         m.submodules.norm1_in_z = self.in_z
 968
 969         in_z = FPNumBase(self.width, False)
 970         in_of = Overflow()
 971         m.submodules.norm1_insel_z = in_z
 972         m.submodules.norm1_insel_overflow = in_of
 973
 974         espec = (len(in_z.e), True)
 975         ediff_n126 = Signal(espec, reset_less=True)
 976         msr = MultiShiftRMerge(mwid, espec)
 977         m.submodules.multishift_r = msr
 978
 979         m.d.comb += in_z.eq(self.in_z)
 980         m.d.comb += in_of.eq(self.in_of)
 981         # initialise out from in (overridden below)
 982         m.d.comb += self.out_z.eq(in_z)
 983         m.d.comb += self.out_of.eq(in_of)
 984         # normalisation decrease condition
 985         decrease = Signal(reset_less=True)
 986         m.d.comb += decrease.eq(in_z.m_msbzero)
 987         # decrease exponent
 988         with m.If(decrease):
 989             # *sigh* not entirely obvious: count leading zeros (clz)
 990             # with a PriorityEncoder: to find from the MSB
 991             # we reverse the order of the bits.
 992             temp_m = Signal(mwid, reset_less=True)
 993             temp_s = Signal(mwid+1, reset_less=True)
 994             clz = Signal((len(in_z.e), True), reset_less=True)
 995             m.d.comb += [
 996                 # cat round and guard bits back into the mantissa
 997                 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
 998                 pe.i.eq(temp_m[::-1]),          # inverted
 999                 clz.eq(pe.o),                   # count zeros from MSB down
1000                 temp_s.eq(temp_m << clz),       # shift mantissa UP
1001                 self.out_z.e.eq(in_z.e - clz),  # DECREASE exponent
1002                 self.out_z.m.eq(temp_s[2:]),    # exclude bits 0&1
1003             ]
1004
1005         return m
1006
1007 class FPNorm1Data:
1008
1009     def __init__(self, width, id_wid):
1010         self.roundz = Signal(reset_less=True)
1011         self.z = FPNumBase(width, False)
1012         self.mid = Signal(id_wid, reset_less=True)
1013
1014     def eq(self, i):
1015         return [self.z.eq(i.z), self.roundz.eq(i.roundz), self.mid.eq(i.mid)]
1016
1017
1018 class FPNorm1ModSingle:
1019
1020     def __init__(self, width, id_wid):
1021         self.width = width
1022         self.id_wid = id_wid
1023         self.i = self.ispec()
1024         self.o = self.ospec()
1025
1026     def ispec(self):
1027         return FPAddStage1Data(self.width, self.id_wid)
1028
1029     def ospec(self):
1030         return FPNorm1Data(self.width, self.id_wid)
1031
1032     def setup(self, m, i, out_z):
1033         """ links module to inputs and outputs
1034         """
1035         m.submodules.normalise_1 = self
1036
1037         m.d.comb += self.i.eq(i)
1038
1039         m.d.comb += out_z.eq(self.o.z)
1040
1041     def elaborate(self, platform):
1042         m = Module()
1043
1044         mwid = self.o.z.m_width+2
1045         pe = PriorityEncoder(mwid)
1046         m.submodules.norm_pe = pe
1047
1048         of = Overflow()
1049         m.d.comb += self.o.roundz.eq(of.roundz)
1050
1051         m.submodules.norm1_out_z = self.o.z
1052         m.submodules.norm1_out_overflow = of
1053         m.submodules.norm1_in_z = self.i.z
1054         m.submodules.norm1_in_overflow = self.i.of
1055
1056         i = self.ispec()
1057         m.submodules.norm1_insel_z = i.z
1058         m.submodules.norm1_insel_overflow = i.of
1059
1060         espec = (len(i.z.e), True)
1061         ediff_n126 = Signal(espec, reset_less=True)
1062         msr = MultiShiftRMerge(mwid, espec)
1063         m.submodules.multishift_r = msr
1064
1065         m.d.comb += i.eq(self.i)
1066         # initialise out from in (overridden below)
1067         m.d.comb += self.o.z.eq(i.z)
1068         m.d.comb += of.eq(i.of)
1069         # normalisation increase/decrease conditions
1070         decrease = Signal(reset_less=True)
1071         increase = Signal(reset_less=True)
1072         m.d.comb += decrease.eq(i.z.m_msbzero & i.z.exp_gt_n126)
1073         m.d.comb += increase.eq(i.z.exp_lt_n126)
1074         # decrease exponent
1075         with m.If(decrease):
1076             # *sigh* not entirely obvious: count leading zeros (clz)
1077             # with a PriorityEncoder: to find from the MSB
1078             # we reverse the order of the bits.
1079             temp_m = Signal(mwid, reset_less=True)
1080             temp_s = Signal(mwid+1, reset_less=True)
1081             clz = Signal((len(i.z.e), True), reset_less=True)
1082             # make sure that the amount to decrease by does NOT
1083             # go below the minimum non-INF/NaN exponent
1084             limclz = Mux(i.z.exp_sub_n126 > pe.o, pe.o,
1085                          i.z.exp_sub_n126)
1086             m.d.comb += [
1087                 # cat round and guard bits back into the mantissa
1088                 temp_m.eq(Cat(i.of.round_bit, i.of.guard, i.z.m)),
1089                 pe.i.eq(temp_m[::-1]),          # inverted
1090                 clz.eq(limclz),                 # count zeros from MSB down
1091                 temp_s.eq(temp_m << clz),       # shift mantissa UP
1092                 self.o.z.e.eq(i.z.e - clz),  # DECREASE exponent
1093                 self.o.z.m.eq(temp_s[2:]),    # exclude bits 0&1
1094                 of.m0.eq(temp_s[2]),          # copy of mantissa[0]
1095                 # overflow in bits 0..1: got shifted too (leave sticky)
1096                 of.guard.eq(temp_s[1]),       # guard
1097                 of.round_bit.eq(temp_s[0]),   # round
1098             ]
1099         # increase exponent
1100         with m.Elif(increase):
1101             temp_m = Signal(mwid+1, reset_less=True)
1102             m.d.comb += [
1103                 temp_m.eq(Cat(i.of.sticky, i.of.round_bit, i.of.guard,
1104                               i.z.m)),
1105                 ediff_n126.eq(i.z.N126 - i.z.e),
1106                 # connect multi-shifter to inp/out mantissa (and ediff)
1107                 msr.inp.eq(temp_m),
1108                 msr.diff.eq(ediff_n126),
1109                 self.o.z.m.eq(msr.m[3:]),
1110                 of.m0.eq(temp_s[3]),   # copy of mantissa[0]
1111                 # overflow in bits 0..1: got shifted too (leave sticky)
1112                 of.guard.eq(temp_s[2]),     # guard
1113                 of.round_bit.eq(temp_s[1]), # round
1114                 of.sticky.eq(temp_s[0]),    # sticky
1115                 self.o.z.e.eq(i.z.e + ediff_n126),
1116             ]
1117
1118         return m
1119
1120
1121 class FPNorm1ModMulti:
1122
1123     def __init__(self, width, single_cycle=True):
1124         self.width = width
1125         self.in_select = Signal(reset_less=True)
1126         self.in_z = FPNumBase(width, False)
1127         self.in_of = Overflow()
1128         self.temp_z = FPNumBase(width, False)
1129         self.temp_of = Overflow()
1130         self.out_z = FPNumBase(width, False)
1131         self.out_of = Overflow()
1132
1133     def elaborate(self, platform):
1134         m = Module()
1135
1136         m.submodules.norm1_out_z = self.out_z
1137         m.submodules.norm1_out_overflow = self.out_of
1138         m.submodules.norm1_temp_z = self.temp_z
1139         m.submodules.norm1_temp_of = self.temp_of
1140         m.submodules.norm1_in_z = self.in_z
1141         m.submodules.norm1_in_overflow = self.in_of
1142
1143         in_z = FPNumBase(self.width, False)
1144         in_of = Overflow()
1145         m.submodules.norm1_insel_z = in_z
1146         m.submodules.norm1_insel_overflow = in_of
1147
1148         # select which of temp or in z/of to use
1149         with m.If(self.in_select):
1150             m.d.comb += in_z.eq(self.in_z)
1151             m.d.comb += in_of.eq(self.in_of)
1152         with m.Else():
1153             m.d.comb += in_z.eq(self.temp_z)
1154             m.d.comb += in_of.eq(self.temp_of)
1155         # initialise out from in (overridden below)
1156         m.d.comb += self.out_z.eq(in_z)
1157         m.d.comb += self.out_of.eq(in_of)
1158         # normalisation increase/decrease conditions
1159         decrease = Signal(reset_less=True)
1160         increase = Signal(reset_less=True)
1161         m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1162         m.d.comb += increase.eq(in_z.exp_lt_n126)
1163         m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
1164         # decrease exponent
1165         with m.If(decrease):
1166             m.d.comb += [
1167                 self.out_z.e.eq(in_z.e - 1),  # DECREASE exponent
1168                 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
1169                 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
1170                 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
1171                 self.out_of.round_bit.eq(0),        # reset round bit
1172                 self.out_of.m0.eq(in_of.guard),
1173             ]
1174         # increase exponent
1175         with m.Elif(increase):
1176             m.d.comb += [
1177                 self.out_z.e.eq(in_z.e + 1),  # INCREASE exponent
1178                 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
1179                 self.out_of.guard.eq(in_z.m[0]),
1180                 self.out_of.m0.eq(in_z.m[1]),
1181                 self.out_of.round_bit.eq(in_of.guard),
1182                 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
1183             ]
1184
1185         return m
1186
1187
1188 class FPNorm1Single(FPState, FPID):
1189
1190     def __init__(self, width, id_wid, single_cycle=True):
1191         FPID.__init__(self, id_wid)
1192         FPState.__init__(self, "normalise_1")
1193         self.mod = FPNorm1ModSingle(width)
1194         self.out_z = FPNumBase(width, False)
1195         self.out_roundz = Signal(reset_less=True)
1196
1197     def setup(self, m, in_z, in_of, in_mid):
1198         """ links module to inputs and outputs
1199         """
1200         self.mod.setup(m, in_z, in_of, self.out_z)
1201
1202         if self.in_mid is not None:
1203             m.d.comb += self.in_mid.eq(in_mid)
1204
1205     def action(self, m):
1206         self.idsync(m)
1207         m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1208         m.next = "round"
1209
1210
1211 class FPNorm1Multi(FPState, FPID):
1212
1213     def __init__(self, width, id_wid):
1214         FPID.__init__(self, id_wid)
1215         FPState.__init__(self, "normalise_1")
1216         self.mod = FPNorm1ModMulti(width)
1217         self.stb = Signal(reset_less=True)
1218         self.ack = Signal(reset=0, reset_less=True)
1219         self.out_norm = Signal(reset_less=True)
1220         self.in_accept = Signal(reset_less=True)
1221         self.temp_z = FPNumBase(width)
1222         self.temp_of = Overflow()
1223         self.out_z = FPNumBase(width)
1224         self.out_roundz = Signal(reset_less=True)
1225
1226     def setup(self, m, in_z, in_of, norm_stb, in_mid):
1227         """ links module to inputs and outputs
1228         """
1229         self.mod.setup(m, in_z, in_of, norm_stb,
1230                        self.in_accept, self.temp_z, self.temp_of,
1231                        self.out_z, self.out_norm)
1232
1233         m.d.comb += self.stb.eq(norm_stb)
1234         m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
1235
1236         if self.in_mid is not None:
1237             m.d.comb += self.in_mid.eq(in_mid)
1238
1239     def action(self, m):
1240         self.idsync(m)
1241         m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
1242         m.d.sync += self.temp_of.eq(self.mod.out_of)
1243         m.d.sync += self.temp_z.eq(self.out_z)
1244         with m.If(self.out_norm):
1245             with m.If(self.in_accept):
1246                 m.d.sync += [
1247                     self.ack.eq(1),
1248                 ]
1249             with m.Else():
1250                 m.d.sync += self.ack.eq(0)
1251         with m.Else():
1252             # normalisation not required (or done).
1253             m.next = "round"
1254             m.d.sync += self.ack.eq(1)
1255             m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1256
1257
1258 class FPNormToPack(FPState, FPID):
1259
1260     def __init__(self, width, id_wid):
1261         FPID.__init__(self, id_wid)
1262         FPState.__init__(self, "normalise_1")
1263         self.width = width
1264
1265     def setup(self, m, i, in_mid):
1266         """ links module to inputs and outputs
1267         """
1268
1269         # Normalisation (chained to input in_z+in_of)
1270         nmod = FPNorm1ModSingle(self.width, self.id_wid)
1271         n_out = nmod.ospec()
1272         nmod.setup(m, i, n_out.z)
1273         m.d.comb += n_out.roundz.eq(nmod.o.roundz)
1274
1275         # Rounding (chained to normalisation)
1276         rmod = FPRoundMod(self.width, self.id_wid)
1277         r_out_z = rmod.ospec()
1278         rmod.setup(m, n_out.z, n_out.roundz)
1279         m.d.comb += r_out_z.eq(rmod.out_z)
1280
1281         # Corrections (chained to rounding)
1282         cmod = FPCorrectionsMod(self.width, self.id_wid)
1283         c_out_z = cmod.ospec()
1284         cmod.setup(m, r_out_z)
1285         m.d.comb += c_out_z.eq(cmod.out_z)
1286
1287         # Pack (chained to corrections)
1288         self.pmod = FPPackMod(self.width, self.id_wid)
1289         self.out_z = self.pmod.ospec()
1290         self.pmod.setup(m, c_out_z)
1291
1292         # Multiplex ID
1293         if self.in_mid is not None:
1294             m.d.comb += self.in_mid.eq(in_mid)
1295
1296     def action(self, m):
1297         self.idsync(m) # copies incoming ID to outgoing
1298         m.d.sync += self.out_z.z.v.eq(self.pmod.o.z.v) # outputs packed result
1299         m.next = "pack_put_z"
1300
1301
1302 class FPRoundData:
1303
1304     def __init__(self, width, id_wid):
1305         self.z = FPNumBase(width, False)
1306         self.mid = Signal(id_wid, reset_less=True)
1307
1308     def eq(self, i):
1309         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1310
1311
1312 class FPRoundMod:
1313
1314     def __init__(self, width, id_wid):
1315         self.width = width
1316         self.id_wid = id_wid
1317         self.i = self.ispec()
1318         self.out_z = self.ospec()
1319
1320     def ispec(self):
1321         return FPNorm1Data(self.width, self.id_wid)
1322
1323     def ospec(self):
1324         return FPRoundData(self.width, self.id_wid)
1325
1326     def setup(self, m, in_z, roundz):
1327         m.submodules.roundz = self
1328
1329         m.d.comb += self.i.z.eq(in_z)
1330         m.d.comb += self.i.roundz.eq(roundz)
1331
1332     def elaborate(self, platform):
1333         m = Module()
1334         m.d.comb += self.out_z.eq(self.i)
1335         with m.If(self.i.roundz):
1336             m.d.comb += self.out_z.z.m.eq(self.i.z.m + 1) # mantissa rounds up
1337             with m.If(self.i.z.m == self.i.z.m1s): # all 1s
1338                 m.d.comb += self.out_z.z.e.eq(self.i.z.e + 1) # exponent up
1339         return m
1340
1341
1342 class FPRound(FPState, FPID):
1343
1344     def __init__(self, width, id_wid):
1345         FPState.__init__(self, "round")
1346         FPID.__init__(self, id_wid)
1347         self.mod = FPRoundMod(width)
1348         self.out_z = self.mod.ospec()
1349
1350     def setup(self, m, in_z, roundz, in_mid):
1351         """ links module to inputs and outputs
1352         """
1353         self.mod.setup(m, in_z, roundz)
1354
1355         if self.in_mid is not None:
1356             m.d.comb += self.in_mid.eq(in_mid)
1357
1358     def action(self, m):
1359         self.idsync(m)
1360         m.d.sync += self.out_z.eq(self.mod.out_z)
1361         m.next = "corrections"
1362
1363
1364 class FPCorrectionsMod:
1365
1366     def __init__(self, width, id_wid):
1367         self.width = width
1368         self.id_wid = id_wid
1369         self.in_z = self.ispec()
1370         self.out_z = self.ospec()
1371
1372     def ispec(self):
1373         return FPRoundData(self.width, self.id_wid)
1374
1375     def ospec(self):
1376         return FPRoundData(self.width, self.id_wid)
1377
1378     def setup(self, m, in_z):
1379         """ links module to inputs and outputs
1380         """
1381         m.submodules.corrections = self
1382         m.d.comb += self.in_z.eq(in_z)
1383
1384     def elaborate(self, platform):
1385         m = Module()
1386         m.submodules.corr_in_z = self.in_z.z
1387         m.submodules.corr_out_z = self.out_z.z
1388         m.d.comb += self.out_z.eq(self.in_z)
1389         with m.If(self.in_z.z.is_denormalised):
1390             m.d.comb += self.out_z.z.e.eq(self.in_z.z.N127)
1391         return m
1392
1393
1394 class FPCorrections(FPState, FPID):
1395
1396     def __init__(self, width, id_wid):
1397         FPState.__init__(self, "corrections")
1398         FPID.__init__(self, id_wid)
1399         self.mod = FPCorrectionsMod(width)
1400         self.out_z = self.mod.ospec()
1401
1402     def setup(self, m, in_z, in_mid):
1403         """ links module to inputs and outputs
1404         """
1405         self.mod.setup(m, in_z)
1406         if self.in_mid is not None:
1407             m.d.comb += self.in_mid.eq(in_mid)
1408
1409     def action(self, m):
1410         self.idsync(m)
1411         m.d.sync += self.out_z.eq(self.mod.out_z)
1412         m.next = "pack"
1413
1414
1415 class FPPackData:
1416
1417     def __init__(self, width, id_wid):
1418         self.z = FPNumOut(width, False)
1419         self.mid = Signal(id_wid, reset_less=True)
1420
1421     def eq(self, i):
1422         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1423
1424
1425 class FPPackMod:
1426
1427     def __init__(self, width, id_wid):
1428         self.width = width
1429         self.id_wid = id_wid
1430         self.i = self.ispec()
1431         self.o = self.ospec()
1432
1433     def ispec(self):
1434         return FPRoundData(self.width, self.id_wid)
1435
1436     def ospec(self):
1437         return FPPackData(self.width, self.id_wid)
1438
1439     def setup(self, m, in_z):
1440         """ links module to inputs and outputs
1441         """
1442         m.submodules.pack = self
1443         m.d.comb += self.i.eq(in_z)
1444
1445     def elaborate(self, platform):
1446         m = Module()
1447         m.submodules.pack_in_z = self.i.z
1448         with m.If(self.i.z.is_overflowed):
1449             m.d.comb += self.o.z.inf(self.i.z.s)
1450         with m.Else():
1451             m.d.comb += self.o.z.create(self.i.z.s, self.i.z.e, self.i.z.m)
1452         return m
1453
1454
1455 class FPPackData:
1456     def __init__(self, width, id_wid):
1457         self.z = FPNumOut(width, False)
1458         self.mid = Signal(id_wid, reset_less=True)
1459
1460     def eq(self, i):
1461         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1462
1463
1464 class FPPack(FPState, FPID):
1465
1466     def __init__(self, width, id_wid):
1467         FPState.__init__(self, "pack")
1468         FPID.__init__(self, id_wid)
1469         self.mod = FPPackMod(width)
1470         self.out_z = self.ospec()
1471
1472     def ispec(self):
1473         return self.mod.ispec()
1474
1475     def ospec(self):
1476         return self.mod.ospec()
1477
1478     def setup(self, m, in_z, in_mid):
1479         """ links module to inputs and outputs
1480         """
1481         self.mod.setup(m, in_z)
1482         if self.in_mid is not None:
1483             m.d.comb += self.in_mid.eq(in_mid)
1484
1485     def action(self, m):
1486         self.idsync(m)
1487         m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
1488         m.next = "pack_put_z"
1489
1490
1491 class FPPutZ(FPState):
1492
1493     def __init__(self, state, in_z, out_z, in_mid, out_mid, to_state=None):
1494         FPState.__init__(self, state)
1495         if to_state is None:
1496             to_state = "get_ops"
1497         self.to_state = to_state
1498         self.in_z = in_z
1499         self.out_z = out_z
1500         self.in_mid = in_mid
1501         self.out_mid = out_mid
1502
1503     def action(self, m):
1504         if self.in_mid is not None:
1505             m.d.sync += self.out_mid.eq(self.in_mid)
1506         m.d.sync += [
1507           self.out_z.v.eq(self.in_z.v)
1508         ]
1509         with m.If(self.out_z.stb & self.out_z.ack):
1510             m.d.sync += self.out_z.stb.eq(0)
1511             m.next = self.to_state
1512         with m.Else():
1513             m.d.sync += self.out_z.stb.eq(1)
1514
1515
1516 class FPPutZIdx(FPState):
1517
1518     def __init__(self, state, in_z, out_zs, in_mid, to_state=None):
1519         FPState.__init__(self, state)
1520         if to_state is None:
1521             to_state = "get_ops"
1522         self.to_state = to_state
1523         self.in_z = in_z
1524         self.out_zs = out_zs
1525         self.in_mid = in_mid
1526
1527     def action(self, m):
1528         outz_stb = Signal(reset_less=True)
1529         outz_ack = Signal(reset_less=True)
1530         m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].stb),
1531                      outz_ack.eq(self.out_zs[self.in_mid].ack),
1532                     ]
1533         m.d.sync += [
1534           self.out_zs[self.in_mid].v.eq(self.in_z.v)
1535         ]
1536         with m.If(outz_stb & outz_ack):
1537             m.d.sync += self.out_zs[self.in_mid].stb.eq(0)
1538             m.next = self.to_state
1539         with m.Else():
1540             m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
1541
1542 class FPADDBaseData:
1543
1544     def __init__(self, width, id_wid):
1545         self.width = width
1546         self.id_wid = id_wid
1547         self.a  = Signal(width)
1548         self.b  = Signal(width)
1549         self.mid = Signal(id_wid, reset_less=True)
1550
1551     def eq(self, i):
1552         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
1553
1554
1555 class FPADDBaseMod(FPID):
1556
1557     def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
1558         """ IEEE754 FP Add
1559
1560             * width: bit-width of IEEE754.  supported: 16, 32, 64
1561             * id_wid: an identifier that is sync-connected to the input
1562             * single_cycle: True indicates each stage to complete in 1 clock
1563             * compact: True indicates a reduced number of stages
1564         """
1565         FPID.__init__(self, id_wid)
1566         self.width = width
1567         self.id_wid = id_wid
1568         self.single_cycle = single_cycle
1569         self.compact = compact
1570
1571         self.in_t = Trigger()
1572         self.i = self.ispec()
1573         self.out_z = FPOp(width)
1574
1575         self.states = []
1576
1577     def ispec(self):
1578         return FPADDBaseData(self.width, self.id_wid)
1579
1580     def add_state(self, state):
1581         self.states.append(state)
1582         return state
1583
1584     def get_fragment(self, platform=None):
1585         """ creates the HDL code-fragment for FPAdd
1586         """
1587         m = Module()
1588         m.submodules.out_z = self.out_z
1589         m.submodules.in_t = self.in_t
1590         if self.compact:
1591             self.get_compact_fragment(m, platform)
1592         else:
1593             self.get_longer_fragment(m, platform)
1594
1595         with m.FSM() as fsm:
1596
1597             for state in self.states:
1598                 with m.State(state.state_from):
1599                     state.action(m)
1600
1601         return m
1602
1603     def get_longer_fragment(self, m, platform=None):
1604
1605         get = self.add_state(FPGet2Op("get_ops", "special_cases",
1606                                       self.in_a, self.in_b, self.width))
1607         get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1608         a = get.out_op1
1609         b = get.out_op2
1610
1611         sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
1612         sc.setup(m, a, b, self.in_mid)
1613
1614         dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
1615         dn.setup(m, a, b, sc.in_mid)
1616
1617         if self.single_cycle:
1618             alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
1619             alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1620         else:
1621             alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
1622             alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1623
1624         add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
1625         add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
1626
1627         add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
1628         add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
1629
1630         if self.single_cycle:
1631             n1 = self.add_state(FPNorm1Single(self.width, self.id_wid))
1632             n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
1633         else:
1634             n1 = self.add_state(FPNorm1Multi(self.width, self.id_wid))
1635             n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
1636
1637         rn = self.add_state(FPRound(self.width, self.id_wid))
1638         rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
1639
1640         cor = self.add_state(FPCorrections(self.width, self.id_wid))
1641         cor.setup(m, rn.out_z, rn.in_mid)
1642
1643         pa = self.add_state(FPPack(self.width, self.id_wid))
1644         pa.setup(m, cor.out_z, rn.in_mid)
1645
1646         ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
1647                                     pa.in_mid, self.out_mid))
1648
1649         pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1650                                     pa.in_mid, self.out_mid))
1651
1652     def get_compact_fragment(self, m, platform=None):
1653
1654         get = self.add_state(FPGet2Op("get_ops", "special_cases",
1655                                       self.i.a, self.i.b,
1656                                       self.width, self.id_wid))
1657         get.setup(m, self.i.a, self.i.b, self.in_t.stb, self.in_t.ack)
1658         a = get.o.a
1659         b = get.o.b
1660
1661         sc = self.add_state(FPAddSpecialCasesDeNorm(self.width, self.id_wid))
1662         sc.setup(m, get.o, self.in_mid)
1663
1664         alm = self.add_state(FPAddAlignSingleAdd(self.width, self.id_wid))
1665         alm.setup(m, sc.o, sc.in_mid)
1666
1667         n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
1668         n1.setup(m, alm.a1o, alm.in_mid)
1669
1670         ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z.z, self.out_z,
1671                                     n1.in_mid, self.out_mid))
1672
1673         pz = self.add_state(FPPutZ("put_z", sc.out_z.z, self.out_z,
1674                                     sc.in_mid, self.out_mid))
1675
1676
1677 class FPADDBase(FPState, FPID):
1678
1679     def __init__(self, width, id_wid=None, single_cycle=False):
1680         """ IEEE754 FP Add
1681
1682             * width: bit-width of IEEE754.  supported: 16, 32, 64
1683             * id_wid: an identifier that is sync-connected to the input
1684             * single_cycle: True indicates each stage to complete in 1 clock
1685         """
1686         FPID.__init__(self, id_wid)
1687         FPState.__init__(self, "fpadd")
1688         self.width = width
1689         self.single_cycle = single_cycle
1690         self.mod = FPADDBaseMod(width, id_wid, single_cycle)
1691
1692         self.in_t = Trigger()
1693         self.in_a  = Signal(width)
1694         self.in_b  = Signal(width)
1695         #self.out_z = FPOp(width)
1696
1697         self.z_done = Signal(reset_less=True) # connects to out_z Strobe
1698         self.in_accept = Signal(reset_less=True)
1699         self.add_stb = Signal(reset_less=True)
1700         self.add_ack = Signal(reset=0, reset_less=True)
1701
1702     def setup(self, m, a, b, add_stb, in_mid, out_z, out_mid):
1703         self.out_z = out_z
1704         self.out_mid = out_mid
1705         m.d.comb += [self.in_a.eq(a),
1706                      self.in_b.eq(b),
1707                      self.mod.i.a.eq(self.in_a),
1708                      self.mod.i.b.eq(self.in_b),
1709                      self.in_mid.eq(in_mid),
1710                      self.mod.in_mid.eq(self.in_mid),
1711                      self.z_done.eq(self.mod.out_z.trigger),
1712                      #self.add_stb.eq(add_stb),
1713                      self.mod.in_t.stb.eq(self.in_t.stb),
1714                      self.in_t.ack.eq(self.mod.in_t.ack),
1715                      self.out_mid.eq(self.mod.out_mid),
1716                      self.out_z.v.eq(self.mod.out_z.v),
1717                      self.out_z.stb.eq(self.mod.out_z.stb),
1718                      self.mod.out_z.ack.eq(self.out_z.ack),
1719                     ]
1720
1721         m.d.sync += self.add_stb.eq(add_stb)
1722         m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
1723         m.d.sync += self.out_z.ack.eq(0) # likewise
1724         #m.d.sync += self.in_t.stb.eq(0)
1725
1726         m.submodules.fpadd = self.mod
1727
1728     def action(self, m):
1729
1730         # in_accept is set on incoming strobe HIGH and ack LOW.
1731         m.d.comb += self.in_accept.eq((~self.add_ack) & (self.add_stb))
1732
1733         #with m.If(self.in_t.ack):
1734         #    m.d.sync += self.in_t.stb.eq(0)
1735         with m.If(~self.z_done):
1736             # not done: test for accepting an incoming operand pair
1737             with m.If(self.in_accept):
1738                 m.d.sync += [
1739                     self.add_ack.eq(1), # acknowledge receipt...
1740                     self.in_t.stb.eq(1), # initiate add
1741                 ]
1742             with m.Else():
1743                 m.d.sync += [self.add_ack.eq(0),
1744                              self.in_t.stb.eq(0),
1745                              self.out_z.ack.eq(1),
1746                             ]
1747         with m.Else():
1748             # done: acknowledge, and write out id and value
1749             m.d.sync += [self.add_ack.eq(1),
1750                          self.in_t.stb.eq(0)
1751                         ]
1752             m.next = "put_z"
1753
1754             return
1755
1756             if self.in_mid is not None:
1757                 m.d.sync += self.out_mid.eq(self.mod.out_mid)
1758
1759             m.d.sync += [
1760               self.out_z.v.eq(self.mod.out_z.v)
1761             ]
1762             # move to output state on detecting z ack
1763             with m.If(self.out_z.trigger):
1764                 m.d.sync += self.out_z.stb.eq(0)
1765                 m.next = "put_z"
1766             with m.Else():
1767                 m.d.sync += self.out_z.stb.eq(1)
1768
1769 class ResArray:
1770     def __init__(self, width, id_wid):
1771         self.width = width
1772         self.id_wid = id_wid
1773         res = []
1774         for i in range(rs_sz):
1775             out_z = FPOp(width)
1776             out_z.name = "out_z_%d" % i
1777             res.append(out_z)
1778         self.res = Array(res)
1779         self.in_z = FPOp(width)
1780         self.in_mid = Signal(self.id_wid, reset_less=True)
1781
1782     def setup(self, m, in_z, in_mid):
1783         m.d.comb += [self.in_z.eq(in_z),
1784                      self.in_mid.eq(in_mid)]
1785
1786     def get_fragment(self, platform=None):
1787         """ creates the HDL code-fragment for FPAdd
1788         """
1789         m = Module()
1790         m.submodules.res_in_z = self.in_z
1791         m.submodules += self.res
1792
1793         return m
1794
1795     def ports(self):
1796         res = []
1797         for z in self.res:
1798             res += z.ports()
1799         return res
1800
1801
1802 class FPADD(FPID):
1803     """ FPADD: stages as follows:
1804
1805         FPGetOp (a)
1806            |
1807         FPGetOp (b)
1808            |
1809         FPAddBase---> FPAddBaseMod
1810            |            |
1811         PutZ          GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
1812
1813         FPAddBase is tricky: it is both a stage and *has* stages.
1814         Connection to FPAddBaseMod therefore requires an in stb/ack
1815         and an out stb/ack.  Just as with Add1-Norm1 interaction, FPGetOp
1816         needs to be the thing that raises the incoming stb.
1817     """
1818
1819     def __init__(self, width, id_wid=None, single_cycle=False, rs_sz=2):
1820         """ IEEE754 FP Add
1821
1822             * width: bit-width of IEEE754.  supported: 16, 32, 64
1823             * id_wid: an identifier that is sync-connected to the input
1824             * single_cycle: True indicates each stage to complete in 1 clock
1825         """
1826         self.width = width
1827         self.id_wid = id_wid
1828         self.single_cycle = single_cycle
1829
1830         #self.out_z = FPOp(width)
1831         self.ids = FPID(id_wid)
1832
1833         rs = []
1834         for i in range(rs_sz):
1835             in_a  = FPOp(width)
1836             in_b  = FPOp(width)
1837             in_a.name = "in_a_%d" % i
1838             in_b.name = "in_b_%d" % i
1839             rs.append((in_a, in_b))
1840         self.rs = Array(rs)
1841
1842         res = []
1843         for i in range(rs_sz):
1844             out_z = FPOp(width)
1845             out_z.name = "out_z_%d" % i
1846             res.append(out_z)
1847         self.res = Array(res)
1848
1849         self.states = []
1850
1851     def add_state(self, state):
1852         self.states.append(state)
1853         return state
1854
1855     def get_fragment(self, platform=None):
1856         """ creates the HDL code-fragment for FPAdd
1857         """
1858         m = Module()
1859         m.submodules += self.rs
1860
1861         in_a = self.rs[0][0]
1862         in_b = self.rs[0][1]
1863
1864         out_z = FPOp(self.width)
1865         out_mid = Signal(self.id_wid, reset_less=True)
1866         m.submodules.out_z = out_z
1867
1868         geta = self.add_state(FPGetOp("get_a", "get_b",
1869                                       in_a, self.width))
1870         geta.setup(m, in_a)
1871         a = geta.out_op
1872
1873         getb = self.add_state(FPGetOp("get_b", "fpadd",
1874                                       in_b, self.width))
1875         getb.setup(m, in_b)
1876         b = getb.out_op
1877
1878         ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
1879         ab = self.add_state(ab)
1880         ab.setup(m, a, b, getb.out_decode, self.ids.in_mid,
1881                  out_z, out_mid)
1882
1883         pz = self.add_state(FPPutZIdx("put_z", ab.out_z, self.res,
1884                                     out_mid, "get_a"))
1885
1886         with m.FSM() as fsm:
1887
1888             for state in self.states:
1889                 with m.State(state.state_from):
1890                     state.action(m)
1891
1892         return m
1893
1894
1895 if __name__ == "__main__":
1896     if True:
1897         alu = FPADD(width=32, id_wid=5, single_cycle=True)
1898         main(alu, ports=alu.rs[0][0].ports() + \
1899                         alu.rs[0][1].ports() + \
1900                         alu.res[0].ports() + \
1901                         [alu.ids.in_mid, alu.ids.out_mid])
1902     else:
1903         alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
1904         main(alu, ports=[alu.in_a, alu.in_b] + \
1905                         alu.in_t.ports() + \
1906                         alu.out_z.ports() + \
1907                         [alu.in_mid, alu.out_mid])
1908
1909
1910     # works... but don't use, just do "python fname.py convert -t v"
1911     #print (verilog.convert(alu, ports=[
1912     #                        ports=alu.in_a.ports() + \
1913     #                              alu.in_b.ports() + \
1914     #                              alu.out_z.ports())