src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat
   6 from nmigen.cli import main, verilog
   7
   8 from fpbase import FPNum, FPOp, Overflow, FPBase
   9
  10
  11 class FPADD(FPBase):
  12
  13     def __init__(self, width, single_cycle=False):
  14         FPBase.__init__(self)
  15         self.width = width
  16         self.single_cycle = single_cycle
  17
  18         self.in_a  = FPOp(width)
  19         self.in_b  = FPOp(width)
  20         self.out_z = FPOp(width)
  21
  22     def get_fragment(self, platform=None):
  23         """ creates the HDL code-fragment for FPAdd
  24         """
  25         m = Module()
  26
  27         # Latches
  28         a = FPNum(self.width)
  29         b = FPNum(self.width)
  30         z = FPNum(self.width, False)
  31
  32         w = {32: 28, 64:57}[self.width]
  33         tot = Signal(w) # sticky/round/guard, {mantissa} result, 1 overflow
  34
  35         of = Overflow()
  36
  37         with m.FSM() as fsm:
  38
  39             # ******
  40             # gets operand a
  41
  42             with m.State("get_a"):
  43                 self.get_op(m, self.in_a, a, "get_b")
  44
  45             # ******
  46             # gets operand b
  47
  48             with m.State("get_b"):
  49                 self.get_op(m, self.in_b, b, "special_cases")
  50
  51             # ******
  52             # special cases: NaNs, infs, zeros, denormalised
  53             # NOTE: some of these are unique to add.  see "Special Operations"
  54             # https://steve.hollasch.net/cgindex/coding/ieeefloat.html
  55
  56             with m.State("special_cases"):
  57
  58                 # if a is NaN or b is NaN return NaN
  59                 with m.If(a.is_nan() | b.is_nan()):
  60                     m.next = "put_z"
  61                     m.d.sync += z.nan(1)
  62
  63                 # if a is inf return inf (or NaN)
  64                 with m.Elif(a.is_inf()):
  65                     m.next = "put_z"
  66                     m.d.sync += z.inf(a.s)
  67                     # if a is inf and signs don't match return NaN
  68                     with m.If((b.e == b.P128) & (a.s != b.s)):
  69                         m.d.sync += z.nan(b.s)
  70
  71                 # if b is inf return inf
  72                 with m.Elif(b.is_inf()):
  73                     m.next = "put_z"
  74                     m.d.sync += z.inf(b.s)
  75
  76                 # if a is zero and b zero return signed-a/b
  77                 with m.Elif(a.is_zero() & b.is_zero()):
  78                     m.next = "put_z"
  79                     m.d.sync += z.create(a.s & b.s, b.e, b.m[3:-1])
  80
  81                 # if a is zero return b
  82                 with m.Elif(a.is_zero()):
  83                     m.next = "put_z"
  84                     m.d.sync += z.create(b.s, b.e, b.m[3:-1])
  85
  86                 # if b is zero return a
  87                 with m.Elif(b.is_zero()):
  88                     m.next = "put_z"
  89                     m.d.sync += z.create(a.s, a.e, a.m[3:-1])
  90
  91                 with m.Elif((a.s != b.s) & (a.m == b.m) & (a.e == b.e)):
  92                     m.next = "put_z"
  93                     m.d.sync += z.zero(0)
  94
  95                 # Denormalised Number checks
  96                 with m.Else():
  97                     m.next = "align"
  98                     self.denormalise(m, a)
  99                     self.denormalise(m, b)
 100
 101             # ******
 102             # align.
 103
 104             with m.State("align"):
 105                 if not self.single_cycle:
 106                     # NOTE: this does *not* do single-cycle multi-shifting,
 107                     #       it *STAYS* in the align state until exponents match
 108
 109                     # exponent of a greater than b: shift b down
 110                     with m.If(a.e > b.e):
 111                         m.d.sync += b.shift_down()
 112                     # exponent of b greater than a: shift a down
 113                     with m.Elif(a.e < b.e):
 114                         m.d.sync += a.shift_down()
 115                     # exponents equal: move to next stage.
 116                     with m.Else():
 117                         m.next = "add_0"
 118                 else:
 119                     # This one however (single-cycle) will do the shift
 120                     # in one go.
 121
 122                     # XXX TODO: the shifter used here is quite expensive
 123                     # having only one would be better
 124
 125                     ediff = Signal((len(a.e), True))
 126                     ediffr = Signal((len(a.e), True))
 127                     m.d.comb += ediff.eq(a.e - b.e)
 128                     m.d.comb += ediffr.eq(b.e - a.e)
 129                     with m.If(ediff > 0):
 130                         m.d.sync += b.shift_down_multi(ediff)
 131                     # exponent of b greater than a: shift a down
 132                     with m.Elif(ediff < 0):
 133                         m.d.sync += a.shift_down_multi(ediffr)
 134
 135                     m.next = "add_0"
 136
 137             # ******
 138             # First stage of add.  covers same-sign (add) and subtract
 139             # special-casing when mantissas are greater or equal, to
 140             # give greatest accuracy.
 141
 142             with m.State("add_0"):
 143                 m.next = "add_1"
 144                 m.d.sync += z.e.eq(a.e)
 145                 # same-sign (both negative or both positive) add mantissas
 146                 with m.If(a.s == b.s):
 147                     m.d.sync += [
 148                         tot.eq(Cat(a.m, 0) + Cat(b.m, 0)),
 149                         z.s.eq(a.s)
 150                     ]
 151                 # a mantissa greater than b, use a
 152                 with m.Elif(a.m >= b.m):
 153                     m.d.sync += [
 154                         tot.eq(Cat(a.m, 0) - Cat(b.m, 0)),
 155                         z.s.eq(a.s)
 156                     ]
 157                 # b mantissa greater than a, use b
 158                 with m.Else():
 159                     m.d.sync += [
 160                         tot.eq(Cat(b.m, 0) - Cat(a.m, 0)),
 161                         z.s.eq(b.s)
 162                 ]
 163
 164             # ******
 165             # Second stage of add: preparation for normalisation.
 166             # detects when tot sum is too big (tot[27] is kinda a carry bit)
 167
 168             with m.State("add_1"):
 169                 m.next = "normalise_1"
 170                 # tot[27] gets set when the sum overflows. shift result down
 171                 with m.If(tot[-1]):
 172                     m.d.sync += [
 173                         z.m.eq(tot[4:]),
 174                         of.guard.eq(tot[3]),
 175                         of.round_bit.eq(tot[2]),
 176                         of.sticky.eq(tot[1] | tot[0]),
 177                         z.e.eq(z.e + 1)
 178                 ]
 179                 # tot[27] zero case
 180                 with m.Else():
 181                     m.d.sync += [
 182                         z.m.eq(tot[3:]),
 183                         of.guard.eq(tot[2]),
 184                         of.round_bit.eq(tot[1]),
 185                         of.sticky.eq(tot[0])
 186                 ]
 187
 188             # ******
 189             # First stage of normalisation.
 190
 191             with m.State("normalise_1"):
 192                 self.normalise_1(m, z, of, "normalise_2")
 193
 194             # ******
 195             # Second stage of normalisation.
 196
 197             with m.State("normalise_2"):
 198                 self.normalise_2(m, z, of, "round")
 199
 200             # ******
 201             # rounding stage
 202
 203             with m.State("round"):
 204                 self.roundz(m, z, of, "corrections")
 205
 206             # ******
 207             # correction stage
 208
 209             with m.State("corrections"):
 210                 self.corrections(m, z, "pack")
 211
 212             # ******
 213             # pack stage
 214
 215             with m.State("pack"):
 216                 self.pack(m, z, "put_z")
 217
 218             # ******
 219             # put_z stage
 220
 221             with m.State("put_z"):
 222                 self.put_z(m, z, self.out_z, "get_a")
 223
 224         return m
 225
 226
 227 if __name__ == "__main__":
 228     alu = FPADD(width=32)
 229     main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
 230
 231
 232     # works... but don't use, just do "python fname.py convert -t v"
 233     #print (verilog.convert(alu, ports=[
 234     #                        ports=alu.in_a.ports() + \
 235     #                              alu.in_b.ports() + \
 236     #                              alu.out_z.ports())