src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat
   6 from nmigen.cli import main, verilog
   7
   8 from fpbase import FPNum, FPOp, Overflow, FPBase
   9
  10
  11 class FPADD(FPBase):
  12
  13     def __init__(self, width, single_cycle=False):
  14         FPBase.__init__(self)
  15         self.width = width
  16         self.single_cycle = single_cycle
  17
  18         self.in_a  = FPOp(width)
  19         self.in_b  = FPOp(width)
  20         self.out_z = FPOp(width)
  21
  22     def get_fragment(self, platform=None):
  23         """ creates the HDL code-fragment for FPAdd
  24         """
  25         m = Module()
  26
  27         # Latches
  28         a = FPNum(self.width)
  29         b = FPNum(self.width)
  30         z = FPNum(self.width, False)
  31
  32         w = z.m_width + 4
  33         tot = Signal(w) # sticky/round/guard, {mantissa} result, 1 overflow
  34
  35         of = Overflow()
  36
  37         with m.FSM() as fsm:
  38
  39             # ******
  40             # gets operand a
  41
  42             with m.State("get_a"):
  43                 self.get_op(m, self.in_a, a, "get_b")
  44
  45             # ******
  46             # gets operand b
  47
  48             with m.State("get_b"):
  49                 self.get_op(m, self.in_b, b, "special_cases")
  50
  51             # ******
  52             # special cases: NaNs, infs, zeros, denormalised
  53             # NOTE: some of these are unique to add.  see "Special Operations"
  54             # https://steve.hollasch.net/cgindex/coding/ieeefloat.html
  55
  56             with m.State("special_cases"):
  57
  58                 # if a is NaN or b is NaN return NaN
  59                 with m.If(a.is_nan() | b.is_nan()):
  60                     m.next = "put_z"
  61                     m.d.sync += z.nan(1)
  62
  63                 # if a is inf return inf (or NaN)
  64                 with m.Elif(a.is_inf()):
  65                     m.next = "put_z"
  66                     m.d.sync += z.inf(a.s)
  67                     # if a is inf and signs don't match return NaN
  68                     with m.If((b.e == b.P128) & (a.s != b.s)):
  69                         m.d.sync += z.nan(1)
  70
  71                 # if b is inf return inf
  72                 with m.Elif(b.is_inf()):
  73                     m.next = "put_z"
  74                     m.d.sync += z.inf(b.s)
  75
  76                 # if a is zero and b zero return signed-a/b
  77                 with m.Elif(a.is_zero() & b.is_zero()):
  78                     m.next = "put_z"
  79                     m.d.sync += z.create(a.s & b.s, b.e, b.m[3:-1])
  80
  81                 # if a is zero return b
  82                 with m.Elif(a.is_zero()):
  83                     m.next = "put_z"
  84                     m.d.sync += z.create(b.s, b.e, b.m[3:-1])
  85
  86                 # if b is zero return a
  87                 with m.Elif(b.is_zero()):
  88                     m.next = "put_z"
  89                     m.d.sync += z.create(a.s, a.e, a.m[3:-1])
  90
  91                 # if a equal to -b return zero (+ve zero)
  92                 with m.Elif((a.s != b.s) & (a.m == b.m) & (a.e == b.e)):
  93                     m.next = "put_z"
  94                     m.d.sync += z.zero(0)
  95
  96                 # Denormalised Number checks
  97                 with m.Else():
  98                     m.next = "align"
  99                     self.denormalise(m, a)
 100                     self.denormalise(m, b)
 101
 102             # ******
 103             # align.
 104
 105             with m.State("align"):
 106                 if not self.single_cycle:
 107                     # NOTE: this does *not* do single-cycle multi-shifting,
 108                     #       it *STAYS* in the align state until exponents match
 109
 110                     # exponent of a greater than b: shift b down
 111                     with m.If(a.e > b.e):
 112                         m.d.sync += b.shift_down()
 113                     # exponent of b greater than a: shift a down
 114                     with m.Elif(a.e < b.e):
 115                         m.d.sync += a.shift_down()
 116                     # exponents equal: move to next stage.
 117                     with m.Else():
 118                         m.next = "add_0"
 119                 else:
 120                     # This one however (single-cycle) will do the shift
 121                     # in one go.
 122
 123                     # XXX TODO: the shifter used here is quite expensive
 124                     # having only one would be better
 125
 126                     ediff = Signal((len(a.e), True))
 127                     ediffr = Signal((len(a.e), True))
 128                     m.d.comb += ediff.eq(a.e - b.e)
 129                     m.d.comb += ediffr.eq(b.e - a.e)
 130                     with m.If(ediff > 0):
 131                         m.d.sync += b.shift_down_multi(ediff)
 132                     # exponent of b greater than a: shift a down
 133                     with m.Elif(ediff < 0):
 134                         m.d.sync += a.shift_down_multi(ediffr)
 135
 136                     m.next = "add_0"
 137
 138             # ******
 139             # First stage of add.  covers same-sign (add) and subtract
 140             # special-casing when mantissas are greater or equal, to
 141             # give greatest accuracy.
 142
 143             with m.State("add_0"):
 144                 m.next = "add_1"
 145                 m.d.sync += z.e.eq(a.e)
 146                 # same-sign (both negative or both positive) add mantissas
 147                 with m.If(a.s == b.s):
 148                     m.d.sync += [
 149                         tot.eq(Cat(a.m, 0) + Cat(b.m, 0)),
 150                         z.s.eq(a.s)
 151                     ]
 152                 # a mantissa greater than b, use a
 153                 with m.Elif(a.m >= b.m):
 154                     m.d.sync += [
 155                         tot.eq(Cat(a.m, 0) - Cat(b.m, 0)),
 156                         z.s.eq(a.s)
 157                     ]
 158                 # b mantissa greater than a, use b
 159                 with m.Else():
 160                     m.d.sync += [
 161                         tot.eq(Cat(b.m, 0) - Cat(a.m, 0)),
 162                         z.s.eq(b.s)
 163                 ]
 164
 165             # ******
 166             # Second stage of add: preparation for normalisation.
 167             # detects when tot sum is too big (tot[27] is kinda a carry bit)
 168
 169             with m.State("add_1"):
 170                 m.next = "normalise_1"
 171                 # tot[27] gets set when the sum overflows. shift result down
 172                 with m.If(tot[-1]):
 173                     m.d.sync += [
 174                         z.m.eq(tot[4:]),
 175                         of.guard.eq(tot[3]),
 176                         of.round_bit.eq(tot[2]),
 177                         of.sticky.eq(tot[1] | tot[0]),
 178                         z.e.eq(z.e + 1)
 179                 ]
 180                 # tot[27] zero case
 181                 with m.Else():
 182                     m.d.sync += [
 183                         z.m.eq(tot[3:]),
 184                         of.guard.eq(tot[2]),
 185                         of.round_bit.eq(tot[1]),
 186                         of.sticky.eq(tot[0])
 187                 ]
 188
 189             # ******
 190             # First stage of normalisation.
 191
 192             with m.State("normalise_1"):
 193                 self.normalise_1(m, z, of, "normalise_2")
 194
 195             # ******
 196             # Second stage of normalisation.
 197
 198             with m.State("normalise_2"):
 199                 self.normalise_2(m, z, of, "round")
 200
 201             # ******
 202             # rounding stage
 203
 204             with m.State("round"):
 205                 self.roundz(m, z, of, "corrections")
 206
 207             # ******
 208             # correction stage
 209
 210             with m.State("corrections"):
 211                 self.corrections(m, z, "pack")
 212
 213             # ******
 214             # pack stage
 215
 216             with m.State("pack"):
 217                 self.pack(m, z, "put_z")
 218
 219             # ******
 220             # put_z stage
 221
 222             with m.State("put_z"):
 223                 self.put_z(m, z, self.out_z, "get_a")
 224
 225         return m
 226
 227
 228 if __name__ == "__main__":
 229     alu = FPADD(width=32)
 230     main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
 231
 232
 233     # works... but don't use, just do "python fname.py convert -t v"
 234     #print (verilog.convert(alu, ports=[
 235     #                        ports=alu.in_a.ports() + \
 236     #                              alu.in_b.ports() + \
 237     #                              alu.out_z.ports())