src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat, Const
   6 from nmigen.cli import main, verilog
   7
   8
   9 class FPNum:
  10     """ Floating-point Number Class, variable-width TODO (currently 32-bit)
  11
  12         Contains signals for an incoming copy of the value, decoded into
  13         sign / exponent / mantissa.
  14         Also contains encoding functions, creation and recognition of
  15         zero, NaN and inf (all signed)
  16
  17         Four extra bits are included in the mantissa: the top bit
  18         (m[-1]) is effectively a carry-overflow.  The other three are
  19         guard (m[2]), round (m[1]), and sticky (m[0])
  20     """
  21     def __init__(self, width, m_width=None):
  22         self.width = width
  23         if m_width is None:
  24             m_width = width - 5 # mantissa extra bits (top,guard,round)
  25         self.v = Signal(width)      # Latched copy of value
  26         self.m = Signal(m_width)    # Mantissa
  27         self.e = Signal((10, True)) # Exponent: 10 bits, signed
  28         self.s = Signal()           # Sign bit
  29
  30         self.mzero = Const(0, (m_width, False))
  31         self.m1s = Const(-1, (m_width, False))
  32         self.P128 = Const(128, (10, True))
  33         self.P127 = Const(127, (10, True))
  34         self.N127 = Const(-127, (10, True))
  35         self.N126 = Const(-126, (10, True))
  36
  37     def decode(self):
  38         """ decodes a latched value into sign / exponent / mantissa
  39
  40             bias is subtracted here, from the exponent.  exponent
  41             is extended to 10 bits so that subtract 127 is done on
  42             a 10-bit number
  43         """
  44         v = self.v
  45         return [self.m.eq(Cat(0, 0, 0, v[0:23])), # mantissa
  46                 self.e.eq(v[23:31] - self.P127), # exp (minus bias)
  47                 self.s.eq(v[31]),                 # sign
  48                 ]
  49
  50     def create(self, s, e, m):
  51         """ creates a value from sign / exponent / mantissa
  52
  53             bias is added here, to the exponent
  54         """
  55         return [
  56           self.v[31].eq(s),          # sign
  57           self.v[23:31].eq(e + self.P127), # exp (add on bias)
  58           self.v[0:23].eq(m)         # mantissa
  59         ]
  60
  61     def shift_down(self):
  62         """ shifts a mantissa down by one. exponent is increased to compensate
  63
  64             accuracy is lost as a result in the mantissa however there are 3
  65             guard bits (the latter of which is the "sticky" bit)
  66         """
  67         return [self.e.eq(self.e + 1),
  68                 self.m.eq(Cat(self.m[0] | self.m[1], self.m[2:], 0))
  69                ]
  70
  71     def nan(self, s):
  72         return self.create(s, self.P128, 1<<22)
  73
  74     def inf(self, s):
  75         return self.create(s, self.P128, 0)
  76
  77     def zero(self, s):
  78         return self.create(s, self.N127, 0)
  79
  80     def is_nan(self):
  81         return (self.e == self.P128) & (self.m != 0)
  82
  83     def is_inf(self):
  84         return (self.e == self.P128) & (self.m == 0)
  85
  86     def is_zero(self):
  87         return (self.e == self.N127) & (self.m == self.mzero)
  88
  89     def is_overflowed(self):
  90         return (self.e > self.P127)
  91
  92     def is_denormalised(self):
  93         return (self.e == self.N126) & (self.m[23] == 0)
  94
  95 class FPOp:
  96     def __init__(self, width):
  97         self.width = width
  98
  99         self.v     = Signal(width)
 100         self.stb = Signal()
 101         self.ack = Signal()
 102
 103     def ports(self):
 104         return [self.v, self.stb, self.ack]
 105
 106
 107 class Overflow:
 108     def __init__(self):
 109         self.guard = Signal()     # tot[2]
 110         self.round_bit = Signal() # tot[1]
 111         self.sticky = Signal()    # tot[0]
 112
 113
 114 class FPADD:
 115     def __init__(self, width):
 116         self.width = width
 117
 118         self.in_a     = FPOp(width)
 119         self.in_b     = FPOp(width)
 120         self.out_z     = FPOp(width)
 121
 122     def get_op(self, m, op, v, next_state):
 123         with m.If((op.ack) & (op.stb)):
 124             m.next = next_state
 125             m.d.sync += [
 126                 v.eq(op.v),
 127                 op.ack.eq(0)
 128             ]
 129         with m.Else():
 130             m.d.sync += op.ack.eq(1)
 131
 132     def normalise_1(self, m, z, of, next_state):
 133         with m.If((z.m[-1] == 0) & (z.e > z.N126)):
 134             m.d.sync +=[
 135                 z.e.eq(z.e - 1),  # DECREASE exponent
 136                 z.m.eq(z.m << 1), # shift mantissa UP
 137                 z.m[0].eq(of.guard),       # steal guard bit (was tot[2])
 138                 of.guard.eq(of.round_bit), # steal round_bit (was tot[1])
 139                 of.round_bit.eq(0),        # reset round bit
 140             ]
 141         with m.Else():
 142             m.next = next_state
 143
 144     def get_fragment(self, platform=None):
 145         m = Module()
 146
 147         # Latches
 148         a = FPNum(self.width)
 149         b = FPNum(self.width)
 150         z = FPNum(self.width, 24)
 151
 152         tot = Signal(28)     # sticky/round/guard bits, 23 result, 1 overflow
 153
 154         of = Overflow()
 155
 156         with m.FSM() as fsm:
 157
 158             # ******
 159             # gets operand a
 160
 161             with m.State("get_a"):
 162                 self.get_op(m, self.in_a, a.v, "get_b")
 163
 164             # ******
 165             # gets operand b
 166
 167             with m.State("get_b"):
 168                 self.get_op(m, self.in_b, b.v, "unpack")
 169
 170             # ******
 171             # unpacks operands into sign, mantissa and exponent
 172
 173             with m.State("unpack"):
 174                 m.next = "special_cases"
 175                 m.d.sync += a.decode()
 176                 m.d.sync += b.decode()
 177
 178             # ******
 179             # special cases: NaNs, infs, zeros, denormalised
 180
 181             with m.State("special_cases"):
 182
 183                 # if a is NaN or b is NaN return NaN
 184                 with m.If(a.is_nan() | b.is_nan()):
 185                     m.next = "put_z"
 186                     m.d.sync += z.nan(1)
 187
 188                 # if a is inf return inf (or NaN)
 189                 with m.Elif(a.is_inf()):
 190                     m.next = "put_z"
 191                     m.d.sync += z.inf(a.s)
 192                     # if a is inf and signs don't match return NaN
 193                     with m.If((b.e == b.P128) & (a.s != b.s)):
 194                         m.d.sync += z.nan(b.s)
 195
 196                 # if b is inf return inf
 197                 with m.Elif(b.is_inf()):
 198                     m.next = "put_z"
 199                     m.d.sync += z.inf(b.s)
 200
 201                 # if a is zero and b zero return signed-a/b
 202                 with m.Elif(a.is_zero() & b.is_zero()):
 203                     m.next = "put_z"
 204                     m.d.sync += z.create(a.s & b.s, b.e[0:8], b.m[3:-1])
 205
 206                 # if a is zero return b
 207                 with m.Elif(a.is_zero()):
 208                     m.next = "put_z"
 209                     m.d.sync += z.create(b.s, b.e[0:8], b.m[3:-1])
 210
 211                 # if b is zero return a
 212                 with m.Elif(b.is_zero()):
 213                     m.next = "put_z"
 214                     m.d.sync += z.create(a.s, a.e[0:8], a.m[3:-1])
 215
 216                 # Denormalised Number checks
 217                 with m.Else():
 218                     m.next = "align"
 219                     # denormalise a check
 220                     with m.If(a.e == a.N127):
 221                         m.d.sync += a.e.eq(-126) # limit a exponent
 222                     with m.Else():
 223                         m.d.sync += a.m[-1].eq(1) # set top mantissa bit
 224                     # denormalise b check
 225                     with m.If(b.e == a.N127):
 226                         m.d.sync += b.e.eq(-126) # limit b exponent
 227                     with m.Else():
 228                         m.d.sync += b.m[-1].eq(1) # set top mantissa bit
 229
 230             # ******
 231             # align.  NOTE: this does *not* do single-cycle multi-shifting,
 232             #         it *STAYS* in the align state until the exponents match
 233
 234             with m.State("align"):
 235                 # exponent of a greater than b: increment b exp, shift b mant
 236                 with m.If(a.e > b.e):
 237                     m.d.sync += b.shift_down()
 238                 # exponent of b greater than a: increment a exp, shift a mant
 239                 with m.Elif(a.e < b.e):
 240                     m.d.sync += a.shift_down()
 241                 # exponents equal: move to next stage.
 242                 with m.Else():
 243                     m.next = "add_0"
 244
 245             # ******
 246             # First stage of add.  covers same-sign (add) and subtract
 247             # special-casing when mantissas are greater or equal, to
 248             # give greatest accuracy.
 249
 250             with m.State("add_0"):
 251                 m.next = "add_1"
 252                 m.d.sync += z.e.eq(a.e)
 253                 # same-sign (both negative or both positive) add mantissas
 254                 with m.If(a.s == b.s):
 255                     m.d.sync += [
 256                         tot.eq(a.m + b.m),
 257                         z.s.eq(a.s)
 258                     ]
 259                 # a mantissa greater than b, use a
 260                 with m.Elif(a.m >= b.m):
 261                     m.d.sync += [
 262                         tot.eq(a.m - b.m),
 263                         z.s.eq(a.s)
 264                     ]
 265                 # b mantissa greater than a, use b
 266                 with m.Else():
 267                     m.d.sync += [
 268                         tot.eq(b.m - a.m),
 269                         z.s.eq(b.s)
 270                 ]
 271
 272             # ******
 273             # Second stage of add: preparation for normalisation.
 274             # detects when tot sum is too big (tot[27] is kinda a carry bit)
 275
 276             with m.State("add_1"):
 277                 m.next = "normalise_1"
 278                 # tot[27] gets set when the sum overflows. shift result down
 279                 with m.If(tot[27]):
 280                     m.d.sync += [
 281                         z.m.eq(tot[4:28]),
 282                         of.guard.eq(tot[3]),
 283                         of.round_bit.eq(tot[2]),
 284                         of.sticky.eq(tot[1] | tot[0]),
 285                         z.e.eq(z.e + 1)
 286                 ]
 287                 # tot[27] zero case
 288                 with m.Else():
 289                     m.d.sync += [
 290                         z.m.eq(tot[3:27]),
 291                         of.guard.eq(tot[2]),
 292                         of.round_bit.eq(tot[1]),
 293                         of.sticky.eq(tot[0])
 294                 ]
 295
 296             # ******
 297             # First stage of normalisation.
 298             # NOTE: just like "align", this one keeps going round every clock
 299             #       until the result's exponent is within acceptable "range"
 300             # NOTE: the weirdness of reassigning guard and round is due to
 301             #       the extra mantissa bits coming from tot[0..2]
 302
 303             with m.State("normalise_1"):
 304                 self.normalise_1(m, z, of, "normalise_2")
 305
 306             # ******
 307             # Second stage of normalisation.
 308             # NOTE: just like "align", this one keeps going round every clock
 309             #       until the result's exponent is within acceptable "range"
 310             # NOTE: the weirdness of reassigning guard and round is due to
 311             #       the extra mantissa bits coming from tot[0..2]
 312
 313             with m.State("normalise_2"):
 314                 with m.If(z.e < z.N126):
 315                     m.d.sync +=[
 316                         z.e.eq(z.e + 1),  # INCREASE exponent
 317                         z.m.eq(z.m >> 1), # shift mantissa DOWN
 318                         of.guard.eq(z.m[0]),
 319                         of.round_bit.eq(of.guard),
 320                         of.sticky.eq(of.sticky | of.round_bit)
 321                     ]
 322                 with m.Else():
 323                     m.next = "round"
 324
 325             # ******
 326             # rounding stage
 327
 328             with m.State("round"):
 329                 m.next = "corrections"
 330                 with m.If(of.guard & (of.round_bit | of.sticky | z.m[0])):
 331                     m.d.sync += z.m.eq(z.m + 1) # mantissa rounds up
 332                     with m.If(z.m == z.m1s): # all 1s
 333                         m.d.sync += z.e.eq(z.e + 1) # exponent rounds up
 334
 335             # ******
 336             # correction stage
 337
 338             with m.State("corrections"):
 339                 m.next = "pack"
 340                 # denormalised, correct exponent to zero
 341                 with m.If(z.is_denormalised()):
 342                     m.d.sync += z.m.eq(-127)
 343                 # FIX SIGN BUG: -a + a = +0.
 344                 with m.If((z.e == z.N126) & (z.m[0:] == 0)):
 345                     m.d.sync += z.s.eq(0)
 346
 347             # ******
 348             # pack stage
 349
 350             with m.State("pack"):
 351                 m.next = "put_z"
 352                 # if overflow occurs, return inf
 353                 with m.If(z.is_overflowed()):
 354                     m.d.sync += z.inf(0)
 355                 with m.Else():
 356                     m.d.sync += z.create(z.s, z.e, z.m)
 357
 358             # ******
 359             # put_z stage
 360
 361             with m.State("put_z"):
 362               m.d.sync += [
 363                   self.out_z.stb.eq(1),
 364                   self.out_z.v.eq(z.v)
 365               ]
 366               with m.If(self.out_z.stb & self.out_z.ack):
 367                   m.d.sync += self.out_z.stb.eq(0)
 368                   m.next = "get_a"
 369
 370         return m
 371
 372
 373 if __name__ == "__main__":
 374     alu = FPADD(width=32)
 375     main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
 376
 377
 378     # works... but don't use, just do "python fname.py convert -t v"
 379     #print (verilog.convert(alu, ports=[
 380     #                        ports=alu.in_a.ports() + \
 381     #                              alu.in_b.ports() + \
 382     #                              alu.out_z.ports())