1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
, Cat
6 from nmigen
.cli
import main
10 """ Floating-point Number Class, variable-width TODO (currently 32-bit)
12 Contains signals for an incoming copy of the value, decoded into
13 sign / exponent / mantissa.
14 Also contains encoding functions, creation and recognition of
15 zero, NaN and inf (all signed)
17 Four extra bits are included in the mantissa: the top bit
18 (m[-1]) is effectively a carry-overflow. The other three are
19 guard (m[2]), round (m[1]), and sticky (m[0])
21 def __init__(self
, width
, m_width
=None):
24 m_width
= width
- 5 # mantissa extra bits (top,guard,round)
25 self
.v
= Signal(width
) # Latched copy of value
26 self
.m
= Signal(m_width
) # Mantissa
27 self
.e
= Signal((10, True)) # Exponent: 10 bits, signed
28 self
.s
= Signal() # Sign bit
31 """ decodes a latched value into sign / exponent / mantissa
33 bias is subtracted here, from the exponent.
36 return [self
.m
.eq(Cat(0, 0, 0, v
[0:23])), # mantissa
37 self
.e
.eq(Cat(v
[23:31]) - 127), # exponent (take off bias)
38 self
.s
.eq(Cat(v
[31])), # sign
41 def create(self
, s
, e
, m
):
42 """ creates a value from sign / exponent / mantissa
44 bias is added here, to the exponent
47 self
.v
[31].eq(s
), # sign
48 self
.v
[23:31].eq(e
+ 127), # exp (add on bias)
49 self
.v
[0:23].eq(m
) # mantissa
53 """ shifts a mantissa down by one. exponent is increased to compensate
55 accuracy is lost as a result in the mantissa however there are 3
56 guard bits (the latter of which is the "sticky" bit)
58 return self
.create(self
.s
,
60 Cat(self
.m
[0] | self
.m
[1], self
.m
[1:-5], 0))
63 return self
.create(s
, 0x80, 1<<22)
66 return self
.create(s
, 0x80, 0)
69 return self
.create(s
, -127, 0)
72 return (self
.e
== 128) & (self
.m
!= 0)
75 return (self
.e
== 128) & (self
.m
== 0)
78 return (self
.e
== -127) & (self
.m
== 0)
82 def __init__(self
, width
):
85 self
.in_a
= Signal(width
)
86 self
.in_a_stb
= Signal()
87 self
.in_a_ack
= Signal()
89 self
.in_b
= Signal(width
)
90 self
.in_b_stb
= Signal()
91 self
.in_b_ack
= Signal()
93 self
.out_z
= Signal(width
)
94 self
.out_z_stb
= Signal()
95 self
.out_z_ack
= Signal()
97 def get_fragment(self
, platform
):
101 a
= FPNum(self
.width
)
102 b
= FPNum(self
.width
)
103 z
= FPNum(self
.width
, 24)
116 with m
.State("get_a"):
117 with m
.If((self
.in_a_ack
) & (self
.in_a_stb
)):
124 m
.d
.sync
+= self
.in_a_ack
.eq(1)
129 with m
.State("get_b"):
130 with m
.If((self
.in_b_ack
) & (self
.in_b_stb
)):
137 m
.d
.sync
+= self
.in_b_ack
.eq(1)
140 # unpacks operands into sign, mantissa and exponent
142 with m
.State("unpack"):
143 m
.next
= "special_cases"
144 m
.d
.sync
+= a
.decode()
145 m
.d
.sync
+= b
.decode()
148 # special cases: NaNs, infs, zeros, denormalised
150 with m
.State("special_cases"):
152 # if a is NaN or b is NaN return NaN
153 with m
.If(a
.is_nan() | b
.is_nan()):
157 # if a is inf return inf (or NaN)
158 with m
.Elif(a
.is_inf()):
160 m
.d
.sync
+= z
.inf(a
.s
)
161 # if a is inf and signs don't match return NaN
162 with m
.If((b
.e
== 128) & (a
.s
!= b
.s
)):
163 m
.d
.sync
+= z
.nan(b
.s
)
165 # if b is inf return inf
166 with m
.Elif(b
.is_inf()):
168 m
.d
.sync
+= z
.inf(b
.s
)
170 # if a is zero and b zero return signed-a/b
171 with m
.Elif(a
.is_zero() & b
.is_zero()):
173 m
.d
.sync
+= z
.create(a
.s
& b
.s
, b
.e
[0:8], b
.m
[3:26])
175 # if a is zero return b
176 with m
.Elif(a
.is_zero()):
178 m
.d
.sync
+= z
.create(b
.s
, b
.e
[0:8], b
.m
[3:26])
180 # if b is zero return a
181 with m
.Elif(b
.is_zero()):
183 m
.d
.sync
+= z
.create(a
.s
, a
.e
[0:8], a
.m
[3:26])
185 # Denormalised Number checks
188 # denormalise a check
189 with m
.If(a
.e
== -127):
190 m
.d
.sync
+= a
.e
.eq(-126) # limit a exponent
192 m
.d
.sync
+= a
.m
[26].eq(1) # set highest mantissa bit
193 # denormalise b check
194 with m
.If(b
.e
== -127):
195 m
.d
.sync
+= b
.e
.eq(-126) # limit b exponent
197 m
.d
.sync
+= b
.m
[26].eq(1) # set highest mantissa bit
200 # align. NOTE: this does *not* do single-cycle multi-shifting,
201 # it *STAYS* in the align state until the exponents match
203 with m
.State("align"):
204 # exponent of a greater than b: increment b exp, shift b mant
205 with m
.If(a
.e
> b
.e
):
206 m
.d
.sync
+= b
.shift_down()
207 # exponent of b greater than a: increment a exp, shift a mant
208 with m
.Elif(a
.e
< b
.e
):
209 m
.d
.sync
+= a
.shift_down()
210 # exponents equal: move to next stage.
215 # First stage of add. covers same-sign (add) and subtract
216 # special-casing when mantissas are greater or equal, to
217 # give greatest accuracy.
219 with m
.State("add_0"):
221 m
.d
.sync
+= z
.e
.eq(a
.e
)
222 # same-sign (both negative or both positive) add mantissas
223 with m
.If(a
.s
== b
.s
):
228 # a mantissa greater than b, use a
229 with m
.Elif(a
.m
>= b
.m
):
234 # b mantissa greater than a, use b
242 # Second stage of add: preparation for normalisation.
243 # detects when tot sum is too big (tot[27] is kinda a carry bit)
245 with m
.State("add_1"):
246 m
.next
= "normalise_1"
247 # tot[27] gets set when the sum overflows. shift result down
252 round_bit
.eq(tot
[2]),
253 sticky
.eq(tot
[1] | tot
[0]),
261 round_bit
.eq(tot
[1]),
266 # First stage of normalisation.
267 # NOTE: just like "align", this one keeps going round every clock
268 # until the result's exponent is within acceptable "range"
269 # NOTE: the weirdness of reassigning guard and round is due to
270 # the extra mantissa bits coming from tot[0..2]
272 with m
.State("normalise_1"):
273 with m
.If((z
.m
[23] == 0) & (z
.e
> -126)):
275 z
.e
.eq(z
.e
- 1), # DECREASE exponent
276 z
.m
.eq(z
.m
<< 1), # shift mantissa UP
277 z
.m
[0].eq(guard
), # steal guard bit (was tot[2])
278 guard
.eq(round_bit
), # steal round_bit (was tot[1])
281 m
.next
= "normalize_2"
284 # Second stage of normalisation.
285 # NOTE: just like "align", this one keeps going round every clock
286 # until the result's exponent is within acceptable "range"
287 # NOTE: the weirdness of reassigning guard and round is due to
288 # the extra mantissa bits coming from tot[0..2]
290 with m
.State("normalise_2"):
291 with m
.If(z
.e
< -126):
293 z
.e
.eq(z
.e
+ 1), # INCREASE exponent
294 z
.m
.eq(z
.m
>> 1), # shift mantissa DOWN
297 sticky
.eq(sticky | round_bit
)
305 with m
.State("round"):
307 with m
.If(guard
& (round_bit | sticky | z
.m
[0])):
308 m
.d
.sync
+= z
.m
.eq(z
.m
+ 1) # mantissa rounds up
309 with m
.If(z
.m
== 0xffffff): # all 1s
310 m
.d
.sync
+= z
.e
.eq(z
.e
+ 1) # exponent rounds up
315 """ TODO: see if z.create can be used *later*. convert
316 verilog first (and commit), *second* phase, convert nmigen
317 code to use FPNum.create() (as a separate commit)
321 z[22 : 0] <= z_m[22:0];
322 z[30 : 23] <= z_e[7:0] + 127;
324 if ($signed(z_e) == -126 && z_m[23] == 0) begin
327 if ($signed(z_e) == -126 && z_m[23:0] == 24'h0) begin
328 z[31] <= 1'b0; // FIX SIGN BUG: -a + a = +0.
330 //if overflow occurs, return inf
331 if ($signed(z_e) > 127) begin
348 if (s_out_z_stb && out_z_ack) begin
358 always @(posedge clk)
366 if (s_in_a_ack && in_a_stb) begin
376 if (s_in_b_ack && in_b_stb) begin
385 a_m <= {a[22 : 0], 3'd0};
386 b_m <= {b[22 : 0], 3'd0};
387 a_e <= a[30 : 23] - 127;
388 b_e <= b[30 : 23] - 127;
391 state <= special_cases;
396 //if a is NaN or b is NaN return NaN
397 if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
403 //if a is inf return inf
404 end else if (a_e == 128) begin
408 //if a is inf and signs don't match return nan
409 if ((b_e == 128) && (a_s != b_s)) begin
416 //if b is inf return inf
417 end else if (b_e == 128) begin
422 //if a is zero return b
423 end else if ((($signed(a_e) == -127) && (a_m == 0)) && (($signed(b_e) == -127) && (b_m == 0))) begin
425 z[30:23] <= b_e[7:0] + 127;
426 z[22:0] <= b_m[26:3];
428 //if a is zero return b
429 end else if (($signed(a_e) == -127) && (a_m == 0)) begin
431 z[30:23] <= b_e[7:0] + 127;
432 z[22:0] <= b_m[26:3];
434 //if b is zero return a
435 end else if (($signed(b_e) == -127) && (b_m == 0)) begin
437 z[30:23] <= a_e[7:0] + 127;
438 z[22:0] <= a_m[26:3];
441 //Denormalised Number
442 if ($signed(a_e) == -127) begin
447 //Denormalised Number
448 if ($signed(b_e) == -127) begin
459 if ($signed(a_e) > $signed(b_e)) begin
462 b_m[0] <= b_m[0] | b_m[1];
463 end else if ($signed(a_e) < $signed(b_e)) begin
466 a_m[0] <= a_m[0] | a_m[1];
475 if (a_s == b_s) begin
479 if (a_m >= b_m) begin
496 sticky <= tot[1] | tot[0];
504 state <= normalise_1;
509 if (z_m[23] == 0 && $signed(z_e) > -126) begin
516 state <= normalise_2;
522 if ($signed(z_e) < -126) begin
527 sticky <= sticky | round_bit;
535 if (guard && (round_bit | sticky | z_m[0])) begin
537 if (z_m == 24'hffffff) begin
546 z[22 : 0] <= z_m[22:0];
547 z[30 : 23] <= z_e[7:0] + 127;
549 if ($signed(z_e) == -126 && z_m[23] == 0) begin
552 if ($signed(z_e) == -126 && z_m[23:0] == 24'h0) begin
553 z[31] <= 1'b0; // FIX SIGN BUG: -a + a = +0.
555 //if overflow occurs, return inf
556 if ($signed(z_e) > 127) begin
568 if (s_out_z_stb && out_z_ack) begin
584 assign in_a_ack = s_in_a_ack;
585 assign in_b_ack = s_in_b_ack;
586 assign out_z_stb = s_out_z_stb;
587 assign out_z = s_out_z;
592 if __name__
== "__main__":
593 alu
= FPADD(width
=32)
595 alu
.in_a
, alu
.in_a_stb
, alu
.in_a_ack
,
596 alu
.in_b
, alu
.in_b_stb
, alu
.in_b_ack
,
597 alu
.out_z
, alu
.out_z_stb
, alu
.out_z_ack
,