src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat
   6 from nmigen.cli import main, verilog
   7
   8 from fpbase import FPNum, FPOp, Overflow, FPBase
   9
  10
  11 class FPADD(FPBase):
  12
  13     def __init__(self, width, single_cycle=False):
  14         FPBase.__init__(self)
  15         self.width = width
  16         self.single_cycle = single_cycle
  17
  18         self.in_a  = FPOp(width)
  19         self.in_b  = FPOp(width)
  20         self.out_z = FPOp(width)
  21
  22     def get_fragment(self, platform=None):
  23         """ creates the HDL code-fragment for FPAdd
  24         """
  25         m = Module()
  26
  27         # Latches
  28         a = FPNum(self.width)
  29         b = FPNum(self.width)
  30         z = FPNum(self.width, False)
  31
  32         w = {32: 28, 64:57}[self.width]
  33         tot = Signal(w) # sticky/round/guard, {mantissa} result, 1 overflow
  34
  35         of = Overflow()
  36
  37         with m.FSM() as fsm:
  38
  39             # ******
  40             # gets operand a
  41
  42             with m.State("get_a"):
  43                 self.get_op(m, self.in_a, a, "get_b")
  44
  45             # ******
  46             # gets operand b
  47
  48             with m.State("get_b"):
  49                 self.get_op(m, self.in_b, b, "special_cases")
  50
  51             # ******
  52             # special cases: NaNs, infs, zeros, denormalised
  53             # NOTE: some of these are unique to add.  see "Special Operations"
  54             # https://steve.hollasch.net/cgindex/coding/ieeefloat.html
  55
  56             with m.State("special_cases"):
  57
  58                 # if a is NaN or b is NaN return NaN
  59                 with m.If(a.is_nan() | b.is_nan()):
  60                     m.next = "put_z"
  61                     m.d.sync += z.nan(1)
  62
  63                 # if a is inf return inf (or NaN)
  64                 with m.Elif(a.is_inf()):
  65                     m.next = "put_z"
  66                     m.d.sync += z.inf(a.s)
  67                     # if a is inf and signs don't match return NaN
  68                     with m.If((b.e == b.P128) & (a.s != b.s)):
  69                         m.d.sync += z.nan(b.s)
  70
  71                 # if b is inf return inf
  72                 with m.Elif(b.is_inf()):
  73                     m.next = "put_z"
  74                     m.d.sync += z.inf(b.s)
  75
  76                 # if a is zero and b zero return signed-a/b
  77                 with m.Elif(a.is_zero() & b.is_zero()):
  78                     m.next = "put_z"
  79                     m.d.sync += z.create(a.s & b.s, b.e, b.m[3:-1])
  80
  81                 # if a is zero return b
  82                 with m.Elif(a.is_zero()):
  83                     m.next = "put_z"
  84                     m.d.sync += z.create(b.s, b.e, b.m[3:-1])
  85
  86                 # if b is zero return a
  87                 with m.Elif(b.is_zero()):
  88                     m.next = "put_z"
  89                     m.d.sync += z.create(a.s, a.e, a.m[3:-1])
  90
  91                 # Denormalised Number checks
  92                 with m.Else():
  93                     m.next = "align"
  94                     self.denormalise(m, a)
  95                     self.denormalise(m, b)
  96
  97             # ******
  98             # align.
  99
 100             with m.State("align"):
 101                 if not self.single_cycle:
 102                     # NOTE: this does *not* do single-cycle multi-shifting,
 103                     #       it *STAYS* in the align state until exponents match
 104
 105                     # exponent of a greater than b: shift b down
 106                     with m.If(a.e > b.e):
 107                         m.d.sync += b.shift_down()
 108                     # exponent of b greater than a: shift a down
 109                     with m.Elif(a.e < b.e):
 110                         m.d.sync += a.shift_down()
 111                     # exponents equal: move to next stage.
 112                     with m.Else():
 113                         m.next = "add_0"
 114                 else:
 115                     # This one however (single-cycle) will do the shift
 116                     # in one go.
 117
 118                     ediff = Signal((len(a.e), True))
 119                     ediffr = Signal((len(a.e), True))
 120                     m.d.comb += ediff.eq(a.e - b.e)
 121                     m.d.comb += ediffr.eq(b.e - a.e)
 122                     with m.If(ediff > 0):
 123                         m.d.sync += b.shift_down_multi(ediff)
 124                     # exponent of b greater than a: shift a down
 125                     with m.Elif(ediff < 0):
 126                         m.d.sync += a.shift_down_multi(ediffr)
 127
 128                     m.next = "add_0"
 129
 130             # ******
 131             # First stage of add.  covers same-sign (add) and subtract
 132             # special-casing when mantissas are greater or equal, to
 133             # give greatest accuracy.
 134
 135             with m.State("add_0"):
 136                 m.next = "add_1"
 137                 m.d.sync += z.e.eq(a.e)
 138                 # same-sign (both negative or both positive) add mantissas
 139                 with m.If(a.s == b.s):
 140                     m.d.sync += [
 141                         tot.eq(Cat(a.m, 0) + Cat(b.m, 0)),
 142                         z.s.eq(a.s)
 143                     ]
 144                 # a mantissa greater than b, use a
 145                 with m.Elif(a.m >= b.m):
 146                     m.d.sync += [
 147                         tot.eq(Cat(a.m, 0) - Cat(b.m, 0)),
 148                         z.s.eq(a.s)
 149                     ]
 150                 # b mantissa greater than a, use b
 151                 with m.Else():
 152                     m.d.sync += [
 153                         tot.eq(Cat(b.m, 0) - Cat(a.m, 0)),
 154                         z.s.eq(b.s)
 155                 ]
 156
 157             # ******
 158             # Second stage of add: preparation for normalisation.
 159             # detects when tot sum is too big (tot[27] is kinda a carry bit)
 160
 161             with m.State("add_1"):
 162                 m.next = "normalise_1"
 163                 # tot[27] gets set when the sum overflows. shift result down
 164                 with m.If(tot[-1]):
 165                     m.d.sync += [
 166                         z.m.eq(tot[4:]),
 167                         of.guard.eq(tot[3]),
 168                         of.round_bit.eq(tot[2]),
 169                         of.sticky.eq(tot[1] | tot[0]),
 170                         z.e.eq(z.e + 1)
 171                 ]
 172                 # tot[27] zero case
 173                 with m.Else():
 174                     m.d.sync += [
 175                         z.m.eq(tot[3:]),
 176                         of.guard.eq(tot[2]),
 177                         of.round_bit.eq(tot[1]),
 178                         of.sticky.eq(tot[0])
 179                 ]
 180
 181             # ******
 182             # First stage of normalisation.
 183
 184             with m.State("normalise_1"):
 185                 self.normalise_1(m, z, of, "normalise_2")
 186
 187             # ******
 188             # Second stage of normalisation.
 189
 190             with m.State("normalise_2"):
 191                 self.normalise_2(m, z, of, "round")
 192
 193             # ******
 194             # rounding stage
 195
 196             with m.State("round"):
 197                 self.roundz(m, z, of, "corrections")
 198
 199             # ******
 200             # correction stage
 201
 202             with m.State("corrections"):
 203                 self.corrections(m, z, "pack")
 204
 205             # ******
 206             # pack stage
 207
 208             with m.State("pack"):
 209                 self.pack(m, z, "put_z")
 210
 211             # ******
 212             # put_z stage
 213
 214             with m.State("put_z"):
 215                 self.put_z(m, z, self.out_z, "get_a")
 216
 217         return m
 218
 219
 220 if __name__ == "__main__":
 221     alu = FPADD(width=32)
 222     main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
 223
 224
 225     # works... but don't use, just do "python fname.py convert -t v"
 226     #print (verilog.convert(alu, ports=[
 227     #                        ports=alu.in_a.ports() + \
 228     #                              alu.in_b.ports() + \
 229     #                              alu.out_z.ports())