src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat, Const
   6 from nmigen.cli import main, verilog
   7
   8
   9 class FPNum:
  10     """ Floating-point Number Class, variable-width TODO (currently 32-bit)
  11
  12         Contains signals for an incoming copy of the value, decoded into
  13         sign / exponent / mantissa.
  14         Also contains encoding functions, creation and recognition of
  15         zero, NaN and inf (all signed)
  16
  17         Four extra bits are included in the mantissa: the top bit
  18         (m[-1]) is effectively a carry-overflow.  The other three are
  19         guard (m[2]), round (m[1]), and sticky (m[0])
  20     """
  21     def __init__(self, width, m_width=None):
  22         self.width = width
  23         if m_width is None:
  24             m_width = width - 5 # mantissa extra bits (top,guard,round)
  25         self.v = Signal(width)      # Latched copy of value
  26         self.m = Signal(m_width)    # Mantissa
  27         self.e = Signal((10, True)) # Exponent: 10 bits, signed
  28         self.s = Signal()           # Sign bit
  29
  30         self.mzero = Const(0, (m_width, False))
  31         self.m1s = Const(-1, (m_width, False))
  32         self.P128 = Const(128, (10, True))
  33         self.P127 = Const(127, (10, True))
  34         self.N127 = Const(-127, (10, True))
  35         self.N126 = Const(-126, (10, True))
  36
  37     def decode(self):
  38         """ decodes a latched value into sign / exponent / mantissa
  39
  40             bias is subtracted here, from the exponent.  exponent
  41             is extended to 10 bits so that subtract 127 is done on
  42             a 10-bit number
  43         """
  44         v = self.v
  45         return [self.m.eq(Cat(0, 0, 0, v[0:23])), # mantissa
  46                 self.e.eq(v[23:31] - self.P127), # exp (minus bias)
  47                 self.s.eq(v[31]),                 # sign
  48                 ]
  49
  50     def create(self, s, e, m):
  51         """ creates a value from sign / exponent / mantissa
  52
  53             bias is added here, to the exponent
  54         """
  55         return [
  56           self.v[31].eq(s),          # sign
  57           self.v[23:31].eq(e + self.P127), # exp (add on bias)
  58           self.v[0:23].eq(m)         # mantissa
  59         ]
  60
  61     def shift_down(self):
  62         """ shifts a mantissa down by one. exponent is increased to compensate
  63
  64             accuracy is lost as a result in the mantissa however there are 3
  65             guard bits (the latter of which is the "sticky" bit)
  66         """
  67         return [self.e.eq(self.e + 1),
  68                 self.m.eq(Cat(self.m[0] | self.m[1], self.m[2:], 0))
  69                ]
  70
  71     def nan(self, s):
  72         return self.create(s, self.P128, 1<<22)
  73
  74     def inf(self, s):
  75         return self.create(s, self.P128, 0)
  76
  77     def zero(self, s):
  78         return self.create(s, self.N127, 0)
  79
  80     def is_nan(self):
  81         return (self.e == self.P128) & (self.m != 0)
  82
  83     def is_inf(self):
  84         return (self.e == self.P128) & (self.m == 0)
  85
  86     def is_zero(self):
  87         return (self.e == self.N127) & (self.m == self.mzero)
  88
  89     def is_overflowed(self):
  90         return (self.e > self.P127)
  91
  92     def is_denormalised(self):
  93         return (self.e == self.N126) & (self.m[23] == 0)
  94
  95 class FPOp:
  96     def __init__(self, width):
  97         self.width = width
  98
  99         self.v     = Signal(width)
 100         self.stb = Signal()
 101         self.ack = Signal()
 102
 103     def ports(self):
 104         return [self.v, self.stb, self.ack]
 105
 106
 107 class Overflow:
 108     def __init__(self):
 109         self.guard = Signal()     # tot[2]
 110         self.round_bit = Signal() # tot[1]
 111         self.sticky = Signal()    # tot[0]
 112
 113
 114 class FPADD:
 115     def __init__(self, width):
 116         self.width = width
 117
 118         self.in_a     = FPOp(width)
 119         self.in_b     = FPOp(width)
 120         self.out_z     = FPOp(width)
 121
 122     def get_op(self, m, op, v, next_state):
 123         with m.If((op.ack) & (op.stb)):
 124             m.next = next_state
 125             m.d.sync += [
 126                 v.eq(op.v),
 127                 op.ack.eq(0)
 128             ]
 129         with m.Else():
 130             m.d.sync += op.ack.eq(1)
 131
 132     def normalise_1(self, m, z, of, next_state):
 133         with m.If((z.m[-1] == 0) & (z.e > z.N126)):
 134             m.d.sync +=[
 135                 z.e.eq(z.e - 1),  # DECREASE exponent
 136                 z.m.eq(z.m << 1), # shift mantissa UP
 137                 z.m[0].eq(of.guard),       # steal guard bit (was tot[2])
 138                 of.guard.eq(of.round_bit), # steal round_bit (was tot[1])
 139                 of.round_bit.eq(0),        # reset round bit
 140             ]
 141         with m.Else():
 142             m.next = next_state
 143
 144     def normalise_2(self, m, z, of, next_state):
 145         with m.If(z.e < z.N126):
 146             m.d.sync +=[
 147                 z.e.eq(z.e + 1),  # INCREASE exponent
 148                 z.m.eq(z.m >> 1), # shift mantissa DOWN
 149                 of.guard.eq(z.m[0]),
 150                 of.round_bit.eq(of.guard),
 151                 of.sticky.eq(of.sticky | of.round_bit)
 152             ]
 153         with m.Else():
 154             m.next = next_state
 155
 156     def get_fragment(self, platform=None):
 157         m = Module()
 158
 159         # Latches
 160         a = FPNum(self.width)
 161         b = FPNum(self.width)
 162         z = FPNum(self.width, 24)
 163
 164         tot = Signal(28)     # sticky/round/guard bits, 23 result, 1 overflow
 165
 166         of = Overflow()
 167
 168         with m.FSM() as fsm:
 169
 170             # ******
 171             # gets operand a
 172
 173             with m.State("get_a"):
 174                 self.get_op(m, self.in_a, a.v, "get_b")
 175
 176             # ******
 177             # gets operand b
 178
 179             with m.State("get_b"):
 180                 self.get_op(m, self.in_b, b.v, "unpack")
 181
 182             # ******
 183             # unpacks operands into sign, mantissa and exponent
 184
 185             with m.State("unpack"):
 186                 m.next = "special_cases"
 187                 m.d.sync += a.decode()
 188                 m.d.sync += b.decode()
 189
 190             # ******
 191             # special cases: NaNs, infs, zeros, denormalised
 192
 193             with m.State("special_cases"):
 194
 195                 # if a is NaN or b is NaN return NaN
 196                 with m.If(a.is_nan() | b.is_nan()):
 197                     m.next = "put_z"
 198                     m.d.sync += z.nan(1)
 199
 200                 # if a is inf return inf (or NaN)
 201                 with m.Elif(a.is_inf()):
 202                     m.next = "put_z"
 203                     m.d.sync += z.inf(a.s)
 204                     # if a is inf and signs don't match return NaN
 205                     with m.If((b.e == b.P128) & (a.s != b.s)):
 206                         m.d.sync += z.nan(b.s)
 207
 208                 # if b is inf return inf
 209                 with m.Elif(b.is_inf()):
 210                     m.next = "put_z"
 211                     m.d.sync += z.inf(b.s)
 212
 213                 # if a is zero and b zero return signed-a/b
 214                 with m.Elif(a.is_zero() & b.is_zero()):
 215                     m.next = "put_z"
 216                     m.d.sync += z.create(a.s & b.s, b.e[0:8], b.m[3:-1])
 217
 218                 # if a is zero return b
 219                 with m.Elif(a.is_zero()):
 220                     m.next = "put_z"
 221                     m.d.sync += z.create(b.s, b.e[0:8], b.m[3:-1])
 222
 223                 # if b is zero return a
 224                 with m.Elif(b.is_zero()):
 225                     m.next = "put_z"
 226                     m.d.sync += z.create(a.s, a.e[0:8], a.m[3:-1])
 227
 228                 # Denormalised Number checks
 229                 with m.Else():
 230                     m.next = "align"
 231                     # denormalise a check
 232                     with m.If(a.e == a.N127):
 233                         m.d.sync += a.e.eq(-126) # limit a exponent
 234                     with m.Else():
 235                         m.d.sync += a.m[-1].eq(1) # set top mantissa bit
 236                     # denormalise b check
 237                     with m.If(b.e == a.N127):
 238                         m.d.sync += b.e.eq(-126) # limit b exponent
 239                     with m.Else():
 240                         m.d.sync += b.m[-1].eq(1) # set top mantissa bit
 241
 242             # ******
 243             # align.  NOTE: this does *not* do single-cycle multi-shifting,
 244             #         it *STAYS* in the align state until the exponents match
 245
 246             with m.State("align"):
 247                 # exponent of a greater than b: increment b exp, shift b mant
 248                 with m.If(a.e > b.e):
 249                     m.d.sync += b.shift_down()
 250                 # exponent of b greater than a: increment a exp, shift a mant
 251                 with m.Elif(a.e < b.e):
 252                     m.d.sync += a.shift_down()
 253                 # exponents equal: move to next stage.
 254                 with m.Else():
 255                     m.next = "add_0"
 256
 257             # ******
 258             # First stage of add.  covers same-sign (add) and subtract
 259             # special-casing when mantissas are greater or equal, to
 260             # give greatest accuracy.
 261
 262             with m.State("add_0"):
 263                 m.next = "add_1"
 264                 m.d.sync += z.e.eq(a.e)
 265                 # same-sign (both negative or both positive) add mantissas
 266                 with m.If(a.s == b.s):
 267                     m.d.sync += [
 268                         tot.eq(a.m + b.m),
 269                         z.s.eq(a.s)
 270                     ]
 271                 # a mantissa greater than b, use a
 272                 with m.Elif(a.m >= b.m):
 273                     m.d.sync += [
 274                         tot.eq(a.m - b.m),
 275                         z.s.eq(a.s)
 276                     ]
 277                 # b mantissa greater than a, use b
 278                 with m.Else():
 279                     m.d.sync += [
 280                         tot.eq(b.m - a.m),
 281                         z.s.eq(b.s)
 282                 ]
 283
 284             # ******
 285             # Second stage of add: preparation for normalisation.
 286             # detects when tot sum is too big (tot[27] is kinda a carry bit)
 287
 288             with m.State("add_1"):
 289                 m.next = "normalise_1"
 290                 # tot[27] gets set when the sum overflows. shift result down
 291                 with m.If(tot[27]):
 292                     m.d.sync += [
 293                         z.m.eq(tot[4:28]),
 294                         of.guard.eq(tot[3]),
 295                         of.round_bit.eq(tot[2]),
 296                         of.sticky.eq(tot[1] | tot[0]),
 297                         z.e.eq(z.e + 1)
 298                 ]
 299                 # tot[27] zero case
 300                 with m.Else():
 301                     m.d.sync += [
 302                         z.m.eq(tot[3:27]),
 303                         of.guard.eq(tot[2]),
 304                         of.round_bit.eq(tot[1]),
 305                         of.sticky.eq(tot[0])
 306                 ]
 307
 308             # ******
 309             # First stage of normalisation.
 310             # NOTE: just like "align", this one keeps going round every clock
 311             #       until the result's exponent is within acceptable "range"
 312             # NOTE: the weirdness of reassigning guard and round is due to
 313             #       the extra mantissa bits coming from tot[0..2]
 314
 315             with m.State("normalise_1"):
 316                 self.normalise_1(m, z, of, "normalise_2")
 317
 318             # ******
 319             # Second stage of normalisation.
 320             # NOTE: just like "align", this one keeps going round every clock
 321             #       until the result's exponent is within acceptable "range"
 322             # NOTE: the weirdness of reassigning guard and round is due to
 323             #       the extra mantissa bits coming from tot[0..2]
 324
 325             with m.State("normalise_2"):
 326                 self.normalise_2(m, z, of, "round")
 327
 328             # ******
 329             # rounding stage
 330
 331             with m.State("round"):
 332                 m.next = "corrections"
 333                 with m.If(of.guard & (of.round_bit | of.sticky | z.m[0])):
 334                     m.d.sync += z.m.eq(z.m + 1) # mantissa rounds up
 335                     with m.If(z.m == z.m1s): # all 1s
 336                         m.d.sync += z.e.eq(z.e + 1) # exponent rounds up
 337
 338             # ******
 339             # correction stage
 340
 341             with m.State("corrections"):
 342                 m.next = "pack"
 343                 # denormalised, correct exponent to zero
 344                 with m.If(z.is_denormalised()):
 345                     m.d.sync += z.m.eq(-127)
 346                 # FIX SIGN BUG: -a + a = +0.
 347                 with m.If((z.e == z.N126) & (z.m[0:] == 0)):
 348                     m.d.sync += z.s.eq(0)
 349
 350             # ******
 351             # pack stage
 352
 353             with m.State("pack"):
 354                 m.next = "put_z"
 355                 # if overflow occurs, return inf
 356                 with m.If(z.is_overflowed()):
 357                     m.d.sync += z.inf(0)
 358                 with m.Else():
 359                     m.d.sync += z.create(z.s, z.e, z.m)
 360
 361             # ******
 362             # put_z stage
 363
 364             with m.State("put_z"):
 365               m.d.sync += [
 366                   self.out_z.stb.eq(1),
 367                   self.out_z.v.eq(z.v)
 368               ]
 369               with m.If(self.out_z.stb & self.out_z.ack):
 370                   m.d.sync += self.out_z.stb.eq(0)
 371                   m.next = "get_a"
 372
 373         return m
 374
 375
 376 if __name__ == "__main__":
 377     alu = FPADD(width=32)
 378     main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
 379
 380
 381     # works... but don't use, just do "python fname.py convert -t v"
 382     #print (verilog.convert(alu, ports=[
 383     #                        ports=alu.in_a.ports() + \
 384     #                              alu.in_b.ports() + \
 385     #                              alu.out_z.ports())