src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat
   6 from nmigen.cli import main, verilog
   7
   8 from fpbase import FPNum, FPOp, Overflow, FPBase
   9
  10
  11 class FPADD(FPBase):
  12
  13     def __init__(self, width, single_cycle=False):
  14         FPBase.__init__(self)
  15         self.width = width
  16         self.single_cycle = single_cycle
  17
  18         self.in_a  = FPOp(width)
  19         self.in_b  = FPOp(width)
  20         self.out_z = FPOp(width)
  21
  22     def get_fragment(self, platform=None):
  23         """ creates the HDL code-fragment for FPAdd
  24         """
  25         m = Module()
  26
  27         # Latches
  28         a = FPNum(self.width)
  29         b = FPNum(self.width)
  30         z = FPNum(self.width, False)
  31
  32         w = z.m_width + 4
  33         tot = Signal(w) # sticky/round/guard, {mantissa} result, 1 overflow
  34
  35         of = Overflow()
  36
  37         with m.FSM() as fsm:
  38
  39             # ******
  40             # gets operand a
  41
  42             with m.State("get_a"):
  43                 self.get_op(m, self.in_a, a, "get_b")
  44
  45             # ******
  46             # gets operand b
  47
  48             with m.State("get_b"):
  49                 self.get_op(m, self.in_b, b, "special_cases")
  50
  51             # ******
  52             # special cases: NaNs, infs, zeros, denormalised
  53             # NOTE: some of these are unique to add.  see "Special Operations"
  54             # https://steve.hollasch.net/cgindex/coding/ieeefloat.html
  55
  56             with m.State("special_cases"):
  57
  58                 # if a is NaN or b is NaN return NaN
  59                 with m.If(a.is_nan() | b.is_nan()):
  60                     m.next = "put_z"
  61                     m.d.sync += z.nan(1)
  62
  63                 # XXX WEIRDNESS for FP16 non-canonical NaN handling
  64                 # under review
  65
  66                 ## if a is zero and b is NaN return -b
  67                 #with m.If(a.is_zero() & (a.s==0) & b.is_nan()):
  68                 #    m.next = "put_z"
  69                 #    m.d.sync += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
  70
  71                 ## if b is zero and a is NaN return -a
  72                 #with m.Elif(b.is_zero() & (b.s==0) & a.is_nan()):
  73                 #    m.next = "put_z"
  74                 #    m.d.sync += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
  75
  76                 ## if a is -zero and b is NaN return -b
  77                 #with m.Elif(a.is_zero() & (a.s==1) & b.is_nan()):
  78                 #    m.next = "put_z"
  79                 #    m.d.sync += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
  80
  81                 ## if b is -zero and a is NaN return -a
  82                 #with m.Elif(b.is_zero() & (b.s==1) & a.is_nan()):
  83                 #    m.next = "put_z"
  84                 #    m.d.sync += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
  85
  86                 # if a is inf return inf (or NaN)
  87                 with m.Elif(a.is_inf()):
  88                     m.next = "put_z"
  89                     m.d.sync += z.inf(a.s)
  90                     # if a is inf and signs don't match return NaN
  91                     with m.If((b.e == b.P128) & (a.s != b.s)):
  92                         m.d.sync += z.nan(1)
  93
  94                 # if b is inf return inf
  95                 with m.Elif(b.is_inf()):
  96                     m.next = "put_z"
  97                     m.d.sync += z.inf(b.s)
  98
  99                 # if a is zero and b zero return signed-a/b
 100                 with m.Elif(a.is_zero() & b.is_zero()):
 101                     m.next = "put_z"
 102                     m.d.sync += z.create(a.s & b.s, b.e, b.m[3:-1])
 103
 104                 # if a is zero return b
 105                 with m.Elif(a.is_zero()):
 106                     m.next = "put_z"
 107                     m.d.sync += z.create(b.s, b.e, b.m[3:-1])
 108
 109                 # if b is zero return a
 110                 with m.Elif(b.is_zero()):
 111                     m.next = "put_z"
 112                     m.d.sync += z.create(a.s, a.e, a.m[3:-1])
 113
 114                 # if a equal to -b return zero (+ve zero)
 115                 with m.Elif((a.s != b.s) & (a.m == b.m) & (a.e == b.e)):
 116                     m.next = "put_z"
 117                     m.d.sync += z.zero(0)
 118
 119                 # Denormalised Number checks
 120                 with m.Else():
 121                     m.next = "align"
 122                     self.denormalise(m, a)
 123                     self.denormalise(m, b)
 124
 125             # ******
 126             # align.
 127
 128             with m.State("align"):
 129                 if not self.single_cycle:
 130                     # NOTE: this does *not* do single-cycle multi-shifting,
 131                     #       it *STAYS* in the align state until exponents match
 132
 133                     # exponent of a greater than b: shift b down
 134                     with m.If(a.e > b.e):
 135                         m.d.sync += b.shift_down()
 136                     # exponent of b greater than a: shift a down
 137                     with m.Elif(a.e < b.e):
 138                         m.d.sync += a.shift_down()
 139                     # exponents equal: move to next stage.
 140                     with m.Else():
 141                         m.next = "add_0"
 142                 else:
 143                     # This one however (single-cycle) will do the shift
 144                     # in one go.
 145
 146                     # XXX TODO: the shifter used here is quite expensive
 147                     # having only one would be better
 148
 149                     ediff = Signal((len(a.e), True))
 150                     ediffr = Signal((len(a.e), True))
 151                     m.d.comb += ediff.eq(a.e - b.e)
 152                     m.d.comb += ediffr.eq(b.e - a.e)
 153                     with m.If(ediff > 0):
 154                         m.d.sync += b.shift_down_multi(ediff)
 155                     # exponent of b greater than a: shift a down
 156                     with m.Elif(ediff < 0):
 157                         m.d.sync += a.shift_down_multi(ediffr)
 158
 159                     m.next = "add_0"
 160
 161             # ******
 162             # First stage of add.  covers same-sign (add) and subtract
 163             # special-casing when mantissas are greater or equal, to
 164             # give greatest accuracy.
 165
 166             with m.State("add_0"):
 167                 m.next = "add_1"
 168                 m.d.sync += z.e.eq(a.e)
 169                 # same-sign (both negative or both positive) add mantissas
 170                 with m.If(a.s == b.s):
 171                     m.d.sync += [
 172                         tot.eq(Cat(a.m, 0) + Cat(b.m, 0)),
 173                         z.s.eq(a.s)
 174                     ]
 175                 # a mantissa greater than b, use a
 176                 with m.Elif(a.m >= b.m):
 177                     m.d.sync += [
 178                         tot.eq(Cat(a.m, 0) - Cat(b.m, 0)),
 179                         z.s.eq(a.s)
 180                     ]
 181                 # b mantissa greater than a, use b
 182                 with m.Else():
 183                     m.d.sync += [
 184                         tot.eq(Cat(b.m, 0) - Cat(a.m, 0)),
 185                         z.s.eq(b.s)
 186                 ]
 187
 188             # ******
 189             # Second stage of add: preparation for normalisation.
 190             # detects when tot sum is too big (tot[27] is kinda a carry bit)
 191
 192             with m.State("add_1"):
 193                 m.next = "normalise_1"
 194                 # tot[27] gets set when the sum overflows. shift result down
 195                 with m.If(tot[-1]):
 196                     m.d.sync += [
 197                         z.m.eq(tot[4:]),
 198                         of.guard.eq(tot[3]),
 199                         of.round_bit.eq(tot[2]),
 200                         of.sticky.eq(tot[1] | tot[0]),
 201                         z.e.eq(z.e + 1)
 202                 ]
 203                 # tot[27] zero case
 204                 with m.Else():
 205                     m.d.sync += [
 206                         z.m.eq(tot[3:]),
 207                         of.guard.eq(tot[2]),
 208                         of.round_bit.eq(tot[1]),
 209                         of.sticky.eq(tot[0])
 210                 ]
 211
 212             # ******
 213             # First stage of normalisation.
 214
 215             with m.State("normalise_1"):
 216                 self.normalise_1(m, z, of, "normalise_2")
 217
 218             # ******
 219             # Second stage of normalisation.
 220
 221             with m.State("normalise_2"):
 222                 self.normalise_2(m, z, of, "round")
 223
 224             # ******
 225             # rounding stage
 226
 227             with m.State("round"):
 228                 self.roundz(m, z, of, "corrections")
 229
 230             # ******
 231             # correction stage
 232
 233             with m.State("corrections"):
 234                 self.corrections(m, z, "pack")
 235
 236             # ******
 237             # pack stage
 238
 239             with m.State("pack"):
 240                 self.pack(m, z, "put_z")
 241
 242             # ******
 243             # put_z stage
 244
 245             with m.State("put_z"):
 246                 self.put_z(m, z, self.out_z, "get_a")
 247
 248         return m
 249
 250
 251 if __name__ == "__main__":
 252     alu = FPADD(width=32)
 253     main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
 254
 255
 256     # works... but don't use, just do "python fname.py convert -t v"
 257     #print (verilog.convert(alu, ports=[
 258     #                        ports=alu.in_a.ports() + \
 259     #                              alu.in_b.ports() + \
 260     #                              alu.out_z.ports())