src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat
   6 from nmigen.cli import main, verilog
   7
   8 from fpbase import FPNum, FPOp, Overflow, FPBase
   9
  10
  11 class FPADD(FPBase):
  12
  13     def __init__(self, width):
  14         FPBase.__init__(self)
  15         self.width = width
  16
  17         self.in_a  = FPOp(width)
  18         self.in_b  = FPOp(width)
  19         self.out_z = FPOp(width)
  20
  21     def get_fragment(self, platform=None):
  22         """ creates the HDL code-fragment for FPAdd
  23         """
  24         m = Module()
  25
  26         # Latches
  27         a = FPNum(self.width)
  28         b = FPNum(self.width)
  29         z = FPNum(self.width, False)
  30
  31         w = {32: 28, 64:57}[self.width]
  32         tot = Signal(w) # sticky/round/guard, {mantissa} result, 1 overflow
  33
  34         of = Overflow()
  35
  36         with m.FSM() as fsm:
  37
  38             # ******
  39             # gets operand a
  40
  41             with m.State("get_a"):
  42                 self.get_op(m, self.in_a, a, "get_b")
  43
  44             # ******
  45             # gets operand b
  46
  47             with m.State("get_b"):
  48                 self.get_op(m, self.in_b, b, "special_cases")
  49
  50             # ******
  51             # special cases: NaNs, infs, zeros, denormalised
  52             # NOTE: some of these are unique to add.  see "Special Operations"
  53             # https://steve.hollasch.net/cgindex/coding/ieeefloat.html
  54
  55             with m.State("special_cases"):
  56
  57                 # if a is NaN or b is NaN return NaN
  58                 with m.If(a.is_nan() | b.is_nan()):
  59                     m.next = "put_z"
  60                     m.d.sync += z.nan(1)
  61
  62                 # if a is inf return inf (or NaN)
  63                 with m.Elif(a.is_inf()):
  64                     m.next = "put_z"
  65                     m.d.sync += z.inf(a.s)
  66                     # if a is inf and signs don't match return NaN
  67                     with m.If((b.e == b.P128) & (a.s != b.s)):
  68                         m.d.sync += z.nan(b.s)
  69
  70                 # if b is inf return inf
  71                 with m.Elif(b.is_inf()):
  72                     m.next = "put_z"
  73                     m.d.sync += z.inf(b.s)
  74
  75                 # if a is zero and b zero return signed-a/b
  76                 with m.Elif(a.is_zero() & b.is_zero()):
  77                     m.next = "put_z"
  78                     m.d.sync += z.create(a.s & b.s, b.e, b.m[3:-1])
  79
  80                 # if a is zero return b
  81                 with m.Elif(a.is_zero()):
  82                     m.next = "put_z"
  83                     m.d.sync += z.create(b.s, b.e, b.m[3:-1])
  84
  85                 # if b is zero return a
  86                 with m.Elif(b.is_zero()):
  87                     m.next = "put_z"
  88                     m.d.sync += z.create(a.s, a.e, a.m[3:-1])
  89
  90                 # Denormalised Number checks
  91                 with m.Else():
  92                     m.next = "align"
  93                     self.denormalise(m, a)
  94                     self.denormalise(m, b)
  95
  96             # ******
  97             # align.  NOTE: this does *not* do single-cycle multi-shifting,
  98             #         it *STAYS* in the align state until the exponents match
  99
 100             with m.State("align"):
 101                 # exponent of a greater than b: increment b exp, shift b mant
 102                 with m.If(a.e > b.e):
 103                     m.d.sync += b.shift_down()
 104                 # exponent of b greater than a: increment a exp, shift a mant
 105                 with m.Elif(a.e < b.e):
 106                     m.d.sync += a.shift_down()
 107                 # exponents equal: move to next stage.
 108                 with m.Else():
 109                     m.next = "add_0"
 110
 111             # ******
 112             # First stage of add.  covers same-sign (add) and subtract
 113             # special-casing when mantissas are greater or equal, to
 114             # give greatest accuracy.
 115
 116             with m.State("add_0"):
 117                 m.next = "add_1"
 118                 m.d.sync += z.e.eq(a.e)
 119                 # same-sign (both negative or both positive) add mantissas
 120                 with m.If(a.s == b.s):
 121                     m.d.sync += [
 122                         tot.eq(Cat(a.m, 0) + Cat(b.m, 0)),
 123                         z.s.eq(a.s)
 124                     ]
 125                 # a mantissa greater than b, use a
 126                 with m.Elif(a.m >= b.m):
 127                     m.d.sync += [
 128                         tot.eq(Cat(a.m, 0) - Cat(b.m, 0)),
 129                         z.s.eq(a.s)
 130                     ]
 131                 # b mantissa greater than a, use b
 132                 with m.Else():
 133                     m.d.sync += [
 134                         tot.eq(Cat(b.m, 0) - Cat(a.m, 0)),
 135                         z.s.eq(b.s)
 136                 ]
 137
 138             # ******
 139             # Second stage of add: preparation for normalisation.
 140             # detects when tot sum is too big (tot[27] is kinda a carry bit)
 141
 142             with m.State("add_1"):
 143                 m.next = "normalise_1"
 144                 # tot[27] gets set when the sum overflows. shift result down
 145                 with m.If(tot[-1]):
 146                     m.d.sync += [
 147                         z.m.eq(tot[4:]),
 148                         of.guard.eq(tot[3]),
 149                         of.round_bit.eq(tot[2]),
 150                         of.sticky.eq(tot[1] | tot[0]),
 151                         z.e.eq(z.e + 1)
 152                 ]
 153                 # tot[27] zero case
 154                 with m.Else():
 155                     m.d.sync += [
 156                         z.m.eq(tot[3:]),
 157                         of.guard.eq(tot[2]),
 158                         of.round_bit.eq(tot[1]),
 159                         of.sticky.eq(tot[0])
 160                 ]
 161
 162             # ******
 163             # First stage of normalisation.
 164
 165             with m.State("normalise_1"):
 166                 self.normalise_1(m, z, of, "normalise_2")
 167
 168             # ******
 169             # Second stage of normalisation.
 170
 171             with m.State("normalise_2"):
 172                 self.normalise_2(m, z, of, "round")
 173
 174             # ******
 175             # rounding stage
 176
 177             with m.State("round"):
 178                 self.roundz(m, z, of, "corrections")
 179
 180             # ******
 181             # correction stage
 182
 183             with m.State("corrections"):
 184                 self.corrections(m, z, "pack")
 185
 186             # ******
 187             # pack stage
 188
 189             with m.State("pack"):
 190                 self.pack(m, z, "put_z")
 191
 192             # ******
 193             # put_z stage
 194
 195             with m.State("put_z"):
 196                 self.put_z(m, z, self.out_z, "get_a")
 197
 198         return m
 199
 200
 201 if __name__ == "__main__":
 202     alu = FPADD(width=32)
 203     main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
 204
 205
 206     # works... but don't use, just do "python fname.py convert -t v"
 207     #print (verilog.convert(alu, ports=[
 208     #                        ports=alu.in_a.ports() + \
 209     #                              alu.in_b.ports() + \
 210     #                              alu.out_z.ports())