1 """ Pipeline and BufferedPipeline implementation, conforming to the same API.
2 For multi-input and multi-output variants, see multipipe.
7 a strategically very important function that is identical in function
8 to nmigen's Signal.eq function, except it may take objects, or a list
9 of objects, or a tuple of objects, and where objects may also be
15 stage requires compliance with a strict API that may be
16 implemented in several means, including as a static class.
17 the methods of a stage instance must be as follows:
19 * ispec() - Input data format specification
20 returns an object or a list or tuple of objects, or
21 a Record, each object having an "eq" function which
22 takes responsibility for copying by assignment all
24 * ospec() - Output data format specification
25 requirements as for ospec
26 * process(m, i) - Processes an ispec-formatted object
27 returns a combinatorial block of a result that
28 may be assigned to the output, by way of the "eq"
30 * setup(m, i) - Optional function for setting up submodules
31 may be used for more complex stages, to link
32 the input (i) to submodules. must take responsibility
33 for adding those submodules to the module (m).
34 the submodules must be combinatorial blocks and
35 must have their inputs and output linked combinatorially.
37 Both StageCls (for use with non-static classes) and Stage (for use
38 by static classes) are abstract classes from which, for convenience
39 and as a courtesy to other developers, anything conforming to the
40 Stage API may *choose* to derive.
45 A useful combinatorial wrapper around stages that chains them together
46 and then presents a Stage-API-conformant interface. By presenting
47 the same API as the stages it wraps, it can clearly be used recursively.
52 A convenience class that takes an input shape, output shape, a
53 "processing" function and an optional "setup" function. Honestly
54 though, there's not much more effort to just... create a class
55 that returns a couple of Records (see ExampleAddRecordStage in
61 A convenience class that takes a single function as a parameter,
62 that is chain-called to create the exact same input and output spec.
63 It has a process() function that simply returns its input.
65 Instances of this class are completely redundant if handed to
66 StageChain, however when passed to UnbufferedPipeline they
67 can be used to introduce a single clock delay.
72 The base class for pipelines. Contains previous and next ready/valid/data.
73 Also has an extremely useful "connect" function that can be used to
74 connect a chain of pipelines and present the exact same prev/next
80 A simple stalling clock-synchronised pipeline that has no buffering
81 (unlike BufferedPipeline). Data flows on *every* clock cycle when
82 the conditions are right (this is nominally when the input is valid
83 and the output is ready).
85 A stall anywhere along the line will result in a stall back-propagating
86 down the entire chain. The BufferedPipeline by contrast will buffer
87 incoming data, allowing previous stages one clock cycle's grace before
90 An advantage of the UnbufferedPipeline over the Buffered one is
91 that the amount of logic needed (number of gates) is greatly
92 reduced (no second set of buffers basically)
94 The disadvantage of the UnbufferedPipeline is that the valid/ready
95 logic, if chained together, is *combinatorial*, resulting in
96 progressively larger gate delay.
101 A convenience class that, because UnbufferedPipeline introduces a single
102 clock delay, when its stage is a PassThroughStage, it results in a Pipeline
103 stage that, duh, delays its (unmodified) input by one clock cycle.
108 nmigen implementation of buffered pipeline stage, based on zipcpu:
109 https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html
111 this module requires quite a bit of thought to understand how it works
112 (and why it is needed in the first place). reading the above is
113 *strongly* recommended.
115 unlike john dawson's IEEE754 FPU STB/ACK signalling, which requires
116 the STB / ACK signals to raise and lower (on separate clocks) before
117 data may proceeed (thus only allowing one piece of data to proceed
118 on *ALTERNATE* cycles), the signalling here is a true pipeline
119 where data will flow on *every* clock when the conditions are right.
121 input acceptance conditions are when:
122 * incoming previous-stage strobe (p.i_valid) is HIGH
123 * outgoing previous-stage ready (p.o_ready) is LOW
125 output transmission conditions are when:
126 * outgoing next-stage strobe (n.o_valid) is HIGH
127 * outgoing next-stage ready (n.i_ready) is LOW
129 the tricky bit is when the input has valid data and the output is not
130 ready to accept it. if it wasn't for the clock synchronisation, it
131 would be possible to tell the input "hey don't send that data, we're
132 not ready". unfortunately, it's not possible to "change the past":
133 the previous stage *has no choice* but to pass on its data.
135 therefore, the incoming data *must* be accepted - and stored: that
136 is the responsibility / contract that this stage *must* accept.
137 on the same clock, it's possible to tell the input that it must
138 not send any more data. this is the "stall" condition.
140 we now effectively have *two* possible pieces of data to "choose" from:
141 the buffered data, and the incoming data. the decision as to which
142 to process and output is based on whether we are in "stall" or not.
143 i.e. when the next stage is no longer ready, the output comes from
144 the buffer if a stall had previously occurred, otherwise it comes
145 direct from processing the input.
147 this allows us to respect a synchronous "travelling STB" with what
148 dan calls a "buffered handshake".
150 it's quite a complex state machine!
153 from nmigen
import Signal
, Cat
, Const
, Mux
, Module
, Value
154 from nmigen
.cli
import verilog
, rtlil
155 from nmigen
.hdl
.ast
import ArrayProxy
156 from nmigen
.hdl
.rec
import Record
, Layout
158 from abc
import ABCMeta
, abstractmethod
159 from collections
.abc
import Sequence
163 """ contains signals that come *from* the previous stage (both in and out)
164 * i_valid: previous stage indicating all incoming data is valid.
165 may be a multi-bit signal, where all bits are required
166 to be asserted to indicate "valid".
167 * o_ready: output to next stage indicating readiness to accept data
168 * i_data : an input - added by the user of this class
171 def __init__(self
, i_width
=1, stage_ctl
=False):
172 self
.stage_ctl
= stage_ctl
173 self
.i_valid
= Signal(i_width
, name
="p_i_valid") # prev >>in self
174 self
._o
_ready
= Signal(name
="p_o_ready") # prev <<out self
175 self
.i_data
= None # XXX MUST BE ADDED BY USER
177 self
.s_o_ready
= Signal(name
="p_s_o_rdy") # prev <<out self
181 """ public-facing API: indicates (externally) that stage is ready
184 return self
.s_o_ready
# set dynamically by stage
185 return self
._o
_ready
# return this when not under dynamic control
187 def _connect_in(self
, prev
):
188 """ internal helper function to connect stage to an input source.
189 do not use to connect stage-to-stage!
191 return [self
.i_valid
.eq(prev
.i_valid
),
192 prev
.o_ready
.eq(self
.o_ready
),
193 eq(self
.i_data
, prev
.i_data
),
196 def i_valid_logic(self
):
197 vlen
= len(self
.i_valid
)
199 # multi-bit case: valid only when i_valid is all 1s
200 all1s
= Const(-1, (len(self
.i_valid
), False))
201 i_valid
= (self
.i_valid
== all1s
)
203 # single-bit i_valid case
204 i_valid
= self
.i_valid
206 # when stage indicates not ready, incoming data
207 # must "appear" to be not ready too
209 i_valid
= i_valid
& self
.s_o_ready
215 """ contains the signals that go *to* the next stage (both in and out)
216 * o_valid: output indicating to next stage that data is valid
217 * i_ready: input from next stage indicating that it can accept data
218 * o_data : an output - added by the user of this class
220 def __init__(self
, stage_ctl
=False):
221 self
.stage_ctl
= stage_ctl
222 self
._o
_valid
= Signal(name
="n_o_valid") # self out>> next
223 self
.i_ready
= Signal(name
="n_i_ready") # self <<in next
224 self
.o_data
= None # XXX MUST BE ADDED BY USER
225 self
.d_valid
= Signal(reset
=1) # INTERNAL (data valid)
229 """ public-facing API: indicates (externally) that data is valid
233 return self
.s_o_valid
235 def i_ready_logic(self
):
236 """ public-facing API: receives indication that transmit is possible
240 return self
.i_ready
& self
.s_o_valid
242 def connect_to_next(self
, nxt
):
243 """ helper function to connect to the next stage data/valid/ready.
244 data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
245 use this when connecting stage-to-stage
247 return [nxt
.i_valid
.eq(self
.o_valid
),
248 self
.i_ready
.eq(nxt
.o_ready
),
249 eq(nxt
.i_data
, self
.o_data
),
252 def _connect_out(self
, nxt
):
253 """ internal helper function to connect stage to an output source.
254 do not use to connect stage-to-stage!
256 return [nxt
.o_valid
.eq(self
.o_valid
),
257 self
.i_ready
.eq(nxt
.i_ready
),
258 eq(nxt
.o_data
, self
.o_data
),
263 """ makes signals equal: a helper routine which identifies if it is being
264 passed a list (or tuple) of objects, or signals, or Records, and calls
265 the objects' eq function.
267 complex objects (classes) can be used: they must follow the
268 convention of having an eq member function, which takes the
269 responsibility of further calling eq and returning a list of
272 Record is a special (unusual, recursive) case, where the input may be
273 specified as a dictionary (which may contain further dictionaries,
274 recursively), where the field names of the dictionary must match
275 the Record's field spec. Alternatively, an object with the same
276 member names as the Record may be assigned: it does not have to
279 ArrayProxy is also special-cased, it's a bit messy: whilst ArrayProxy
280 has an eq function, the object being assigned to it (e.g. a python
281 object) might not. despite the *input* having an eq function,
282 that doesn't help us, because it's the *ArrayProxy* that's being
283 assigned to. so.... we cheat. use the ports() function of the
284 python object, enumerate them, find out the list of Signals that way,
288 if isinstance(o
, dict):
289 for (k
, v
) in o
.items():
290 print ("d-eq", v
, i
[k
])
291 res
.append(v
.eq(i
[k
]))
294 if not isinstance(o
, Sequence
):
296 for (ao
, ai
) in zip(o
, i
):
297 #print ("eq", ao, ai)
298 if isinstance(ao
, Record
):
299 for idx
, (field_name
, field_shape
, _
) in enumerate(ao
.layout
):
300 if isinstance(field_shape
, Layout
):
304 if hasattr(val
, field_name
): # check for attribute
305 val
= getattr(val
, field_name
)
307 val
= val
[field_name
] # dictionary-style specification
308 rres
= eq(ao
.fields
[field_name
], val
)
310 elif isinstance(ao
, ArrayProxy
) and not isinstance(ai
, Value
):
312 op
= getattr(ao
, p
.name
)
313 #print (op, p, p.name)
315 if not isinstance(rres
, Sequence
):
320 if not isinstance(rres
, Sequence
):
326 class StageCls(metaclass
=ABCMeta
):
327 """ Class-based "Stage" API. requires instantiation (after derivation)
329 see "Stage API" above.. Note: python does *not* require derivation
330 from this class. All that is required is that the pipelines *have*
331 the functions listed in this class. Derivation from this class
332 is therefore merely a "courtesy" to maintainers.
335 def ispec(self
): pass # REQUIRED
337 def ospec(self
): pass # REQUIRED
339 #def setup(self, m, i): pass # OPTIONAL
341 def process(self
, i
): pass # REQUIRED
344 class Stage(metaclass
=ABCMeta
):
345 """ Static "Stage" API. does not require instantiation (after derivation)
347 see "Stage API" above. Note: python does *not* require derivation
348 from this class. All that is required is that the pipelines *have*
349 the functions listed in this class. Derivation from this class
350 is therefore merely a "courtesy" to maintainers.
362 #def setup(m, i): pass
369 class RecordBasedStage(Stage
):
370 """ convenience class which provides a Records-based layout.
371 honestly it's a lot easier just to create a direct Records-based
372 class (see ExampleAddRecordStage)
374 def __init__(self
, in_shape
, out_shape
, processfn
, setupfn
=None):
375 self
.in_shape
= in_shape
376 self
.out_shape
= out_shape
377 self
.__process
= processfn
378 self
.__setup
= setupfn
379 def ispec(self
): return Record(self
.in_shape
)
380 def ospec(self
): return Record(self
.out_shape
)
381 def process(seif
, i
): return self
.__process
(i
)
382 def setup(seif
, m
, i
): return self
.__setup
(m
, i
)
385 class StageChain(StageCls
):
386 """ pass in a list of stages, and they will automatically be
387 chained together via their input and output specs into a
390 the end result basically conforms to the exact same Stage API.
392 * input to this class will be the input of the first stage
393 * output of first stage goes into input of second
394 * output of second goes into input into third (etc. etc.)
395 * the output of this class will be the output of the last stage
397 def __init__(self
, chain
, specallocate
=False):
399 self
.specallocate
= specallocate
402 return self
.chain
[0].ispec()
405 return self
.chain
[-1].ospec()
407 def setup(self
, m
, i
):
408 for (idx
, c
) in enumerate(self
.chain
):
409 if hasattr(c
, "setup"):
410 c
.setup(m
, i
) # stage may have some module stuff
411 if self
.specallocate
:
412 o
= self
.chain
[idx
].ospec() # last assignment survives
413 m
.d
.comb
+= eq(o
, c
.process(i
)) # process input into "o"
415 o
= c
.process(i
) # store input into "o"
416 if idx
!= len(self
.chain
)-1:
417 if self
.specallocate
:
418 ni
= self
.chain
[idx
+1].ispec() # new input on next loop
419 m
.d
.comb
+= eq(ni
, o
) # assign to next input
423 self
.o
= o
# last loop is the output
425 def process(self
, i
):
426 return self
.o
# conform to Stage API: return last-loop output
430 """ Common functions for Pipeline API
432 def __init__(self
, in_multi
=None, stage_ctl
=False):
433 """ Base class containing ready/valid/data to previous and next stages
435 * p: contains ready/valid to the previous stage
436 * n: contains ready/valid to the next stage
438 Except when calling Controlbase.connect(), user must also:
439 * add i_data member to PrevControl (p) and
440 * add o_data member to NextControl (n)
442 # set up input and output IO ACK (prev/next ready/valid)
443 self
.p
= PrevControl(in_multi
, stage_ctl
)
444 self
.n
= NextControl(stage_ctl
)
446 def connect_to_next(self
, nxt
):
447 """ helper function to connect to the next stage data/valid/ready.
449 return self
.n
.connect_to_next(nxt
.p
)
451 def _connect_in(self
, prev
):
452 """ internal helper function to connect stage to an input source.
453 do not use to connect stage-to-stage!
455 return self
.p
._connect
_in
(prev
.p
)
457 def _connect_out(self
, nxt
):
458 """ internal helper function to connect stage to an output source.
459 do not use to connect stage-to-stage!
461 return self
.n
._connect
_out
(nxt
.n
)
463 def connect(self
, pipechain
):
464 """ connects a chain (list) of Pipeline instances together and
465 links them to this ControlBase instance:
467 in <----> self <---> out
470 [pipe1, pipe2, pipe3, pipe4]
473 out---in out--in out---in
475 Also takes care of allocating i_data/o_data, by looking up
476 the data spec for each end of the pipechain. i.e It is NOT
477 necessary to allocate self.p.i_data or self.n.o_data manually:
478 this is handled AUTOMATICALLY, here.
480 Basically this function is the direct equivalent of StageChain,
481 except that unlike StageChain, the Pipeline logic is followed.
483 Just as StageChain presents an object that conforms to the
484 Stage API from a list of objects that also conform to the
485 Stage API, an object that calls this Pipeline connect function
486 has the exact same pipeline API as the list of pipline objects
489 Thus it becomes possible to build up larger chains recursively.
490 More complex chains (multi-input, multi-output) will have to be
493 eqs
= [] # collated list of assignment statements
495 # connect inter-chain
496 for i
in range(len(pipechain
)-1):
498 pipe2
= pipechain
[i
+1]
499 eqs
+= pipe1
.connect_to_next(pipe2
)
501 # connect front of chain to ourselves
503 self
.p
.i_data
= front
.stage
.ispec()
504 eqs
+= front
._connect
_in
(self
)
506 # connect end of chain to ourselves
508 self
.n
.o_data
= end
.stage
.ospec()
509 eqs
+= end
._connect
_out
(self
)
513 def set_input(self
, i
):
514 """ helper function to set the input data
516 return eq(self
.p
.i_data
, i
)
519 res
= [self
.p
.i_valid
, self
.n
.i_ready
,
520 self
.n
.o_valid
, self
.p
.o_ready
,
522 if hasattr(self
.p
.i_data
, "ports"):
523 res
+= self
.p
.i_data
.ports()
526 if hasattr(self
.n
.o_data
, "ports"):
527 res
+= self
.n
.o_data
.ports()
532 def _elaborate(self
, platform
):
533 """ handles case where stage has dynamic ready/valid functions
536 if not self
.n
.stage_ctl
:
539 # when the pipeline (buffered or otherwise) says "ready",
540 # test the *stage* "ready".
542 with m
.If(self
.p
._o
_ready
):
543 m
.d
.comb
+= self
.p
.s_o_ready
.eq(self
.stage
.p_o_ready
)
545 m
.d
.comb
+= self
.p
.s_o_ready
.eq(0)
547 # bring data valid into n-control
548 m
.d
.comb
+= self
.n
.d_valid
.eq(self
.stage
.d_valid
)
553 class BufferedPipeline(ControlBase
):
554 """ buffered pipeline stage. data and strobe signals travel in sync.
555 if ever the input is ready and the output is not, processed data
556 is shunted in a temporary register.
558 Argument: stage. see Stage API above
560 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
561 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
562 stage-1 p.i_data >>in stage n.o_data out>> stage+1
568 input data p.i_data is read (only), is processed and goes into an
569 intermediate result store [process()]. this is updated combinatorially.
571 in a non-stall condition, the intermediate result will go into the
572 output (update_output). however if ever there is a stall, it goes
573 into r_data instead [update_buffer()].
575 when the non-stall condition is released, r_data is the first
576 to be transferred to the output [flush_buffer()], and the stall
579 on the next cycle (as long as stall is not raised again) the
580 input may begin to be processed and transferred directly to output.
583 def __init__(self
, stage
, stage_ctl
=False):
584 ControlBase
.__init
__(self
, stage_ctl
=stage_ctl
)
587 # set up the input and output data
588 self
.p
.i_data
= stage
.ispec() # input type
589 self
.n
.o_data
= stage
.ospec()
591 def elaborate(self
, platform
):
593 self
.m
= ControlBase
._elaborate
(self
, platform
)
595 result
= self
.stage
.ospec()
596 r_data
= self
.stage
.ospec()
597 if hasattr(self
.stage
, "setup"):
598 self
.stage
.setup(self
.m
, self
.p
.i_data
)
600 # establish some combinatorial temporaries
601 o_n_validn
= Signal(reset_less
=True)
602 i_p_valid_o_p_ready
= Signal(reset_less
=True)
603 p_i_valid
= Signal(reset_less
=True)
604 self
.m
.d
.comb
+= [p_i_valid
.eq(self
.p
.i_valid_logic()),
605 o_n_validn
.eq(~self
.n
.o_valid
),
606 i_p_valid_o_p_ready
.eq(p_i_valid
& self
.p
.o_ready
),
609 # store result of processing in combinatorial temporary
610 self
.m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
612 # if not in stall condition, update the temporary register
613 with self
.m
.If(self
.p
.o_ready
): # not stalled
614 self
.m
.d
.sync
+= eq(r_data
, result
) # update buffer
616 with self
.m
.If(self
.n
.i_ready
): # next stage is ready
617 with self
.m
.If(self
.p
._o
_ready
): # not stalled
618 # nothing in buffer: send (processed) input direct to output
619 self
.m
.d
.sync
+= [self
.n
._o
_valid
.eq(p_i_valid
),
620 eq(self
.n
.o_data
, result
), # update output
622 with self
.m
.Else(): # p.o_ready is false, and something in buffer
623 # Flush the [already processed] buffer to the output port.
624 self
.m
.d
.sync
+= [self
.n
._o
_valid
.eq(1), # reg empty
625 eq(self
.n
.o_data
, r_data
), # flush buffer
626 self
.p
._o
_ready
.eq(1), # clear stall
628 # ignore input, since p.o_ready is also false.
630 # (n.i_ready) is false here: next stage is ready
631 with self
.m
.Elif(o_n_validn
): # next stage being told "ready"
632 self
.m
.d
.sync
+= [self
.n
._o
_valid
.eq(p_i_valid
),
633 self
.p
._o
_ready
.eq(1), # Keep the buffer empty
634 eq(self
.n
.o_data
, result
), # set output data
637 # (n.i_ready) false and (n.o_valid) true:
638 with self
.m
.Elif(i_p_valid_o_p_ready
):
639 # If next stage *is* ready, and not stalled yet, accept input
640 self
.m
.d
.sync
+= self
.p
._o
_ready
.eq(~
(p_i_valid
& self
.n
.o_valid
))
645 class UnbufferedPipeline(ControlBase
):
646 """ A simple pipeline stage with single-clock synchronisation
647 and two-way valid/ready synchronised signalling.
649 Note that a stall in one stage will result in the entire pipeline
652 Also that unlike BufferedPipeline, the valid/ready signalling does NOT
653 travel synchronously with the data: the valid/ready signalling
654 combines in a *combinatorial* fashion. Therefore, a long pipeline
655 chain will lengthen propagation delays.
657 Argument: stage. see Stage API, above
659 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
660 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
661 stage-1 p.i_data >>in stage n.o_data out>> stage+1
669 p.i_data : StageInput, shaped according to ispec
671 p.o_data : StageOutput, shaped according to ospec
673 r_data : input_shape according to ispec
674 A temporary (buffered) copy of a prior (valid) input.
675 This is HELD if the output is not ready. It is updated
677 result: output_shape according to ospec
678 The output of the combinatorial logic. it is updated
679 COMBINATORIALLY (no clock dependence).
682 def __init__(self
, stage
, stage_ctl
=False):
683 ControlBase
.__init
__(self
, stage_ctl
=stage_ctl
)
686 # set up the input and output data
687 self
.p
.i_data
= stage
.ispec() # input type
688 self
.n
.o_data
= stage
.ospec() # output type
690 def elaborate(self
, platform
):
691 self
.m
= ControlBase
._elaborate
(self
, platform
)
693 data_valid
= Signal() # is data valid or not
694 r_data
= self
.stage
.ispec() # input type
695 if hasattr(self
.stage
, "setup"):
696 self
.stage
.setup(self
.m
, r_data
)
699 p_i_valid
= Signal(reset_less
=True)
700 pv
= Signal(reset_less
=True)
701 self
.m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_logic())
702 self
.m
.d
.comb
+= pv
.eq(self
.p
.i_valid
& self
.p
.o_ready
)
704 self
.m
.d
.comb
+= self
.n
._o
_valid
.eq(data_valid
)
705 self
.m
.d
.comb
+= self
.p
._o
_ready
.eq(~data_valid | self
.n
.i_ready
)
706 self
.m
.d
.sync
+= data_valid
.eq(p_i_valid | \
707 (~self
.n
.i_ready
& data_valid
))
709 self
.m
.d
.sync
+= eq(r_data
, self
.p
.i_data
)
710 self
.m
.d
.comb
+= eq(self
.n
.o_data
, self
.stage
.process(r_data
))
714 class PassThroughStage(StageCls
):
715 """ a pass-through stage which has its input data spec equal to its output,
716 and "passes through" its data from input to output.
718 def __init__(self
, iospecfn
):
719 self
.iospecfn
= iospecfn
720 def ispec(self
): return self
.iospecfn()
721 def ospec(self
): return self
.iospecfn()
722 def process(self
, i
): return i
725 class RegisterPipeline(UnbufferedPipeline
):
726 """ A pipeline stage that delays by one clock cycle, creating a
727 sync'd latch out of o_data and o_valid as an indirect byproduct
728 of using PassThroughStage
730 def __init__(self
, iospecfn
):
731 UnbufferedPipeline
.__init
__(self
, PassThroughStage(iospecfn
))