ef037fb95d2091dab1207835b055b0018dc891b7
1 """ Pipeline and BufferedPipeline implementation, conforming to the same API.
2 For multi-input and multi-output variants, see multipipe.
7 a strategically very important function that is identical in function
8 to nmigen's Signal.eq function, except it may take objects, or a list
9 of objects, or a tuple of objects, and where objects may also be
15 stage requires compliance with a strict API that may be
16 implemented in several means, including as a static class.
17 the methods of a stage instance must be as follows:
19 * ispec() - Input data format specification
20 returns an object or a list or tuple of objects, or
21 a Record, each object having an "eq" function which
22 takes responsibility for copying by assignment all
24 * ospec() - Output data format specification
25 requirements as for ospec
26 * process(m, i) - Processes an ispec-formatted object
27 returns a combinatorial block of a result that
28 may be assigned to the output, by way of the "eq"
30 * setup(m, i) - Optional function for setting up submodules
31 may be used for more complex stages, to link
32 the input (i) to submodules. must take responsibility
33 for adding those submodules to the module (m).
34 the submodules must be combinatorial blocks and
35 must have their inputs and output linked combinatorially.
37 Both StageCls (for use with non-static classes) and Stage (for use
38 by static classes) are abstract classes from which, for convenience
39 and as a courtesy to other developers, anything conforming to the
40 Stage API may *choose* to derive.
45 A useful combinatorial wrapper around stages that chains them together
46 and then presents a Stage-API-conformant interface. By presenting
47 the same API as the stages it wraps, it can clearly be used recursively.
52 A convenience class that takes an input shape, output shape, a
53 "processing" function and an optional "setup" function. Honestly
54 though, there's not much more effort to just... create a class
55 that returns a couple of Records (see ExampleAddRecordStage in
61 A convenience class that takes a single function as a parameter,
62 that is chain-called to create the exact same input and output spec.
63 It has a process() function that simply returns its input.
65 Instances of this class are completely redundant if handed to
66 StageChain, however when passed to UnbufferedPipeline they
67 can be used to introduce a single clock delay.
72 The base class for pipelines. Contains previous and next ready/valid/data.
73 Also has an extremely useful "connect" function that can be used to
74 connect a chain of pipelines and present the exact same prev/next
80 A simple stalling clock-synchronised pipeline that has no buffering
81 (unlike BufferedPipeline). Data flows on *every* clock cycle when
82 the conditions are right (this is nominally when the input is valid
83 and the output is ready).
85 A stall anywhere along the line will result in a stall back-propagating
86 down the entire chain. The BufferedPipeline by contrast will buffer
87 incoming data, allowing previous stages one clock cycle's grace before
90 An advantage of the UnbufferedPipeline over the Buffered one is
91 that the amount of logic needed (number of gates) is greatly
92 reduced (no second set of buffers basically)
94 The disadvantage of the UnbufferedPipeline is that the valid/ready
95 logic, if chained together, is *combinatorial*, resulting in
96 progressively larger gate delay.
101 A convenience class that, because UnbufferedPipeline introduces a single
102 clock delay, when its stage is a PassThroughStage, it results in a Pipeline
103 stage that, duh, delays its (unmodified) input by one clock cycle.
108 nmigen implementation of buffered pipeline stage, based on zipcpu:
109 https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html
111 this module requires quite a bit of thought to understand how it works
112 (and why it is needed in the first place). reading the above is
113 *strongly* recommended.
115 unlike john dawson's IEEE754 FPU STB/ACK signalling, which requires
116 the STB / ACK signals to raise and lower (on separate clocks) before
117 data may proceeed (thus only allowing one piece of data to proceed
118 on *ALTERNATE* cycles), the signalling here is a true pipeline
119 where data will flow on *every* clock when the conditions are right.
121 input acceptance conditions are when:
122 * incoming previous-stage strobe (p.i_valid) is HIGH
123 * outgoing previous-stage ready (p.o_ready) is LOW
125 output transmission conditions are when:
126 * outgoing next-stage strobe (n.o_valid) is HIGH
127 * outgoing next-stage ready (n.i_ready) is LOW
129 the tricky bit is when the input has valid data and the output is not
130 ready to accept it. if it wasn't for the clock synchronisation, it
131 would be possible to tell the input "hey don't send that data, we're
132 not ready". unfortunately, it's not possible to "change the past":
133 the previous stage *has no choice* but to pass on its data.
135 therefore, the incoming data *must* be accepted - and stored: that
136 is the responsibility / contract that this stage *must* accept.
137 on the same clock, it's possible to tell the input that it must
138 not send any more data. this is the "stall" condition.
140 we now effectively have *two* possible pieces of data to "choose" from:
141 the buffered data, and the incoming data. the decision as to which
142 to process and output is based on whether we are in "stall" or not.
143 i.e. when the next stage is no longer ready, the output comes from
144 the buffer if a stall had previously occurred, otherwise it comes
145 direct from processing the input.
147 this allows us to respect a synchronous "travelling STB" with what
148 dan calls a "buffered handshake".
150 it's quite a complex state machine!
153 from nmigen
import Signal
, Cat
, Const
, Mux
, Module
, Value
154 from nmigen
.cli
import verilog
, rtlil
155 from nmigen
.hdl
.ast
import ArrayProxy
156 from nmigen
.hdl
.rec
import Record
, Layout
158 from abc
import ABCMeta
, abstractmethod
159 from collections
.abc
import Sequence
163 """ contains signals that come *from* the previous stage (both in and out)
164 * i_valid: previous stage indicating all incoming data is valid.
165 may be a multi-bit signal, where all bits are required
166 to be asserted to indicate "valid".
167 * o_ready: output to next stage indicating readiness to accept data
168 * i_data : an input - added by the user of this class
171 def __init__(self
, i_width
=1, stage_ctl
=False):
172 self
.stage_ctl
= stage_ctl
173 self
.i_valid
= Signal(i_width
, name
="p_i_valid") # prev >>in self
174 self
._o
_ready
= Signal(name
="p_o_ready") # prev <<out self
175 self
.i_data
= None # XXX MUST BE ADDED BY USER
177 self
.s_o_ready
= Signal(name
="p_s_o_rdy") # prev <<out self
182 return self
.s_o_ready
185 def _connect_in(self
, prev
):
186 """ internal helper function to connect stage to an input source.
187 do not use to connect stage-to-stage!
189 return [self
.i_valid
.eq(prev
.i_valid
),
190 prev
.o_ready
.eq(self
.o_ready
),
191 eq(self
.i_data
, prev
.i_data
),
194 def i_valid_logic(self
):
195 vlen
= len(self
.i_valid
)
196 if vlen
> 1: # multi-bit case: valid only when i_valid is all 1s
197 all1s
= Const(-1, (len(self
.i_valid
), False))
198 return self
.i_valid
== all1s
199 # single-bit i_valid case
204 """ contains the signals that go *to* the next stage (both in and out)
205 * o_valid: output indicating to next stage that data is valid
206 * i_ready: input from next stage indicating that it can accept data
207 * o_data : an output - added by the user of this class
209 def __init__(self
, stage_ctl
=False):
210 self
.stage_ctl
= stage_ctl
211 self
._o
_valid
= Signal(name
="n_o_valid") # self out>> next
212 self
.i_ready
= Signal(name
="n_i_ready") # self <<in next
213 self
.o_data
= None # XXX MUST BE ADDED BY USER
215 self
.s_o_valid
= Signal(name
="n_s_o_vld") # self out>> next
220 return self
.s_o_valid
223 def connect_to_next(self
, nxt
):
224 """ helper function to connect to the next stage data/valid/ready.
225 data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
226 use this when connecting stage-to-stage
228 return [nxt
.i_valid
.eq(self
.o_valid
),
229 self
.i_ready
.eq(nxt
.o_ready
),
230 eq(nxt
.i_data
, self
.o_data
),
233 def _connect_out(self
, nxt
):
234 """ internal helper function to connect stage to an output source.
235 do not use to connect stage-to-stage!
237 return [nxt
.o_valid
.eq(self
.o_valid
),
238 self
.i_ready
.eq(nxt
.i_ready
),
239 eq(nxt
.o_data
, self
.o_data
),
244 """ makes signals equal: a helper routine which identifies if it is being
245 passed a list (or tuple) of objects, or signals, or Records, and calls
246 the objects' eq function.
248 complex objects (classes) can be used: they must follow the
249 convention of having an eq member function, which takes the
250 responsibility of further calling eq and returning a list of
253 Record is a special (unusual, recursive) case, where the input may be
254 specified as a dictionary (which may contain further dictionaries,
255 recursively), where the field names of the dictionary must match
256 the Record's field spec. Alternatively, an object with the same
257 member names as the Record may be assigned: it does not have to
260 ArrayProxy is also special-cased, it's a bit messy: whilst ArrayProxy
261 has an eq function, the object being assigned to it (e.g. a python
262 object) might not. despite the *input* having an eq function,
263 that doesn't help us, because it's the *ArrayProxy* that's being
264 assigned to. so.... we cheat. use the ports() function of the
265 python object, enumerate them, find out the list of Signals that way,
269 if isinstance(o
, dict):
270 for (k
, v
) in o
.items():
271 print ("d-eq", v
, i
[k
])
272 res
.append(v
.eq(i
[k
]))
275 if not isinstance(o
, Sequence
):
277 for (ao
, ai
) in zip(o
, i
):
278 #print ("eq", ao, ai)
279 if isinstance(ao
, Record
):
280 for idx
, (field_name
, field_shape
, _
) in enumerate(ao
.layout
):
281 if isinstance(field_shape
, Layout
):
285 if hasattr(val
, field_name
): # check for attribute
286 val
= getattr(val
, field_name
)
288 val
= val
[field_name
] # dictionary-style specification
289 rres
= eq(ao
.fields
[field_name
], val
)
291 elif isinstance(ao
, ArrayProxy
) and not isinstance(ai
, Value
):
293 op
= getattr(ao
, p
.name
)
294 #print (op, p, p.name)
296 if not isinstance(rres
, Sequence
):
301 if not isinstance(rres
, Sequence
):
307 class StageCls(metaclass
=ABCMeta
):
308 """ Class-based "Stage" API. requires instantiation (after derivation)
310 see "Stage API" above.. Note: python does *not* require derivation
311 from this class. All that is required is that the pipelines *have*
312 the functions listed in this class. Derivation from this class
313 is therefore merely a "courtesy" to maintainers.
316 def ispec(self
): pass # REQUIRED
318 def ospec(self
): pass # REQUIRED
320 #def setup(self, m, i): pass # OPTIONAL
322 def process(self
, i
): pass # REQUIRED
325 class Stage(metaclass
=ABCMeta
):
326 """ Static "Stage" API. does not require instantiation (after derivation)
328 see "Stage API" above. Note: python does *not* require derivation
329 from this class. All that is required is that the pipelines *have*
330 the functions listed in this class. Derivation from this class
331 is therefore merely a "courtesy" to maintainers.
343 #def setup(m, i): pass
350 class RecordBasedStage(Stage
):
351 """ convenience class which provides a Records-based layout.
352 honestly it's a lot easier just to create a direct Records-based
353 class (see ExampleAddRecordStage)
355 def __init__(self
, in_shape
, out_shape
, processfn
, setupfn
=None):
356 self
.in_shape
= in_shape
357 self
.out_shape
= out_shape
358 self
.__process
= processfn
359 self
.__setup
= setupfn
360 def ispec(self
): return Record(self
.in_shape
)
361 def ospec(self
): return Record(self
.out_shape
)
362 def process(seif
, i
): return self
.__process
(i
)
363 def setup(seif
, m
, i
): return self
.__setup
(m
, i
)
366 class StageChain(StageCls
):
367 """ pass in a list of stages, and they will automatically be
368 chained together via their input and output specs into a
371 the end result basically conforms to the exact same Stage API.
373 * input to this class will be the input of the first stage
374 * output of first stage goes into input of second
375 * output of second goes into input into third (etc. etc.)
376 * the output of this class will be the output of the last stage
378 def __init__(self
, chain
, specallocate
=False):
380 self
.specallocate
= specallocate
383 return self
.chain
[0].ispec()
386 return self
.chain
[-1].ospec()
388 def setup(self
, m
, i
):
389 for (idx
, c
) in enumerate(self
.chain
):
390 if hasattr(c
, "setup"):
391 c
.setup(m
, i
) # stage may have some module stuff
392 if self
.specallocate
:
393 o
= self
.chain
[idx
].ospec() # last assignment survives
394 m
.d
.comb
+= eq(o
, c
.process(i
)) # process input into "o"
396 o
= c
.process(i
) # store input into "o"
397 if idx
!= len(self
.chain
)-1:
398 if self
.specallocate
:
399 ni
= self
.chain
[idx
+1].ispec() # new input on next loop
400 m
.d
.comb
+= eq(ni
, o
) # assign to next input
404 self
.o
= o
# last loop is the output
406 def process(self
, i
):
407 return self
.o
# conform to Stage API: return last-loop output
411 """ Common functions for Pipeline API
413 def __init__(self
, in_multi
=None, stage_ctl
=False):
414 """ Base class containing ready/valid/data to previous and next stages
416 * p: contains ready/valid to the previous stage
417 * n: contains ready/valid to the next stage
419 Except when calling Controlbase.connect(), user must also:
420 * add i_data member to PrevControl (p) and
421 * add o_data member to NextControl (n)
423 # set up input and output IO ACK (prev/next ready/valid)
424 self
.p
= PrevControl(in_multi
, stage_ctl
)
425 self
.n
= NextControl(stage_ctl
)
427 def connect_to_next(self
, nxt
):
428 """ helper function to connect to the next stage data/valid/ready.
430 return self
.n
.connect_to_next(nxt
.p
)
432 def _connect_in(self
, prev
):
433 """ internal helper function to connect stage to an input source.
434 do not use to connect stage-to-stage!
436 return self
.p
._connect
_in
(prev
.p
)
438 def _connect_out(self
, nxt
):
439 """ internal helper function to connect stage to an output source.
440 do not use to connect stage-to-stage!
442 return self
.n
._connect
_out
(nxt
.n
)
444 def connect(self
, pipechain
):
445 """ connects a chain (list) of Pipeline instances together and
446 links them to this ControlBase instance:
448 in <----> self <---> out
451 [pipe1, pipe2, pipe3, pipe4]
454 out---in out--in out---in
456 Also takes care of allocating i_data/o_data, by looking up
457 the data spec for each end of the pipechain. i.e It is NOT
458 necessary to allocate self.p.i_data or self.n.o_data manually:
459 this is handled AUTOMATICALLY, here.
461 Basically this function is the direct equivalent of StageChain,
462 except that unlike StageChain, the Pipeline logic is followed.
464 Just as StageChain presents an object that conforms to the
465 Stage API from a list of objects that also conform to the
466 Stage API, an object that calls this Pipeline connect function
467 has the exact same pipeline API as the list of pipline objects
470 Thus it becomes possible to build up larger chains recursively.
471 More complex chains (multi-input, multi-output) will have to be
474 eqs
= [] # collated list of assignment statements
476 # connect inter-chain
477 for i
in range(len(pipechain
)-1):
479 pipe2
= pipechain
[i
+1]
480 eqs
+= pipe1
.connect_to_next(pipe2
)
482 # connect front of chain to ourselves
484 self
.p
.i_data
= front
.stage
.ispec()
485 eqs
+= front
._connect
_in
(self
)
487 # connect end of chain to ourselves
489 self
.n
.o_data
= end
.stage
.ospec()
490 eqs
+= end
._connect
_out
(self
)
494 def set_input(self
, i
):
495 """ helper function to set the input data
497 return eq(self
.p
.i_data
, i
)
500 res
= [self
.p
.i_valid
, self
.n
.i_ready
,
501 self
.n
.o_valid
, self
.p
.o_ready
,
503 if hasattr(self
.p
.i_data
, "ports"):
504 res
+= self
.p
.i_data
.ports()
507 if hasattr(self
.n
.o_data
, "ports"):
508 res
+= self
.n
.o_data
.ports()
514 class BufferedPipeline(ControlBase
):
515 """ buffered pipeline stage. data and strobe signals travel in sync.
516 if ever the input is ready and the output is not, processed data
517 is shunted in a temporary register.
519 Argument: stage. see Stage API above
521 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
522 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
523 stage-1 p.i_data >>in stage n.o_data out>> stage+1
529 input data p.i_data is read (only), is processed and goes into an
530 intermediate result store [process()]. this is updated combinatorially.
532 in a non-stall condition, the intermediate result will go into the
533 output (update_output). however if ever there is a stall, it goes
534 into r_data instead [update_buffer()].
536 when the non-stall condition is released, r_data is the first
537 to be transferred to the output [flush_buffer()], and the stall
540 on the next cycle (as long as stall is not raised again) the
541 input may begin to be processed and transferred directly to output.
544 def __init__(self
, stage
):
545 ControlBase
.__init
__(self
)
548 # set up the input and output data
549 self
.p
.i_data
= stage
.ispec() # input type
550 self
.n
.o_data
= stage
.ospec()
552 def elaborate(self
, platform
):
556 result
= self
.stage
.ospec()
557 r_data
= self
.stage
.ospec()
558 if hasattr(self
.stage
, "setup"):
559 self
.stage
.setup(self
.m
, self
.p
.i_data
)
561 # establish some combinatorial temporaries
562 o_n_validn
= Signal(reset_less
=True)
563 i_p_valid_o_p_ready
= Signal(reset_less
=True)
564 p_i_valid
= Signal(reset_less
=True)
565 self
.m
.d
.comb
+= [p_i_valid
.eq(self
.p
.i_valid_logic()),
566 o_n_validn
.eq(~self
.n
.o_valid
),
567 i_p_valid_o_p_ready
.eq(p_i_valid
& self
.p
.o_ready
),
570 # store result of processing in combinatorial temporary
571 self
.m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
573 # if not in stall condition, update the temporary register
574 with self
.m
.If(self
.p
.o_ready
): # not stalled
575 self
.m
.d
.sync
+= eq(r_data
, result
) # update buffer
577 with self
.m
.If(self
.n
.i_ready
): # next stage is ready
578 with self
.m
.If(self
.p
.o_ready
): # not stalled
579 # nothing in buffer: send (processed) input direct to output
580 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(p_i_valid
),
581 eq(self
.n
.o_data
, result
), # update output
583 with self
.m
.Else(): # p.o_ready is false, and something in buffer
584 # Flush the [already processed] buffer to the output port.
585 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(1), # declare reg empty
586 eq(self
.n
.o_data
, r_data
), # flush buffer
587 self
.p
.o_ready
.eq(1), # clear stall
589 # ignore input, since p.o_ready is also false.
591 # (n.i_ready) is false here: next stage is ready
592 with self
.m
.Elif(o_n_validn
): # next stage being told "ready"
593 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(p_i_valid
),
594 self
.p
.o_ready
.eq(1), # Keep the buffer empty
595 eq(self
.n
.o_data
, result
), # set output data
598 # (n.i_ready) false and (n.o_valid) true:
599 with self
.m
.Elif(i_p_valid_o_p_ready
):
600 # If next stage *is* ready, and not stalled yet, accept input
601 self
.m
.d
.sync
+= self
.p
.o_ready
.eq(~
(p_i_valid
& self
.n
.o_valid
))
606 class UnbufferedPipeline(ControlBase
):
607 """ A simple pipeline stage with single-clock synchronisation
608 and two-way valid/ready synchronised signalling.
610 Note that a stall in one stage will result in the entire pipeline
613 Also that unlike BufferedPipeline, the valid/ready signalling does NOT
614 travel synchronously with the data: the valid/ready signalling
615 combines in a *combinatorial* fashion. Therefore, a long pipeline
616 chain will lengthen propagation delays.
618 Argument: stage. see Stage API, above
620 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
621 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
622 stage-1 p.i_data >>in stage n.o_data out>> stage+1
630 p.i_data : StageInput, shaped according to ispec
632 p.o_data : StageOutput, shaped according to ospec
634 r_data : input_shape according to ispec
635 A temporary (buffered) copy of a prior (valid) input.
636 This is HELD if the output is not ready. It is updated
638 result: output_shape according to ospec
639 The output of the combinatorial logic. it is updated
640 COMBINATORIALLY (no clock dependence).
643 def __init__(self
, stage
):
644 ControlBase
.__init
__(self
)
647 # set up the input and output data
648 self
.p
.i_data
= stage
.ispec() # input type
649 self
.n
.o_data
= stage
.ospec() # output type
651 def elaborate(self
, platform
):
654 data_valid
= Signal() # is data valid or not
655 r_data
= self
.stage
.ispec() # input type
656 if hasattr(self
.stage
, "setup"):
657 self
.stage
.setup(self
.m
, r_data
)
660 p_i_valid
= Signal(reset_less
=True)
661 pv
= Signal(reset_less
=True)
662 self
.m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_logic())
663 self
.m
.d
.comb
+= pv
.eq(self
.p
.i_valid
& self
.p
.o_ready
)
665 self
.m
.d
.comb
+= self
.n
.o_valid
.eq(data_valid
)
666 self
.m
.d
.comb
+= self
.p
.o_ready
.eq(~data_valid | self
.n
.i_ready
)
667 self
.m
.d
.sync
+= data_valid
.eq(p_i_valid | \
668 (~self
.n
.i_ready
& data_valid
))
670 self
.m
.d
.sync
+= eq(r_data
, self
.p
.i_data
)
671 self
.m
.d
.comb
+= eq(self
.n
.o_data
, self
.stage
.process(r_data
))
675 class PassThroughStage(StageCls
):
676 """ a pass-through stage which has its input data spec equal to its output,
677 and "passes through" its data from input to output.
679 def __init__(self
, iospecfn
):
680 self
.iospecfn
= iospecfn
681 def ispec(self
): return self
.iospecfn()
682 def ospec(self
): return self
.iospecfn()
683 def process(self
, i
): return i
686 class RegisterPipeline(UnbufferedPipeline
):
687 """ A pipeline stage that delays by one clock cycle, creating a
688 sync'd latch out of o_data and o_valid as an indirect byproduct
689 of using PassThroughStage
691 def __init__(self
, iospecfn
):
692 UnbufferedPipeline
.__init
__(self
, PassThroughStage(iospecfn
))