f6c2070342b2d874b95b7710b4be006f7acd79ec
1 """ Pipeline and BufferedHandshake implementation, conforming to the same API.
2 For multi-input and multi-output variants, see multipipe.
7 a strategically very important function that is identical in function
8 to nmigen's Signal.eq function, except it may take objects, or a list
9 of objects, or a tuple of objects, and where objects may also be
15 stage requires compliance with a strict API that may be
16 implemented in several means, including as a static class.
17 the methods of a stage instance must be as follows:
19 * ispec() - Input data format specification
20 returns an object or a list or tuple of objects, or
21 a Record, each object having an "eq" function which
22 takes responsibility for copying by assignment all
24 * ospec() - Output data format specification
25 requirements as for ospec
26 * process(m, i) - Processes an ispec-formatted object
27 returns a combinatorial block of a result that
28 may be assigned to the output, by way of the "eq"
30 * setup(m, i) - Optional function for setting up submodules
31 may be used for more complex stages, to link
32 the input (i) to submodules. must take responsibility
33 for adding those submodules to the module (m).
34 the submodules must be combinatorial blocks and
35 must have their inputs and output linked combinatorially.
37 Both StageCls (for use with non-static classes) and Stage (for use
38 by static classes) are abstract classes from which, for convenience
39 and as a courtesy to other developers, anything conforming to the
40 Stage API may *choose* to derive.
45 A useful combinatorial wrapper around stages that chains them together
46 and then presents a Stage-API-conformant interface. By presenting
47 the same API as the stages it wraps, it can clearly be used recursively.
52 A convenience class that takes an input shape, output shape, a
53 "processing" function and an optional "setup" function. Honestly
54 though, there's not much more effort to just... create a class
55 that returns a couple of Records (see ExampleAddRecordStage in
61 A convenience class that takes a single function as a parameter,
62 that is chain-called to create the exact same input and output spec.
63 It has a process() function that simply returns its input.
65 Instances of this class are completely redundant if handed to
66 StageChain, however when passed to UnbufferedPipeline they
67 can be used to introduce a single clock delay.
72 The base class for pipelines. Contains previous and next ready/valid/data.
73 Also has an extremely useful "connect" function that can be used to
74 connect a chain of pipelines and present the exact same prev/next
80 A simple stalling clock-synchronised pipeline that has no buffering
81 (unlike BufferedHandshake). Data flows on *every* clock cycle when
82 the conditions are right (this is nominally when the input is valid
83 and the output is ready).
85 A stall anywhere along the line will result in a stall back-propagating
86 down the entire chain. The BufferedHandshake by contrast will buffer
87 incoming data, allowing previous stages one clock cycle's grace before
90 An advantage of the UnbufferedPipeline over the Buffered one is
91 that the amount of logic needed (number of gates) is greatly
92 reduced (no second set of buffers basically)
94 The disadvantage of the UnbufferedPipeline is that the valid/ready
95 logic, if chained together, is *combinatorial*, resulting in
96 progressively larger gate delay.
101 A Control class that introduces a single clock delay, passing its
102 data through unaltered. Unlike RegisterPipeline (which relies
103 on UnbufferedPipeline and PassThroughStage) it handles ready/valid
109 A convenience class that, because UnbufferedPipeline introduces a single
110 clock delay, when its stage is a PassThroughStage, it results in a Pipeline
111 stage that, duh, delays its (unmodified) input by one clock cycle.
116 nmigen implementation of buffered pipeline stage, based on zipcpu:
117 https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html
119 this module requires quite a bit of thought to understand how it works
120 (and why it is needed in the first place). reading the above is
121 *strongly* recommended.
123 unlike john dawson's IEEE754 FPU STB/ACK signalling, which requires
124 the STB / ACK signals to raise and lower (on separate clocks) before
125 data may proceeed (thus only allowing one piece of data to proceed
126 on *ALTERNATE* cycles), the signalling here is a true pipeline
127 where data will flow on *every* clock when the conditions are right.
129 input acceptance conditions are when:
130 * incoming previous-stage strobe (p.i_valid) is HIGH
131 * outgoing previous-stage ready (p.o_ready) is LOW
133 output transmission conditions are when:
134 * outgoing next-stage strobe (n.o_valid) is HIGH
135 * outgoing next-stage ready (n.i_ready) is LOW
137 the tricky bit is when the input has valid data and the output is not
138 ready to accept it. if it wasn't for the clock synchronisation, it
139 would be possible to tell the input "hey don't send that data, we're
140 not ready". unfortunately, it's not possible to "change the past":
141 the previous stage *has no choice* but to pass on its data.
143 therefore, the incoming data *must* be accepted - and stored: that
144 is the responsibility / contract that this stage *must* accept.
145 on the same clock, it's possible to tell the input that it must
146 not send any more data. this is the "stall" condition.
148 we now effectively have *two* possible pieces of data to "choose" from:
149 the buffered data, and the incoming data. the decision as to which
150 to process and output is based on whether we are in "stall" or not.
151 i.e. when the next stage is no longer ready, the output comes from
152 the buffer if a stall had previously occurred, otherwise it comes
153 direct from processing the input.
155 this allows us to respect a synchronous "travelling STB" with what
156 dan calls a "buffered handshake".
158 it's quite a complex state machine!
163 Synchronised pipeline, Based on:
164 https://github.com/ZipCPU/dbgbus/blob/master/hexbus/rtl/hbdeword.v
167 from nmigen
import Signal
, Cat
, Const
, Mux
, Module
, Value
168 from nmigen
.cli
import verilog
, rtlil
169 from nmigen
.hdl
.ast
import ArrayProxy
170 from nmigen
.hdl
.rec
import Record
, Layout
172 from abc
import ABCMeta
, abstractmethod
173 from collections
.abc
import Sequence
177 """ contains signals that come *from* the previous stage (both in and out)
178 * i_valid: previous stage indicating all incoming data is valid.
179 may be a multi-bit signal, where all bits are required
180 to be asserted to indicate "valid".
181 * o_ready: output to next stage indicating readiness to accept data
182 * i_data : an input - added by the user of this class
185 def __init__(self
, i_width
=1, stage_ctl
=False):
186 self
.stage_ctl
= stage_ctl
187 self
.i_valid
= Signal(i_width
, name
="p_i_valid") # prev >>in self
188 self
._o
_ready
= Signal(name
="p_o_ready") # prev <<out self
189 self
.i_data
= None # XXX MUST BE ADDED BY USER
191 self
.s_o_ready
= Signal(name
="p_s_o_rdy") # prev <<out self
195 """ public-facing API: indicates (externally) that stage is ready
198 return self
.s_o_ready
# set dynamically by stage
199 return self
._o
_ready
# return this when not under dynamic control
201 def _connect_in(self
, prev
):
202 """ internal helper function to connect stage to an input source.
203 do not use to connect stage-to-stage!
205 return [self
.i_valid
.eq(prev
.i_valid_test
),
206 prev
.o_ready
.eq(self
.o_ready
),
207 eq(self
.i_data
, prev
.i_data
),
211 def i_valid_test(self
):
212 vlen
= len(self
.i_valid
)
214 # multi-bit case: valid only when i_valid is all 1s
215 all1s
= Const(-1, (len(self
.i_valid
), False))
216 i_valid
= (self
.i_valid
== all1s
)
218 # single-bit i_valid case
219 i_valid
= self
.i_valid
221 # when stage indicates not ready, incoming data
222 # must "appear" to be not ready too
224 i_valid
= i_valid
& self
.s_o_ready
230 """ contains the signals that go *to* the next stage (both in and out)
231 * o_valid: output indicating to next stage that data is valid
232 * i_ready: input from next stage indicating that it can accept data
233 * o_data : an output - added by the user of this class
235 def __init__(self
, stage_ctl
=False):
236 self
.stage_ctl
= stage_ctl
237 self
.o_valid
= Signal(name
="n_o_valid") # self out>> next
238 self
.i_ready
= Signal(name
="n_i_ready") # self <<in next
239 self
.o_data
= None # XXX MUST BE ADDED BY USER
241 self
.d_valid
= Signal(reset
=1) # INTERNAL (data valid)
244 def i_ready_test(self
):
246 return self
.i_ready
& self
.d_valid
249 def connect_to_next(self
, nxt
):
250 """ helper function to connect to the next stage data/valid/ready.
251 data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
252 use this when connecting stage-to-stage
254 return [nxt
.i_valid
.eq(self
.o_valid
),
255 self
.i_ready
.eq(nxt
.o_ready
),
256 eq(nxt
.i_data
, self
.o_data
),
259 def _connect_out(self
, nxt
):
260 """ internal helper function to connect stage to an output source.
261 do not use to connect stage-to-stage!
263 return [nxt
.o_valid
.eq(self
.o_valid
),
264 self
.i_ready
.eq(nxt
.i_ready_test
),
265 eq(nxt
.o_data
, self
.o_data
),
270 """ makes signals equal: a helper routine which identifies if it is being
271 passed a list (or tuple) of objects, or signals, or Records, and calls
272 the objects' eq function.
274 complex objects (classes) can be used: they must follow the
275 convention of having an eq member function, which takes the
276 responsibility of further calling eq and returning a list of
279 Record is a special (unusual, recursive) case, where the input may be
280 specified as a dictionary (which may contain further dictionaries,
281 recursively), where the field names of the dictionary must match
282 the Record's field spec. Alternatively, an object with the same
283 member names as the Record may be assigned: it does not have to
286 ArrayProxy is also special-cased, it's a bit messy: whilst ArrayProxy
287 has an eq function, the object being assigned to it (e.g. a python
288 object) might not. despite the *input* having an eq function,
289 that doesn't help us, because it's the *ArrayProxy* that's being
290 assigned to. so.... we cheat. use the ports() function of the
291 python object, enumerate them, find out the list of Signals that way,
295 if isinstance(o
, dict):
296 for (k
, v
) in o
.items():
297 print ("d-eq", v
, i
[k
])
298 res
.append(v
.eq(i
[k
]))
301 if not isinstance(o
, Sequence
):
303 for (ao
, ai
) in zip(o
, i
):
304 #print ("eq", ao, ai)
305 if isinstance(ao
, Record
):
307 for idx
, (field_name
, field_shape
, _
) in enumerate(ao
.layout
):
308 if isinstance(field_shape
, Layout
):
312 if hasattr(val
, field_name
): # check for attribute
313 val
= getattr(val
, field_name
)
315 val
= val
[field_name
] # dictionary-style specification
316 rres
+= eq(ao
.fields
[field_name
], val
)
317 elif isinstance(ao
, ArrayProxy
) and not isinstance(ai
, Value
):
320 op
= getattr(ao
, p
.name
)
321 #print (op, p, p.name)
322 rres
.append(op
.eq(p
))
325 if not isinstance(rres
, Sequence
):
331 class StageCls(metaclass
=ABCMeta
):
332 """ Class-based "Stage" API. requires instantiation (after derivation)
334 see "Stage API" above.. Note: python does *not* require derivation
335 from this class. All that is required is that the pipelines *have*
336 the functions listed in this class. Derivation from this class
337 is therefore merely a "courtesy" to maintainers.
340 def ispec(self
): pass # REQUIRED
342 def ospec(self
): pass # REQUIRED
344 #def setup(self, m, i): pass # OPTIONAL
346 def process(self
, i
): pass # REQUIRED
349 class Stage(metaclass
=ABCMeta
):
350 """ Static "Stage" API. does not require instantiation (after derivation)
352 see "Stage API" above. Note: python does *not* require derivation
353 from this class. All that is required is that the pipelines *have*
354 the functions listed in this class. Derivation from this class
355 is therefore merely a "courtesy" to maintainers.
367 #def setup(m, i): pass
374 class RecordBasedStage(Stage
):
375 """ convenience class which provides a Records-based layout.
376 honestly it's a lot easier just to create a direct Records-based
377 class (see ExampleAddRecordStage)
379 def __init__(self
, in_shape
, out_shape
, processfn
, setupfn
=None):
380 self
.in_shape
= in_shape
381 self
.out_shape
= out_shape
382 self
.__process
= processfn
383 self
.__setup
= setupfn
384 def ispec(self
): return Record(self
.in_shape
)
385 def ospec(self
): return Record(self
.out_shape
)
386 def process(seif
, i
): return self
.__process
(i
)
387 def setup(seif
, m
, i
): return self
.__setup
(m
, i
)
390 class StageChain(StageCls
):
391 """ pass in a list of stages, and they will automatically be
392 chained together via their input and output specs into a
395 the end result basically conforms to the exact same Stage API.
397 * input to this class will be the input of the first stage
398 * output of first stage goes into input of second
399 * output of second goes into input into third (etc. etc.)
400 * the output of this class will be the output of the last stage
402 def __init__(self
, chain
, specallocate
=False):
404 self
.specallocate
= specallocate
407 return self
.chain
[0].ispec()
410 return self
.chain
[-1].ospec()
412 def _specallocate_setup(self
, m
, i
):
413 for (idx
, c
) in enumerate(self
.chain
):
414 if hasattr(c
, "setup"):
415 c
.setup(m
, i
) # stage may have some module stuff
416 o
= self
.chain
[idx
].ospec() # last assignment survives
417 m
.d
.comb
+= eq(o
, c
.process(i
)) # process input into "o"
418 if idx
== len(self
.chain
)-1:
420 i
= self
.chain
[idx
+1].ispec() # new input on next loop
421 m
.d
.comb
+= eq(i
, o
) # assign to next input
422 return o
# last loop is the output
424 def _noallocate_setup(self
, m
, i
):
425 for (idx
, c
) in enumerate(self
.chain
):
426 if hasattr(c
, "setup"):
427 c
.setup(m
, i
) # stage may have some module stuff
428 i
= o
= c
.process(i
) # store input into "o"
429 return o
# last loop is the output
431 def setup(self
, m
, i
):
432 if self
.specallocate
:
433 self
.o
= self
._specallocate
_setup
(m
, i
)
435 self
.o
= self
._noallocate
_setup
(m
, i
)
437 def process(self
, i
):
438 return self
.o
# conform to Stage API: return last-loop output
442 """ Common functions for Pipeline API
444 def __init__(self
, in_multi
=None, stage_ctl
=False):
445 """ Base class containing ready/valid/data to previous and next stages
447 * p: contains ready/valid to the previous stage
448 * n: contains ready/valid to the next stage
450 Except when calling Controlbase.connect(), user must also:
451 * add i_data member to PrevControl (p) and
452 * add o_data member to NextControl (n)
454 # set up input and output IO ACK (prev/next ready/valid)
455 self
.p
= PrevControl(in_multi
, stage_ctl
)
456 self
.n
= NextControl(stage_ctl
)
458 def connect_to_next(self
, nxt
):
459 """ helper function to connect to the next stage data/valid/ready.
461 return self
.n
.connect_to_next(nxt
.p
)
463 def _connect_in(self
, prev
):
464 """ internal helper function to connect stage to an input source.
465 do not use to connect stage-to-stage!
467 return self
.p
._connect
_in
(prev
.p
)
469 def _connect_out(self
, nxt
):
470 """ internal helper function to connect stage to an output source.
471 do not use to connect stage-to-stage!
473 return self
.n
._connect
_out
(nxt
.n
)
475 def connect(self
, pipechain
):
476 """ connects a chain (list) of Pipeline instances together and
477 links them to this ControlBase instance:
479 in <----> self <---> out
482 [pipe1, pipe2, pipe3, pipe4]
485 out---in out--in out---in
487 Also takes care of allocating i_data/o_data, by looking up
488 the data spec for each end of the pipechain. i.e It is NOT
489 necessary to allocate self.p.i_data or self.n.o_data manually:
490 this is handled AUTOMATICALLY, here.
492 Basically this function is the direct equivalent of StageChain,
493 except that unlike StageChain, the Pipeline logic is followed.
495 Just as StageChain presents an object that conforms to the
496 Stage API from a list of objects that also conform to the
497 Stage API, an object that calls this Pipeline connect function
498 has the exact same pipeline API as the list of pipline objects
501 Thus it becomes possible to build up larger chains recursively.
502 More complex chains (multi-input, multi-output) will have to be
505 eqs
= [] # collated list of assignment statements
507 # connect inter-chain
508 for i
in range(len(pipechain
)-1):
510 pipe2
= pipechain
[i
+1]
511 eqs
+= pipe1
.connect_to_next(pipe2
)
513 # connect front of chain to ourselves
515 self
.p
.i_data
= front
.stage
.ispec()
516 eqs
+= front
._connect
_in
(self
)
518 # connect end of chain to ourselves
520 self
.n
.o_data
= end
.stage
.ospec()
521 eqs
+= end
._connect
_out
(self
)
525 def set_input(self
, i
):
526 """ helper function to set the input data
528 return eq(self
.p
.i_data
, i
)
531 res
= [self
.p
.i_valid
, self
.n
.i_ready
,
532 self
.n
.o_valid
, self
.p
.o_ready
,
534 if hasattr(self
.p
.i_data
, "ports"):
535 res
+= self
.p
.i_data
.ports()
538 if hasattr(self
.n
.o_data
, "ports"):
539 res
+= self
.n
.o_data
.ports()
544 def _elaborate(self
, platform
):
545 """ handles case where stage has dynamic ready/valid functions
548 if not self
.p
.stage_ctl
:
551 # intercept the previous (outgoing) "ready", combine with stage ready
552 m
.d
.comb
+= self
.p
.s_o_ready
.eq(self
.p
._o
_ready
& self
.stage
.d_ready
)
554 # intercept the next (incoming) "ready" and combine it with data valid
555 sdv
= self
.stage
.d_valid(self
.n
.i_ready
)
556 m
.d
.comb
+= self
.n
.d_valid
.eq(self
.n
.i_ready
& sdv
)
561 class BufferedHandshake(ControlBase
):
562 """ buffered pipeline stage. data and strobe signals travel in sync.
563 if ever the input is ready and the output is not, processed data
564 is shunted in a temporary register.
566 Argument: stage. see Stage API above
568 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
569 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
570 stage-1 p.i_data >>in stage n.o_data out>> stage+1
576 input data p.i_data is read (only), is processed and goes into an
577 intermediate result store [process()]. this is updated combinatorially.
579 in a non-stall condition, the intermediate result will go into the
580 output (update_output). however if ever there is a stall, it goes
581 into r_data instead [update_buffer()].
583 when the non-stall condition is released, r_data is the first
584 to be transferred to the output [flush_buffer()], and the stall
587 on the next cycle (as long as stall is not raised again) the
588 input may begin to be processed and transferred directly to output.
591 def __init__(self
, stage
, stage_ctl
=False):
592 ControlBase
.__init
__(self
, stage_ctl
=stage_ctl
)
595 # set up the input and output data
596 self
.p
.i_data
= stage
.ispec() # input type
597 self
.n
.o_data
= stage
.ospec()
599 def elaborate(self
, platform
):
601 self
.m
= ControlBase
._elaborate
(self
, platform
)
603 result
= self
.stage
.ospec()
604 r_data
= self
.stage
.ospec()
605 if hasattr(self
.stage
, "setup"):
606 self
.stage
.setup(self
.m
, self
.p
.i_data
)
608 # establish some combinatorial temporaries
609 o_n_validn
= Signal(reset_less
=True)
610 n_i_ready
= Signal(reset_less
=True, name
="n_i_rdy_data")
611 i_p_valid_o_p_ready
= Signal(reset_less
=True)
612 p_i_valid
= Signal(reset_less
=True)
613 self
.m
.d
.comb
+= [p_i_valid
.eq(self
.p
.i_valid_test
),
614 o_n_validn
.eq(~self
.n
.o_valid
),
615 i_p_valid_o_p_ready
.eq(p_i_valid
& self
.p
.o_ready
),
616 n_i_ready
.eq(self
.n
.i_ready_test
),
619 # store result of processing in combinatorial temporary
620 self
.m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
622 # if not in stall condition, update the temporary register
623 with self
.m
.If(self
.p
.o_ready
): # not stalled
624 self
.m
.d
.sync
+= eq(r_data
, result
) # update buffer
626 with self
.m
.If(n_i_ready
): # next stage is ready
627 with self
.m
.If(self
.p
._o
_ready
): # not stalled
628 # nothing in buffer: send (processed) input direct to output
629 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(p_i_valid
),
630 eq(self
.n
.o_data
, result
), # update output
632 with self
.m
.Else(): # p.o_ready is false, and data in buffer
633 # Flush the [already processed] buffer to the output port.
634 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(1), # reg empty
635 eq(self
.n
.o_data
, r_data
), # flush buffer
636 self
.p
._o
_ready
.eq(1), # clear stall
638 # ignore input, since p.o_ready is also false.
640 # (n.i_ready) is false here: next stage is ready
641 with self
.m
.Elif(o_n_validn
): # next stage being told "ready"
642 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(p_i_valid
),
643 self
.p
._o
_ready
.eq(1), # Keep the buffer empty
644 eq(self
.n
.o_data
, result
), # set output data
647 # (n.i_ready) false and (n.o_valid) true:
648 with self
.m
.Elif(i_p_valid_o_p_ready
):
649 # If next stage *is* ready, and not stalled yet, accept input
650 self
.m
.d
.sync
+= self
.p
._o
_ready
.eq(~
(p_i_valid
& self
.n
.o_valid
))
655 class SimpleHandshake(ControlBase
):
656 """ simple handshake control. data and strobe signals travel in sync.
657 implements the protocol used by Wishbone and AXI4.
659 Argument: stage. see Stage API above
661 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
662 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
663 stage-1 p.i_data >>in stage n.o_data out>> stage+1
667 def __init__(self
, stage
, stage_ctl
=False):
668 ControlBase
.__init
__(self
, stage_ctl
=stage_ctl
)
671 # set up the input and output data
672 self
.p
.i_data
= stage
.ispec() # input type
673 self
.n
.o_data
= stage
.ospec()
675 def elaborate(self
, platform
):
677 self
.m
= ControlBase
._elaborate
(self
, platform
)
680 result
= self
.stage
.ospec()
681 if hasattr(self
.stage
, "setup"):
682 self
.stage
.setup(self
.m
, self
.p
.i_data
)
684 # establish some combinatorial temporaries
685 n_i_ready
= Signal(reset_less
=True, name
="n_i_rdy_data")
686 p_i_valid_p_o_ready
= Signal(reset_less
=True)
687 p_i_valid
= Signal(reset_less
=True)
688 self
.m
.d
.comb
+= [p_i_valid
.eq(self
.p
.i_valid_test
),
689 n_i_ready
.eq(self
.n
.i_ready_test
),
690 p_i_valid_p_o_ready
.eq(p_i_valid
& self
.p
.o_ready
),
693 # store result of processing in combinatorial temporary
694 self
.m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
696 # previous valid and ready
697 with self
.m
.If(p_i_valid_p_o_ready
):
698 self
.m
.d
.sync
+= [r_busy
.eq(1), # output valid
699 #self.n.o_valid.eq(1), # output valid
700 eq(self
.n
.o_data
, result
), # update output
702 # previous invalid or not ready, however next is accepting
703 with self
.m
.Elif(n_i_ready
):
704 self
.m
.d
.sync
+= [ eq(self
.n
.o_data
, result
)]
705 # TODO: could still send data here (if there was any)
706 #self.m.d.sync += self.n.o_valid.eq(0) # ...so set output invalid
707 self
.m
.d
.sync
+= r_busy
.eq(0) # ...so set output invalid
709 self
.m
.d
.comb
+= self
.n
.o_valid
.eq(r_busy
)
710 # if next is ready, so is previous
711 self
.m
.d
.comb
+= self
.p
._o
_ready
.eq(n_i_ready
)
716 class UnbufferedPipeline(ControlBase
):
717 """ A simple pipeline stage with single-clock synchronisation
718 and two-way valid/ready synchronised signalling.
720 Note that a stall in one stage will result in the entire pipeline
723 Also that unlike BufferedHandshake, the valid/ready signalling does NOT
724 travel synchronously with the data: the valid/ready signalling
725 combines in a *combinatorial* fashion. Therefore, a long pipeline
726 chain will lengthen propagation delays.
728 Argument: stage. see Stage API, above
730 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
731 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
732 stage-1 p.i_data >>in stage n.o_data out>> stage+1
740 p.i_data : StageInput, shaped according to ispec
742 p.o_data : StageOutput, shaped according to ospec
744 r_data : input_shape according to ispec
745 A temporary (buffered) copy of a prior (valid) input.
746 This is HELD if the output is not ready. It is updated
748 result: output_shape according to ospec
749 The output of the combinatorial logic. it is updated
750 COMBINATORIALLY (no clock dependence).
753 def __init__(self
, stage
, stage_ctl
=False):
754 ControlBase
.__init
__(self
, stage_ctl
=stage_ctl
)
757 # set up the input and output data
758 self
.p
.i_data
= stage
.ispec() # input type
759 self
.n
.o_data
= stage
.ospec() # output type
761 def elaborate(self
, platform
):
762 self
.m
= ControlBase
._elaborate
(self
, platform
)
764 data_valid
= Signal() # is data valid or not
765 r_data
= self
.stage
.ispec() # input type
766 if hasattr(self
.stage
, "setup"):
767 self
.stage
.setup(self
.m
, r_data
)
770 p_i_valid
= Signal(reset_less
=True)
771 pv
= Signal(reset_less
=True)
772 self
.m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
773 self
.m
.d
.comb
+= pv
.eq(self
.p
.i_valid
& self
.p
.o_ready
)
775 self
.m
.d
.comb
+= self
.n
.o_valid
.eq(data_valid
)
776 self
.m
.d
.comb
+= self
.p
._o
_ready
.eq(~data_valid | self
.n
.i_ready_test
)
777 self
.m
.d
.sync
+= data_valid
.eq(p_i_valid | \
778 (~self
.n
.i_ready_test
& data_valid
))
780 self
.m
.d
.sync
+= eq(r_data
, self
.p
.i_data
)
781 self
.m
.d
.comb
+= eq(self
.n
.o_data
, self
.stage
.process(r_data
))
785 class UnbufferedPipeline2(ControlBase
):
786 """ A simple pipeline stage with single-clock synchronisation
787 and two-way valid/ready synchronised signalling.
789 Note that a stall in one stage will result in the entire pipeline
792 Also that unlike BufferedHandshake, the valid/ready signalling does NOT
793 travel synchronously with the data: the valid/ready signalling
794 combines in a *combinatorial* fashion. Therefore, a long pipeline
795 chain will lengthen propagation delays.
797 Argument: stage. see Stage API, above
799 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
800 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
801 stage-1 p.i_data >>in stage n.o_data out>> stage+1
809 p.i_data : StageInput, shaped according to ispec
811 p.o_data : StageOutput, shaped according to ospec
813 buf : output_shape according to ospec
814 A temporary (buffered) copy of a valid output
815 This is HELD if the output is not ready. It is updated
819 def __init__(self
, stage
, stage_ctl
=False):
820 ControlBase
.__init
__(self
, stage_ctl
=stage_ctl
)
823 # set up the input and output data
824 self
.p
.i_data
= stage
.ispec() # input type
825 self
.n
.o_data
= stage
.ospec() # output type
827 def elaborate(self
, platform
):
828 self
.m
= ControlBase
._elaborate
(self
, platform
)
830 buf_full
= Signal() # is data valid or not
831 buf
= self
.stage
.ospec() # output type
832 if hasattr(self
.stage
, "setup"):
833 self
.stage
.setup(self
.m
, self
.p
.i_data
)
836 p_i_valid
= Signal(reset_less
=True)
837 self
.m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
839 self
.m
.d
.comb
+= self
.n
.o_valid
.eq(buf_full | p_i_valid
)
840 self
.m
.d
.comb
+= self
.p
._o
_ready
.eq(~buf_full
)
841 self
.m
.d
.sync
+= buf_full
.eq(~self
.n
.i_ready_test
& self
.n
.o_valid
)
843 odata
= Mux(buf_full
, buf
, self
.stage
.process(self
.p
.i_data
))
844 self
.m
.d
.comb
+= eq(self
.n
.o_data
, odata
)
845 self
.m
.d
.sync
+= eq(buf
, self
.n
.o_data
)
850 class PassThroughStage(StageCls
):
851 """ a pass-through stage which has its input data spec equal to its output,
852 and "passes through" its data from input to output.
854 def __init__(self
, iospecfn
):
855 self
.iospecfn
= iospecfn
856 def ispec(self
): return self
.iospecfn()
857 def ospec(self
): return self
.iospecfn()
858 def process(self
, i
): return i
861 class PassThroughHandshake(ControlBase
):
862 """ A control block that delays by one clock cycle.
864 def __init__(self
, stage
, stage_ctl
=False):
865 ControlBase
.__init
__(self
, stage_ctl
=stage_ctl
)
868 # set up the input and output data
869 self
.p
.i_data
= stage
.ispec() # input type
870 self
.n
.o_data
= stage
.ospec() # output type
872 def elaborate(self
, platform
):
873 m
= ControlBase
._elaborate
(self
, platform
)
876 p_i_valid
= Signal(reset_less
=True)
877 pvr
= Signal(reset_less
=True)
878 m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
879 m
.d
.comb
+= pvr
.eq(p_i_valid
& self
.p
.o_ready
)
881 m
.d
.comb
+= self
.p
.o_ready
.eq(~self
.n
.o_valid | self
.n
.i_ready_test
)
882 m
.d
.sync
+= self
.n
.o_valid
.eq(p_i_valid | ~self
.p
.o_ready
)
884 odata
= Mux(pvr
, self
.stage
.process(self
.p
.i_data
), self
.n
.o_data
)
885 m
.d
.sync
+= eq(self
.n
.o_data
, odata
)
891 class RegisterPipeline(UnbufferedPipeline
):
892 """ A pipeline stage that delays by one clock cycle, creating a
893 sync'd latch out of o_data and o_valid as an indirect byproduct
894 of using PassThroughStage
896 def __init__(self
, iospecfn
):
897 UnbufferedPipeline
.__init
__(self
, PassThroughStage(iospecfn
))