1 """ Pipeline and BufferedHandshake implementation, conforming to the same API.
2 For multi-input and multi-output variants, see multipipe.
7 a strategically very important function that is identical in function
8 to nmigen's Signal.eq function, except it may take objects, or a list
9 of objects, or a tuple of objects, and where objects may also be
15 stage requires compliance with a strict API that may be
16 implemented in several means, including as a static class.
17 the methods of a stage instance must be as follows:
19 * ispec() - Input data format specification
20 returns an object or a list or tuple of objects, or
21 a Record, each object having an "eq" function which
22 takes responsibility for copying by assignment all
24 * ospec() - Output data format specification
25 requirements as for ospec
26 * process(m, i) - Processes an ispec-formatted object
27 returns a combinatorial block of a result that
28 may be assigned to the output, by way of the "eq"
30 * setup(m, i) - Optional function for setting up submodules
31 may be used for more complex stages, to link
32 the input (i) to submodules. must take responsibility
33 for adding those submodules to the module (m).
34 the submodules must be combinatorial blocks and
35 must have their inputs and output linked combinatorially.
37 Both StageCls (for use with non-static classes) and Stage (for use
38 by static classes) are abstract classes from which, for convenience
39 and as a courtesy to other developers, anything conforming to the
40 Stage API may *choose* to derive.
45 A useful combinatorial wrapper around stages that chains them together
46 and then presents a Stage-API-conformant interface. By presenting
47 the same API as the stages it wraps, it can clearly be used recursively.
52 A convenience class that takes an input shape, output shape, a
53 "processing" function and an optional "setup" function. Honestly
54 though, there's not much more effort to just... create a class
55 that returns a couple of Records (see ExampleAddRecordStage in
61 A convenience class that takes a single function as a parameter,
62 that is chain-called to create the exact same input and output spec.
63 It has a process() function that simply returns its input.
65 Instances of this class are completely redundant if handed to
66 StageChain, however when passed to UnbufferedPipeline they
67 can be used to introduce a single clock delay.
72 The base class for pipelines. Contains previous and next ready/valid/data.
73 Also has an extremely useful "connect" function that can be used to
74 connect a chain of pipelines and present the exact same prev/next
80 A simple stalling clock-synchronised pipeline that has no buffering
81 (unlike BufferedHandshake). Data flows on *every* clock cycle when
82 the conditions are right (this is nominally when the input is valid
83 and the output is ready).
85 A stall anywhere along the line will result in a stall back-propagating
86 down the entire chain. The BufferedHandshake by contrast will buffer
87 incoming data, allowing previous stages one clock cycle's grace before
90 An advantage of the UnbufferedPipeline over the Buffered one is
91 that the amount of logic needed (number of gates) is greatly
92 reduced (no second set of buffers basically)
94 The disadvantage of the UnbufferedPipeline is that the valid/ready
95 logic, if chained together, is *combinatorial*, resulting in
96 progressively larger gate delay.
101 A Control class that introduces a single clock delay, passing its
102 data through unaltered. Unlike RegisterPipeline (which relies
103 on UnbufferedPipeline and PassThroughStage) it handles ready/valid
109 A convenience class that, because UnbufferedPipeline introduces a single
110 clock delay, when its stage is a PassThroughStage, it results in a Pipeline
111 stage that, duh, delays its (unmodified) input by one clock cycle.
116 nmigen implementation of buffered pipeline stage, based on zipcpu:
117 https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html
119 this module requires quite a bit of thought to understand how it works
120 (and why it is needed in the first place). reading the above is
121 *strongly* recommended.
123 unlike john dawson's IEEE754 FPU STB/ACK signalling, which requires
124 the STB / ACK signals to raise and lower (on separate clocks) before
125 data may proceeed (thus only allowing one piece of data to proceed
126 on *ALTERNATE* cycles), the signalling here is a true pipeline
127 where data will flow on *every* clock when the conditions are right.
129 input acceptance conditions are when:
130 * incoming previous-stage strobe (p.i_valid) is HIGH
131 * outgoing previous-stage ready (p.o_ready) is LOW
133 output transmission conditions are when:
134 * outgoing next-stage strobe (n.o_valid) is HIGH
135 * outgoing next-stage ready (n.i_ready) is LOW
137 the tricky bit is when the input has valid data and the output is not
138 ready to accept it. if it wasn't for the clock synchronisation, it
139 would be possible to tell the input "hey don't send that data, we're
140 not ready". unfortunately, it's not possible to "change the past":
141 the previous stage *has no choice* but to pass on its data.
143 therefore, the incoming data *must* be accepted - and stored: that
144 is the responsibility / contract that this stage *must* accept.
145 on the same clock, it's possible to tell the input that it must
146 not send any more data. this is the "stall" condition.
148 we now effectively have *two* possible pieces of data to "choose" from:
149 the buffered data, and the incoming data. the decision as to which
150 to process and output is based on whether we are in "stall" or not.
151 i.e. when the next stage is no longer ready, the output comes from
152 the buffer if a stall had previously occurred, otherwise it comes
153 direct from processing the input.
155 this allows us to respect a synchronous "travelling STB" with what
156 dan calls a "buffered handshake".
158 it's quite a complex state machine!
163 Synchronised pipeline, Based on:
164 https://github.com/ZipCPU/dbgbus/blob/master/hexbus/rtl/hbdeword.v
167 from nmigen
import Signal
, Cat
, Const
, Mux
, Module
, Value
168 from nmigen
.cli
import verilog
, rtlil
169 from nmigen
.lib
.fifo
import SyncFIFO
170 from nmigen
.hdl
.ast
import ArrayProxy
171 from nmigen
.hdl
.rec
import Record
, Layout
173 from abc
import ABCMeta
, abstractmethod
174 from collections
.abc
import Sequence
178 """ contains signals that come *from* the previous stage (both in and out)
179 * i_valid: previous stage indicating all incoming data is valid.
180 may be a multi-bit signal, where all bits are required
181 to be asserted to indicate "valid".
182 * o_ready: output to next stage indicating readiness to accept data
183 * i_data : an input - added by the user of this class
186 def __init__(self
, i_width
=1, stage_ctl
=False):
187 self
.stage_ctl
= stage_ctl
188 self
.i_valid
= Signal(i_width
, name
="p_i_valid") # prev >>in self
189 self
._o
_ready
= Signal(name
="p_o_ready") # prev <<out self
190 self
.i_data
= None # XXX MUST BE ADDED BY USER
192 self
.s_o_ready
= Signal(name
="p_s_o_rdy") # prev <<out self
196 """ public-facing API: indicates (externally) that stage is ready
199 return self
.s_o_ready
# set dynamically by stage
200 return self
._o
_ready
# return this when not under dynamic control
202 def _connect_in(self
, prev
):
203 """ internal helper function to connect stage to an input source.
204 do not use to connect stage-to-stage!
206 return [self
.i_valid
.eq(prev
.i_valid_test
),
207 prev
.o_ready
.eq(self
.o_ready
),
208 eq(self
.i_data
, prev
.i_data
),
212 def i_valid_test(self
):
213 vlen
= len(self
.i_valid
)
215 # multi-bit case: valid only when i_valid is all 1s
216 all1s
= Const(-1, (len(self
.i_valid
), False))
217 i_valid
= (self
.i_valid
== all1s
)
219 # single-bit i_valid case
220 i_valid
= self
.i_valid
222 # when stage indicates not ready, incoming data
223 # must "appear" to be not ready too
225 i_valid
= i_valid
& self
.s_o_ready
231 """ contains the signals that go *to* the next stage (both in and out)
232 * o_valid: output indicating to next stage that data is valid
233 * i_ready: input from next stage indicating that it can accept data
234 * o_data : an output - added by the user of this class
236 def __init__(self
, stage_ctl
=False):
237 self
.stage_ctl
= stage_ctl
238 self
.o_valid
= Signal(name
="n_o_valid") # self out>> next
239 self
.i_ready
= Signal(name
="n_i_ready") # self <<in next
240 self
.o_data
= None # XXX MUST BE ADDED BY USER
242 self
.d_valid
= Signal(reset
=1) # INTERNAL (data valid)
245 def i_ready_test(self
):
247 return self
.i_ready
& self
.d_valid
250 def connect_to_next(self
, nxt
):
251 """ helper function to connect to the next stage data/valid/ready.
252 data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
253 use this when connecting stage-to-stage
255 return [nxt
.i_valid
.eq(self
.o_valid
),
256 self
.i_ready
.eq(nxt
.o_ready
),
257 eq(nxt
.i_data
, self
.o_data
),
260 def _connect_out(self
, nxt
):
261 """ internal helper function to connect stage to an output source.
262 do not use to connect stage-to-stage!
264 return [nxt
.o_valid
.eq(self
.o_valid
),
265 self
.i_ready
.eq(nxt
.i_ready_test
),
266 eq(nxt
.o_data
, self
.o_data
),
271 """ makes signals equal: a helper routine which identifies if it is being
272 passed a list (or tuple) of objects, or signals, or Records, and calls
273 the objects' eq function.
275 complex objects (classes) can be used: they must follow the
276 convention of having an eq member function, which takes the
277 responsibility of further calling eq and returning a list of
280 Record is a special (unusual, recursive) case, where the input may be
281 specified as a dictionary (which may contain further dictionaries,
282 recursively), where the field names of the dictionary must match
283 the Record's field spec. Alternatively, an object with the same
284 member names as the Record may be assigned: it does not have to
287 ArrayProxy is also special-cased, it's a bit messy: whilst ArrayProxy
288 has an eq function, the object being assigned to it (e.g. a python
289 object) might not. despite the *input* having an eq function,
290 that doesn't help us, because it's the *ArrayProxy* that's being
291 assigned to. so.... we cheat. use the ports() function of the
292 python object, enumerate them, find out the list of Signals that way,
296 if isinstance(o
, dict):
297 for (k
, v
) in o
.items():
298 print ("d-eq", v
, i
[k
])
299 res
.append(v
.eq(i
[k
]))
302 if not isinstance(o
, Sequence
):
304 for (ao
, ai
) in zip(o
, i
):
305 #print ("eq", ao, ai)
306 if isinstance(ao
, Record
):
308 for idx
, (field_name
, field_shape
, _
) in enumerate(ao
.layout
):
309 if isinstance(field_shape
, Layout
):
313 if hasattr(val
, field_name
): # check for attribute
314 val
= getattr(val
, field_name
)
316 val
= val
[field_name
] # dictionary-style specification
317 rres
+= eq(ao
.fields
[field_name
], val
)
318 elif isinstance(ao
, ArrayProxy
) and not isinstance(ai
, Value
):
321 op
= getattr(ao
, p
.name
)
322 #print (op, p, p.name)
323 rres
.append(op
.eq(p
))
326 if not isinstance(rres
, Sequence
):
332 class StageCls(metaclass
=ABCMeta
):
333 """ Class-based "Stage" API. requires instantiation (after derivation)
335 see "Stage API" above.. Note: python does *not* require derivation
336 from this class. All that is required is that the pipelines *have*
337 the functions listed in this class. Derivation from this class
338 is therefore merely a "courtesy" to maintainers.
341 def ispec(self
): pass # REQUIRED
343 def ospec(self
): pass # REQUIRED
345 #def setup(self, m, i): pass # OPTIONAL
347 def process(self
, i
): pass # REQUIRED
350 class Stage(metaclass
=ABCMeta
):
351 """ Static "Stage" API. does not require instantiation (after derivation)
353 see "Stage API" above. Note: python does *not* require derivation
354 from this class. All that is required is that the pipelines *have*
355 the functions listed in this class. Derivation from this class
356 is therefore merely a "courtesy" to maintainers.
368 #def setup(m, i): pass
375 class RecordBasedStage(Stage
):
376 """ convenience class which provides a Records-based layout.
377 honestly it's a lot easier just to create a direct Records-based
378 class (see ExampleAddRecordStage)
380 def __init__(self
, in_shape
, out_shape
, processfn
, setupfn
=None):
381 self
.in_shape
= in_shape
382 self
.out_shape
= out_shape
383 self
.__process
= processfn
384 self
.__setup
= setupfn
385 def ispec(self
): return Record(self
.in_shape
)
386 def ospec(self
): return Record(self
.out_shape
)
387 def process(seif
, i
): return self
.__process
(i
)
388 def setup(seif
, m
, i
): return self
.__setup
(m
, i
)
391 class StageChain(StageCls
):
392 """ pass in a list of stages, and they will automatically be
393 chained together via their input and output specs into a
396 the end result basically conforms to the exact same Stage API.
398 * input to this class will be the input of the first stage
399 * output of first stage goes into input of second
400 * output of second goes into input into third (etc. etc.)
401 * the output of this class will be the output of the last stage
403 def __init__(self
, chain
, specallocate
=False):
405 self
.specallocate
= specallocate
408 return self
.chain
[0].ispec()
411 return self
.chain
[-1].ospec()
413 def _specallocate_setup(self
, m
, i
):
414 for (idx
, c
) in enumerate(self
.chain
):
415 if hasattr(c
, "setup"):
416 c
.setup(m
, i
) # stage may have some module stuff
417 o
= self
.chain
[idx
].ospec() # last assignment survives
418 m
.d
.comb
+= eq(o
, c
.process(i
)) # process input into "o"
419 if idx
== len(self
.chain
)-1:
421 i
= self
.chain
[idx
+1].ispec() # new input on next loop
422 m
.d
.comb
+= eq(i
, o
) # assign to next input
423 return o
# last loop is the output
425 def _noallocate_setup(self
, m
, i
):
426 for (idx
, c
) in enumerate(self
.chain
):
427 if hasattr(c
, "setup"):
428 c
.setup(m
, i
) # stage may have some module stuff
429 i
= o
= c
.process(i
) # store input into "o"
430 return o
# last loop is the output
432 def setup(self
, m
, i
):
433 if self
.specallocate
:
434 self
.o
= self
._specallocate
_setup
(m
, i
)
436 self
.o
= self
._noallocate
_setup
(m
, i
)
438 def process(self
, i
):
439 return self
.o
# conform to Stage API: return last-loop output
443 """ Common functions for Pipeline API
445 def __init__(self
, stage
=None, in_multi
=None, stage_ctl
=False):
446 """ Base class containing ready/valid/data to previous and next stages
448 * p: contains ready/valid to the previous stage
449 * n: contains ready/valid to the next stage
451 Except when calling Controlbase.connect(), user must also:
452 * add i_data member to PrevControl (p) and
453 * add o_data member to NextControl (n)
457 # set up input and output IO ACK (prev/next ready/valid)
458 self
.p
= PrevControl(in_multi
, stage_ctl
)
459 self
.n
= NextControl(stage_ctl
)
461 # set up the input and output data
462 if stage
is not None:
463 self
.p
.i_data
= stage
.ispec() # input type
464 self
.n
.o_data
= stage
.ospec()
466 def connect_to_next(self
, nxt
):
467 """ helper function to connect to the next stage data/valid/ready.
469 return self
.n
.connect_to_next(nxt
.p
)
471 def _connect_in(self
, prev
):
472 """ internal helper function to connect stage to an input source.
473 do not use to connect stage-to-stage!
475 return self
.p
._connect
_in
(prev
.p
)
477 def _connect_out(self
, nxt
):
478 """ internal helper function to connect stage to an output source.
479 do not use to connect stage-to-stage!
481 return self
.n
._connect
_out
(nxt
.n
)
483 def connect(self
, pipechain
):
484 """ connects a chain (list) of Pipeline instances together and
485 links them to this ControlBase instance:
487 in <----> self <---> out
490 [pipe1, pipe2, pipe3, pipe4]
493 out---in out--in out---in
495 Also takes care of allocating i_data/o_data, by looking up
496 the data spec for each end of the pipechain. i.e It is NOT
497 necessary to allocate self.p.i_data or self.n.o_data manually:
498 this is handled AUTOMATICALLY, here.
500 Basically this function is the direct equivalent of StageChain,
501 except that unlike StageChain, the Pipeline logic is followed.
503 Just as StageChain presents an object that conforms to the
504 Stage API from a list of objects that also conform to the
505 Stage API, an object that calls this Pipeline connect function
506 has the exact same pipeline API as the list of pipline objects
509 Thus it becomes possible to build up larger chains recursively.
510 More complex chains (multi-input, multi-output) will have to be
513 eqs
= [] # collated list of assignment statements
515 # connect inter-chain
516 for i
in range(len(pipechain
)-1):
518 pipe2
= pipechain
[i
+1]
519 eqs
+= pipe1
.connect_to_next(pipe2
)
521 # connect front of chain to ourselves
523 self
.p
.i_data
= front
.stage
.ispec()
524 eqs
+= front
._connect
_in
(self
)
526 # connect end of chain to ourselves
528 self
.n
.o_data
= end
.stage
.ospec()
529 eqs
+= end
._connect
_out
(self
)
533 def set_input(self
, i
):
534 """ helper function to set the input data
536 return eq(self
.p
.i_data
, i
)
539 res
= [self
.p
.i_valid
, self
.n
.i_ready
,
540 self
.n
.o_valid
, self
.p
.o_ready
,
542 if hasattr(self
.p
.i_data
, "ports"):
543 res
+= self
.p
.i_data
.ports()
546 if hasattr(self
.n
.o_data
, "ports"):
547 res
+= self
.n
.o_data
.ports()
552 def _elaborate(self
, platform
):
553 """ handles case where stage has dynamic ready/valid functions
557 if self
.stage
is not None and hasattr(self
.stage
, "setup"):
558 self
.stage
.setup(m
, self
.p
.i_data
)
560 if not self
.p
.stage_ctl
:
563 # intercept the previous (outgoing) "ready", combine with stage ready
564 m
.d
.comb
+= self
.p
.s_o_ready
.eq(self
.p
._o
_ready
& self
.stage
.d_ready
)
566 # intercept the next (incoming) "ready" and combine it with data valid
567 sdv
= self
.stage
.d_valid(self
.n
.i_ready
)
568 m
.d
.comb
+= self
.n
.d_valid
.eq(self
.n
.i_ready
& sdv
)
573 class BufferedHandshake(ControlBase
):
574 """ buffered pipeline stage. data and strobe signals travel in sync.
575 if ever the input is ready and the output is not, processed data
576 is shunted in a temporary register.
578 Argument: stage. see Stage API above
580 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
581 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
582 stage-1 p.i_data >>in stage n.o_data out>> stage+1
588 input data p.i_data is read (only), is processed and goes into an
589 intermediate result store [process()]. this is updated combinatorially.
591 in a non-stall condition, the intermediate result will go into the
592 output (update_output). however if ever there is a stall, it goes
593 into r_data instead [update_buffer()].
595 when the non-stall condition is released, r_data is the first
596 to be transferred to the output [flush_buffer()], and the stall
599 on the next cycle (as long as stall is not raised again) the
600 input may begin to be processed and transferred directly to output.
603 def elaborate(self
, platform
):
604 self
.m
= ControlBase
._elaborate
(self
, platform
)
606 result
= self
.stage
.ospec()
607 r_data
= self
.stage
.ospec()
609 # establish some combinatorial temporaries
610 o_n_validn
= Signal(reset_less
=True)
611 n_i_ready
= Signal(reset_less
=True, name
="n_i_rdy_data")
612 nir_por
= Signal(reset_less
=True)
613 nir_por_n
= Signal(reset_less
=True)
614 p_i_valid
= Signal(reset_less
=True)
615 nir_novn
= Signal(reset_less
=True)
616 nirn_novn
= Signal(reset_less
=True)
617 por_pivn
= Signal(reset_less
=True)
618 npnn
= Signal(reset_less
=True)
619 self
.m
.d
.comb
+= [p_i_valid
.eq(self
.p
.i_valid_test
),
620 o_n_validn
.eq(~self
.n
.o_valid
),
621 n_i_ready
.eq(self
.n
.i_ready_test
),
622 nir_por
.eq(n_i_ready
& self
.p
._o
_ready
),
623 nir_por_n
.eq(n_i_ready
& ~self
.p
._o
_ready
),
624 nir_novn
.eq(n_i_ready | o_n_validn
),
625 nirn_novn
.eq(~n_i_ready
& o_n_validn
),
626 npnn
.eq(nir_por | nirn_novn
),
627 por_pivn
.eq(self
.p
._o
_ready
& ~p_i_valid
)
630 # store result of processing in combinatorial temporary
631 self
.m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
633 # if not in stall condition, update the temporary register
634 with self
.m
.If(self
.p
.o_ready
): # not stalled
635 self
.m
.d
.sync
+= eq(r_data
, result
) # update buffer
637 # data pass-through conditions
638 with self
.m
.If(npnn
):
639 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(p_i_valid
), # valid if p_valid
640 eq(self
.n
.o_data
, result
), # update output
642 # buffer flush conditions (NOTE: can override data passthru conditions)
643 with self
.m
.If(nir_por_n
): # not stalled
644 # Flush the [already processed] buffer to the output port.
645 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(1), # reg empty
646 eq(self
.n
.o_data
, r_data
), # flush buffer
648 # output ready conditions
649 self
.m
.d
.sync
+= self
.p
._o
_ready
.eq(nir_novn | por_pivn
)
654 class SimpleHandshake(ControlBase
):
655 """ simple handshake control. data and strobe signals travel in sync.
656 implements the protocol used by Wishbone and AXI4.
658 Argument: stage. see Stage API above
660 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
661 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
662 stage-1 p.i_data >>in stage n.o_data out>> stage+1
667 Inputs Temporary Output
668 ------- ---------- -----
669 P P N N PiV& ~NiV& N P
696 def elaborate(self
, platform
):
697 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
700 result
= self
.stage
.ospec()
702 # establish some combinatorial temporaries
703 n_i_ready
= Signal(reset_less
=True, name
="n_i_rdy_data")
704 p_i_valid_p_o_ready
= Signal(reset_less
=True)
705 p_i_valid
= Signal(reset_less
=True)
706 m
.d
.comb
+= [p_i_valid
.eq(self
.p
.i_valid_test
),
707 n_i_ready
.eq(self
.n
.i_ready_test
),
708 p_i_valid_p_o_ready
.eq(p_i_valid
& self
.p
.o_ready
),
711 # store result of processing in combinatorial temporary
712 m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
714 # previous valid and ready
715 with m
.If(p_i_valid_p_o_ready
):
716 m
.d
.sync
+= [r_busy
.eq(1), # output valid
717 eq(self
.n
.o_data
, result
), # update output
719 # previous invalid or not ready, however next is accepting
720 with m
.Elif(n_i_ready
):
721 m
.d
.sync
+= [eq(self
.n
.o_data
, result
)]
722 # TODO: could still send data here (if there was any)
723 #m.d.sync += self.n.o_valid.eq(0) # ...so set output invalid
724 m
.d
.sync
+= r_busy
.eq(0) # ...so set output invalid
726 m
.d
.comb
+= self
.n
.o_valid
.eq(r_busy
)
727 # if next is ready, so is previous
728 m
.d
.comb
+= self
.p
._o
_ready
.eq(n_i_ready
)
733 class UnbufferedPipeline(ControlBase
):
734 """ A simple pipeline stage with single-clock synchronisation
735 and two-way valid/ready synchronised signalling.
737 Note that a stall in one stage will result in the entire pipeline
740 Also that unlike BufferedHandshake, the valid/ready signalling does NOT
741 travel synchronously with the data: the valid/ready signalling
742 combines in a *combinatorial* fashion. Therefore, a long pipeline
743 chain will lengthen propagation delays.
745 Argument: stage. see Stage API, above
747 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
748 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
749 stage-1 p.i_data >>in stage n.o_data out>> stage+1
757 p.i_data : StageInput, shaped according to ispec
759 p.o_data : StageOutput, shaped according to ospec
761 r_data : input_shape according to ispec
762 A temporary (buffered) copy of a prior (valid) input.
763 This is HELD if the output is not ready. It is updated
765 result: output_shape according to ospec
766 The output of the combinatorial logic. it is updated
767 COMBINATORIALLY (no clock dependence).
799 Note: PoR is *NOT* involved in the above decision-making.
802 def elaborate(self
, platform
):
803 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
805 data_valid
= Signal() # is data valid or not
806 r_data
= self
.stage
.ospec() # output type
809 p_i_valid
= Signal(reset_less
=True)
810 pv
= Signal(reset_less
=True)
811 m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
812 m
.d
.comb
+= pv
.eq(self
.p
.i_valid
& self
.p
.o_ready
)
814 m
.d
.comb
+= self
.n
.o_valid
.eq(data_valid
)
815 m
.d
.comb
+= self
.p
._o
_ready
.eq(~data_valid | self
.n
.i_ready_test
)
816 m
.d
.sync
+= data_valid
.eq(p_i_valid | \
817 (~self
.n
.i_ready_test
& data_valid
))
819 m
.d
.sync
+= eq(r_data
, self
.stage
.process(self
.p
.i_data
))
820 m
.d
.comb
+= eq(self
.n
.o_data
, r_data
)
825 class UnbufferedPipeline2(ControlBase
):
826 """ A simple pipeline stage with single-clock synchronisation
827 and two-way valid/ready synchronised signalling.
829 Note that a stall in one stage will result in the entire pipeline
832 Also that unlike BufferedHandshake, the valid/ready signalling does NOT
833 travel synchronously with the data: the valid/ready signalling
834 combines in a *combinatorial* fashion. Therefore, a long pipeline
835 chain will lengthen propagation delays.
837 Argument: stage. see Stage API, above
839 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
840 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
841 stage-1 p.i_data >>in stage n.o_data out>> stage+1
846 p.i_data : StageInput, shaped according to ispec
848 p.o_data : StageOutput, shaped according to ospec
850 buf : output_shape according to ospec
851 A temporary (buffered) copy of a valid output
852 This is HELD if the output is not ready. It is updated
856 def elaborate(self
, platform
):
857 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
859 buf_full
= Signal() # is data valid or not
860 buf
= self
.stage
.ospec() # output type
863 p_i_valid
= Signal(reset_less
=True)
864 m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
866 m
.d
.comb
+= self
.n
.o_valid
.eq(buf_full | p_i_valid
)
867 m
.d
.comb
+= self
.p
._o
_ready
.eq(~buf_full
)
868 m
.d
.sync
+= buf_full
.eq(~self
.n
.i_ready_test
& self
.n
.o_valid
)
870 odata
= Mux(buf_full
, buf
, self
.stage
.process(self
.p
.i_data
))
871 m
.d
.comb
+= eq(self
.n
.o_data
, odata
)
872 m
.d
.sync
+= eq(buf
, self
.n
.o_data
)
877 class PassThroughStage(StageCls
):
878 """ a pass-through stage which has its input data spec equal to its output,
879 and "passes through" its data from input to output.
881 def __init__(self
, iospecfn
):
882 self
.iospecfn
= iospecfn
883 def ispec(self
): return self
.iospecfn()
884 def ospec(self
): return self
.iospecfn()
885 def process(self
, i
): return i
888 class PassThroughHandshake(ControlBase
):
889 """ A control block that delays by one clock cycle.
892 def elaborate(self
, platform
):
893 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
896 p_i_valid
= Signal(reset_less
=True)
897 pvr
= Signal(reset_less
=True)
898 m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
899 m
.d
.comb
+= pvr
.eq(p_i_valid
& self
.p
.o_ready
)
901 m
.d
.comb
+= self
.p
.o_ready
.eq(~self
.n
.o_valid | self
.n
.i_ready_test
)
902 m
.d
.sync
+= self
.n
.o_valid
.eq(p_i_valid | ~self
.p
.o_ready
)
904 odata
= Mux(pvr
, self
.stage
.process(self
.p
.i_data
), self
.n
.o_data
)
905 m
.d
.sync
+= eq(self
.n
.o_data
, odata
)
910 class RegisterPipeline(UnbufferedPipeline
):
911 """ A pipeline stage that delays by one clock cycle, creating a
912 sync'd latch out of o_data and o_valid as an indirect byproduct
913 of using PassThroughStage
915 def __init__(self
, iospecfn
):
916 UnbufferedPipeline
.__init
__(self
, PassThroughStage(iospecfn
))
919 class FIFOtest(ControlBase
):
920 """ A test of using a SyncFIFO to see if it will work.
921 Note: the only things it will accept is a Signal of width "width".
924 def __init__(self
, width
, depth
):
929 return Signal(width
, name
="data")
930 stage
= PassThroughStage(iospecfn
)
931 ControlBase
.__init
__(self
, stage
=stage
)
933 def elaborate(self
, platform
):
934 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
936 fifo
= SyncFIFO(self
.fwidth
, self
.fdepth
)
938 # prev: make the FIFO "look" like a PrevControl...
940 fp
.i_valid
= fifo
.writable
941 fp
._o
_ready
= fifo
.we
943 # ... so we can do this!
944 m
.d
.comb
+= fp
._connect
_in
(self
)
946 # next: make the FIFO "look" like a NextControl...
948 fn
.o_valid
= fifo
.readable
950 fn
.o_data
= fifo
.dout
951 # ... so we can do this!
952 m
.d
.comb
+= fn
._connect
_out
(self
)
954 # err... that should be all!