6f9d8c8e2e2a479dcfb1595b5e1346d3118e9858
1 from sfpy
import Float32
2 from nmigen
.compat
.sim
import run_simulation
3 from dual_add_experiment
import ALU
6 def get_case(dut
, a
, b
, c
):
11 a_ack
= (yield dut
.a
.ack
)
18 b_ack
= (yield dut
.b
.ack
)
25 c_ack
= (yield dut
.c
.ack
)
29 out_z_stb
= (yield dut
.int_stb
)
36 out_z_stb
= (yield dut
.z
.stb
)
54 def check_case(dut
, a
, b
, c
, z
):
55 out_z
= yield from get_case(dut
, a
, b
, c
)
56 assert out_z
== z
, "Output z 0x%x != 0x%x" % (out_z
, z
)
59 yield from check_case(dut
, 0, 0, 0, 0)
60 yield from check_case(dut
, 0x3F800000, 0x40000000, 0xc0000000, 0x3F800000)
62 if __name__
== '__main__':
64 run_simulation(dut
, testbench(dut
), vcd_name
="test_dual_add.vcd")