f88d8f975e0fa8f8743d05acbd4674f7afa35822
1 # IEEE Floating Point Divider (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
, Const
, Cat
6 from nmigen
.cli
import main
, verilog
, rtlil
7 from nmigen
.compat
.sim
import run_simulation
10 from fpbase
import FPNumIn
, FPNumOut
, FPOpIn
, FPOpOut
, FPBase
, FPState
11 from singlepipe
import eq
, SimpleHandshake
, ControlBase
12 from test_buf_pipe
import data_chain2
, Test5
17 def __init__(self
, width
):
21 self
.in_a
= FPOpIn(width
)
22 self
.in_b
= FPOpIn(width
)
23 self
.out_z
= FPOpOut(width
)
27 def add_state(self
, state
):
28 self
.states
.append(state
)
31 def elaborate(self
, platform
=None):
32 """ creates the HDL code-fragment for FPDiv
37 a
= FPNumIn(None, self
.width
, False)
38 z
= FPNumOut(self
.width
, False)
43 m
.d
.comb
+= a
.v
.eq(self
.in_a
.v
)
50 with m
.State("get_a"):
51 res
= self
.get_op(m
, self
.in_a
, a
, "add_1")
52 m
.d
.sync
+= eq([a
, self
.in_a
.ready_o
], res
)
54 with m
.State("add_1"):
58 z
.e
.eq(a
.e
), # exponent
59 z
.m
.eq(a
.m
+ 1), # mantissa
66 self
.pack(m
, z
, "put_z")
71 with m
.State("put_z"):
72 self
.put_z(m
, z
, self
.out_z
, "get_a")
76 class FPDIVPipe(ControlBase
):
78 def __init__(self
, width
):
80 self
.fpdiv
= FPDIV(width
=width
)
81 ControlBase
.__init
__(self
, self
)
84 return Signal(self
.width
, name
="a")
87 return Signal(self
.width
, name
="z")
89 def setup(self
, m
, i
):
90 m
.d
.comb
+= self
.fpdiv
.in_a
.v
.eq(i
) # connect input
93 return self
.fpdiv
.out_z
.v
# return z output
95 def elaborate(self
, platform
):
96 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
98 m
.submodules
.fpdiv
= self
.fpdiv
100 # see if connecting to stb/ack works
101 m
.d
.comb
+= self
.p
.ready_o
.eq(self
.fpdiv
.in_a
.ready_o
)
102 m
.d
.comb
+= self
.fpdiv
.in_a
.i_valid
.eq(self
.p
.i_valid_test
)
104 m
.d
.comb
+= self
.n
.o_valid
.eq(self
.fpdiv
.out_z
.o_valid
)
105 m
.d
.comb
+= self
.fpdiv
.out_z
.i_ready
.eq(self
.n
.i_ready_test
)
106 m
.d
.comb
+= self
.n
.o_data
.eq(self
.fpdiv
.out_z
.v
)
110 def resultfn(o_data
, expected
, i
, o
):
112 assert o_data
== res
, \
113 "%d-%d received data %x not match expected %x\n" \
114 % (i
, o
, o_data
, res
)
117 if __name__
== "__main__":
118 dut
= FPDIVPipe(width
=16)
121 vl
= rtlil
.convert(dut
, ports
=ports
)
122 with
open("test_fsm_experiment.il", "w") as f
:
124 test
= Test5(dut
, resultfn
, data
=data
)
125 run_simulation(dut
, [test
.send
, test
.rcv
],
126 vcd_name
="test_fsm_experiment.vcd")