src/add/test_inputgroup.py

   1 from random import randint
   2 from nmigen import Module, Signal
   3 from nmigen.compat.sim import run_simulation
   4 from nmigen.cli import verilog
   5
   6 from nmigen_add_experiment import InputGroup
   7
   8
   9 def testbench(dut):
  10     stb = yield dut.out_op.stb
  11     assert stb == 0
  12     ack = yield dut.out_op.ack
  13     assert ack == 0
  14
  15     # set row 1 input 0
  16     yield dut.rs[1].in_op[0].eq(5)
  17     yield dut.rs[1].stb.eq(0b01) # strobe indicate 1st op ready
  18     yield dut.rs[1].ack.eq(1)
  19     yield
  20     yield
  21
  22     # check row 1 output (should be inactive)
  23     decode = yield dut.rs[1].out_decode
  24     assert decode == 0
  25     op0 = yield dut.rs[1].out_op[0]
  26     op1 = yield dut.rs[1].out_op[1]
  27     assert op0 == 0 and op1 == 0
  28
  29     # output should be inactive
  30     out_stb = yield dut.out_op.stb
  31     assert out_stb == 0
  32
  33     # set row 0 input 1
  34     yield dut.rs[1].in_op[1].eq(6)
  35     yield dut.rs[1].stb.eq(0b11) # strobe indicate both ops ready
  36     yield
  37     yield
  38
  39     # row 0 output should be active
  40     decode = yield dut.rs[1].out_decode
  41     assert decode == 1
  42     op0 = yield dut.rs[1].out_op[0]
  43     op1 = yield dut.rs[1].out_op[1]
  44     assert op0 == 5 and op1 == 6
  45
  46     # output should be active, MID should be 0 until "ack" is set
  47     out_stb = yield dut.out_op.stb
  48     assert out_stb == 1
  49     out_mid = yield dut.mid
  50     assert out_mid == 0
  51
  52     yield dut.out_op.ack.eq(1)
  53     yield
  54     yield
  55     yield
  56     yield
  57
  58     op0 = yield dut.out_op.v[0]
  59     op1 = yield dut.out_op.v[1]
  60     assert op0 == 5 and op1 == 6
  61
  62
  63 if __name__ == '__main__':
  64     dut = InputGroup(width=32)
  65     vl = verilog.convert(dut, ports=dut.ports())
  66     with open("test_inputgroup.v", "w") as f:
  67         f.write(vl)
  68     run_simulation(dut, testbench(dut), vcd_name="test_inputgroup.vcd")