5fa649ef83f79dcbce7d3338da418d02dd9b9b2d
1 from random
import randint
2 from nmigen
import Module
, Signal
3 from nmigen
.compat
.sim
import run_simulation
5 from fpbase
import MultiShift
, MultiShiftR
8 def __init__(self
, width
):
9 self
.ms
= MultiShift(width
)
10 self
.a
= Signal(width
)
11 self
.b
= Signal(self
.ms
.smax
)
12 self
.x
= Signal(width
)
14 def get_fragment(self
, platform
=None):
17 m
.d
.comb
+= self
.x
.eq(self
.ms
.lshift(self
.a
, self
.b
))
22 def __init__(self
, width
):
23 self
.ms
= MultiShift(width
)
24 self
.a
= Signal(width
)
25 self
.b
= Signal(self
.ms
.smax
)
26 self
.x
= Signal(width
)
28 def get_fragment(self
, platform
=None):
31 m
.d
.comb
+= self
.x
.eq(self
.ms
.rshift(self
.a
, self
.b
))
35 class MultiShiftModRMod
:
36 def __init__(self
, width
):
37 self
.ms
= MultiShiftR(width
)
38 self
.a
= Signal(width
)
39 self
.b
= Signal(self
.ms
.smax
)
40 self
.x
= Signal(width
)
42 def get_fragment(self
, platform
=None):
45 m
.submodules
+= self
.ms
46 m
.d
.comb
+= self
.ms
.i
.eq(self
.a
)
47 m
.d
.comb
+= self
.ms
.s
.eq(self
.b
)
48 m
.d
.comb
+= self
.x
.eq(self
.ms
.o
)
52 def check_case(dut
, width
, a
, b
):
57 x
= (a
<< b
) & ((1<<width
)-1)
60 assert out_x
== x
, "Output x 0x%x not equal to expected 0x%x" % (out_x
, x
)
62 def check_caser(dut
, width
, a
, b
):
67 x
= (a
>> b
) & ((1<<width
)-1)
70 assert out_x
== x
, "Output x 0x%x not equal to expected 0x%x" % (out_x
, x
)
75 a
= randint(0, (1<<32)-1)
76 yield from check_case(dut
, 32, a
, i
)
81 a
= randint(0, (1<<32)-1)
82 yield from check_caser(dut
, 32, a
, i
)
84 if __name__
== '__main__':
85 dut
= MultiShiftModRMod(width
=32)
86 run_simulation(dut
, testbenchr(dut
), vcd_name
="test_multishift.vcd")
88 dut
= MultiShiftModR(width
=32)
89 run_simulation(dut
, testbenchr(dut
), vcd_name
="test_multishift.vcd")
91 dut
= MultiShiftModL(width
=32)
92 run_simulation(dut
, testbench(dut
), vcd_name
="test_multishift.vcd")