f1b0774f3153608f8332ced346b6b60a16407f12
1 from random
import randint
3 from nmigen
import Module
, Signal
, Cat
4 from nmigen
.compat
.sim
import run_simulation
5 from nmigen
.cli
import verilog
, rtlil
7 from multipipe
import CombMuxOutPipe
8 from singlepipe
import SimpleHandshake
, PassThroughHandshake
13 self
.mid
= Signal(2, reset_less
=True)
14 self
.data
= Signal(16, reset_less
=True)
21 return [self
.mid
.eq(i
.mid
), self
.data
.eq(i
.data
)]
24 return [self
.mid
, self
.data
]
27 class PassThroughStage
:
33 return Signal(16, name
="data_out", reset_less
=True)
39 class PassThroughDataStage
:
43 return self
.ispec() # same as ospec
46 return i
# pass-through
50 class PassThroughPipe(PassThroughHandshake
):
52 PassThroughHandshake
.__init
__(self
, PassThroughDataStage())
58 stb
= yield dut
.out_op
.stb
60 ack
= yield dut
.out_op
.ack
64 yield dut
.rs
[1].in_op
[0].eq(5)
65 yield dut
.rs
[1].stb
.eq(0b01) # strobe indicate 1st op ready
66 #yield dut.rs[1].ack.eq(1)
69 # check row 1 output (should be inactive)
70 decode
= yield dut
.rs
[1].out_decode
73 op0
= yield dut
.rs
[1].out_op
[0]
74 op1
= yield dut
.rs
[1].out_op
[1]
75 assert op0
== 0 and op1
== 0
77 # output should be inactive
78 out_stb
= yield dut
.out_op
.stb
82 yield dut
.rs
[1].in_op
[1].eq(6)
83 yield dut
.rs
[1].stb
.eq(0b11) # strobe indicate both ops ready
85 # set acknowledgement of output... takes 1 cycle to respond
86 yield dut
.out_op
.ack
.eq(1)
88 yield dut
.out_op
.ack
.eq(0) # clear ack on output
89 yield dut
.rs
[1].stb
.eq(0) # clear row 1 strobe
91 # output strobe should be active, MID should be 0 until "ack" is set...
92 out_stb
= yield dut
.out_op
.stb
94 out_mid
= yield dut
.mid
97 # ... and output should not yet be passed through either
98 op0
= yield dut
.out_op
.v
[0]
99 op1
= yield dut
.out_op
.v
[1]
100 assert op0
== 0 and op1
== 0
102 # wait for out_op.ack to activate...
103 yield dut
.rs
[1].stb
.eq(0b00) # set row 1 strobes to zero
106 # *now* output should be passed through
107 op0
= yield dut
.out_op
.v
[0]
108 op1
= yield dut
.out_op
.v
[1]
109 assert op0
== 5 and op1
== 6
112 yield dut
.rs
[2].in_op
[0].eq(3)
113 yield dut
.rs
[2].in_op
[1].eq(4)
114 yield dut
.rs
[2].stb
.eq(0b11) # strobe indicate 1st op ready
115 yield dut
.out_op
.ack
.eq(1) # set output ack
117 yield dut
.rs
[2].stb
.eq(0) # clear row 2 strobe
118 yield dut
.out_op
.ack
.eq(0) # set output ack
120 op0
= yield dut
.out_op
.v
[0]
121 op1
= yield dut
.out_op
.v
[1]
122 assert op0
== 3 and op1
== 4, "op0 %d op1 %d" % (op0
, op1
)
123 out_mid
= yield dut
.mid
126 # set row 0 and 3 input
127 yield dut
.rs
[0].in_op
[0].eq(9)
128 yield dut
.rs
[0].in_op
[1].eq(8)
129 yield dut
.rs
[0].stb
.eq(0b11) # strobe indicate 1st op ready
130 yield dut
.rs
[3].in_op
[0].eq(1)
131 yield dut
.rs
[3].in_op
[1].eq(2)
132 yield dut
.rs
[3].stb
.eq(0b11) # strobe indicate 1st op ready
134 # set acknowledgement of output... takes 1 cycle to respond
135 yield dut
.out_op
.ack
.eq(1)
137 yield dut
.rs
[0].stb
.eq(0) # clear row 1 strobe
139 out_mid
= yield dut
.mid
140 assert out_mid
== 0, "out mid %d" % out_mid
143 yield dut
.rs
[3].stb
.eq(0) # clear row 1 strobe
144 yield dut
.out_op
.ack
.eq(0) # clear ack on output
146 out_mid
= yield dut
.mid
147 assert out_mid
== 3, "out mid %d" % out_mid
151 def __init__(self
, dut
):
156 for i
in range(self
.tlen
* dut
.num_rows
):
160 mid
= randint(0, dut
.num_rows
-1)
161 data
= randint(0, 255) + (mid
<<8)
162 if mid
not in self
.do
:
164 self
.di
.append((data
, mid
))
165 self
.do
[mid
].append(data
)
168 for i
in range(self
.tlen
* dut
.num_rows
):
172 yield rs
.i_valid
.eq(1)
173 yield rs
.i_data
.data
.eq(op2
)
174 yield rs
.i_data
.mid
.eq(mid
)
176 o_p_ready
= yield rs
.o_ready
179 o_p_ready
= yield rs
.o_ready
181 print ("send", mid
, i
, hex(op2
))
183 yield rs
.i_valid
.eq(0)
184 # wait random period of time before queueing another value
185 for i
in range(randint(0, 3)):
188 yield rs
.i_valid
.eq(0)
193 stall_range
= randint(0, 3)
194 while out_i
!= len(self
.do
[mid
]):
196 assert count
!= 2000, "timeout: too long"
198 yield n
.i_ready
.eq(1)
200 o_n_valid
= yield n
.o_valid
201 i_n_ready
= yield n
.i_ready
202 if not o_n_valid
or not i_n_ready
:
205 out_v
= yield n
.o_data
207 print ("recv", mid
, out_i
, hex(out_v
))
209 assert self
.do
[mid
][out_i
] == out_v
# pass-through data
213 if randint(0, 5) == 0:
214 stall_range
= randint(0, 3)
215 stall
= randint(0, stall_range
) != 0
217 yield n
.i_ready
.eq(0)
218 for i
in range(stall_range
):
222 class TestPriorityMuxPipe(CombMuxOutPipe
):
223 def __init__(self
, num_rows
):
224 self
.num_rows
= num_rows
225 stage
= PassThroughStage()
226 CombMuxOutPipe
.__init
__(self
, stage
, n_len
=self
.num_rows
)
229 class TestSyncToPriorityPipe
:
232 self
.pipe
= PassThroughPipe()
233 self
.muxpipe
= TestPriorityMuxPipe(self
.num_rows
)
236 self
.n
= self
.muxpipe
.n
238 def elaborate(self
, platform
):
240 m
.submodules
.pipe
= self
.pipe
241 m
.submodules
.muxpipe
= self
.muxpipe
242 m
.d
.comb
+= self
.pipe
.n
.connect_to_next(self
.muxpipe
.p
)
246 res
= [self
.p
.i_valid
, self
.p
.o_ready
] + \
247 self
.p
.i_data
.ports()
248 for i
in range(len(self
.n
)):
249 res
+= [self
.n
[i
].i_ready
, self
.n
[i
].o_valid
] + \
251 #self.n[i].o_data.ports()
255 if __name__
== '__main__':
256 dut
= TestSyncToPriorityPipe()
257 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
258 with
open("test_outmux_pipe.il", "w") as f
:
260 #run_simulation(dut, testbench(dut), vcd_name="test_inputgroup.vcd")
262 test
= OutputTest(dut
)
263 run_simulation(dut
, [test
.rcv(1), test
.rcv(0),
264 test
.rcv(3), test
.rcv(2),
266 vcd_name
="test_outmux_pipe.vcd")