2 * Copyright © 2018 Valve Corporation
3 * Copyright © 2018 Google
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "ac_shader_util.h"
33 #include "aco_builder.h"
34 #include "aco_interface.h"
35 #include "aco_instruction_selection_setup.cpp"
36 #include "util/fast_idiv_by_const.h"
41 #define isel_err(...) _isel_err(ctx, __FILE__, __LINE__, __VA_ARGS__)
43 static void _isel_err(isel_context
*ctx
, const char *file
, unsigned line
,
44 const nir_instr
*instr
, const char *msg
)
48 FILE *memf
= open_memstream(&out
, &outsize
);
50 fprintf(memf
, "%s: ", msg
);
51 nir_print_instr(instr
, memf
);
54 _aco_err(ctx
->program
, file
, line
, out
);
58 class loop_info_RAII
{
60 unsigned header_idx_old
;
62 bool divergent_cont_old
;
63 bool divergent_branch_old
;
64 bool divergent_if_old
;
67 loop_info_RAII(isel_context
* ctx
, unsigned loop_header_idx
, Block
* loop_exit
)
69 header_idx_old(ctx
->cf_info
.parent_loop
.header_idx
), exit_old(ctx
->cf_info
.parent_loop
.exit
),
70 divergent_cont_old(ctx
->cf_info
.parent_loop
.has_divergent_continue
),
71 divergent_branch_old(ctx
->cf_info
.parent_loop
.has_divergent_branch
),
72 divergent_if_old(ctx
->cf_info
.parent_if
.is_divergent
)
74 ctx
->cf_info
.parent_loop
.header_idx
= loop_header_idx
;
75 ctx
->cf_info
.parent_loop
.exit
= loop_exit
;
76 ctx
->cf_info
.parent_loop
.has_divergent_continue
= false;
77 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
78 ctx
->cf_info
.parent_if
.is_divergent
= false;
79 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
84 ctx
->cf_info
.parent_loop
.header_idx
= header_idx_old
;
85 ctx
->cf_info
.parent_loop
.exit
= exit_old
;
86 ctx
->cf_info
.parent_loop
.has_divergent_continue
= divergent_cont_old
;
87 ctx
->cf_info
.parent_loop
.has_divergent_branch
= divergent_branch_old
;
88 ctx
->cf_info
.parent_if
.is_divergent
= divergent_if_old
;
89 ctx
->cf_info
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
- 1;
90 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
)
91 ctx
->cf_info
.exec_potentially_empty_discard
= false;
99 bool exec_potentially_empty_discard_old
;
100 bool exec_potentially_empty_break_old
;
101 uint16_t exec_potentially_empty_break_depth_old
;
105 bool uniform_has_then_branch
;
106 bool then_branch_divergent
;
111 static bool visit_cf_list(struct isel_context
*ctx
,
112 struct exec_list
*list
);
114 static void add_logical_edge(unsigned pred_idx
, Block
*succ
)
116 succ
->logical_preds
.emplace_back(pred_idx
);
120 static void add_linear_edge(unsigned pred_idx
, Block
*succ
)
122 succ
->linear_preds
.emplace_back(pred_idx
);
125 static void add_edge(unsigned pred_idx
, Block
*succ
)
127 add_logical_edge(pred_idx
, succ
);
128 add_linear_edge(pred_idx
, succ
);
131 static void append_logical_start(Block
*b
)
133 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_start
);
136 static void append_logical_end(Block
*b
)
138 Builder(NULL
, b
).pseudo(aco_opcode::p_logical_end
);
141 Temp
get_ssa_temp(struct isel_context
*ctx
, nir_ssa_def
*def
)
143 assert(ctx
->allocated
[def
->index
].id());
144 return ctx
->allocated
[def
->index
];
147 Temp
emit_mbcnt(isel_context
*ctx
, Definition dst
,
148 Operand mask_lo
= Operand((uint32_t) -1), Operand mask_hi
= Operand((uint32_t) -1))
150 Builder
bld(ctx
->program
, ctx
->block
);
151 Definition lo_def
= ctx
->program
->wave_size
== 32 ? dst
: bld
.def(v1
);
152 Temp thread_id_lo
= bld
.vop3(aco_opcode::v_mbcnt_lo_u32_b32
, lo_def
, mask_lo
, Operand(0u));
154 if (ctx
->program
->wave_size
== 32) {
156 } else if (ctx
->program
->chip_class
<= GFX7
) {
157 Temp thread_id_hi
= bld
.vop2(aco_opcode::v_mbcnt_hi_u32_b32
, dst
, mask_hi
, thread_id_lo
);
160 Temp thread_id_hi
= bld
.vop3(aco_opcode::v_mbcnt_hi_u32_b32_e64
, dst
, mask_hi
, thread_id_lo
);
165 Temp
emit_wqm(isel_context
*ctx
, Temp src
, Temp dst
=Temp(0, s1
), bool program_needs_wqm
= false)
167 Builder
bld(ctx
->program
, ctx
->block
);
170 dst
= bld
.tmp(src
.regClass());
172 assert(src
.size() == dst
.size());
174 if (ctx
->stage
!= fragment_fs
) {
178 bld
.copy(Definition(dst
), src
);
182 bld
.pseudo(aco_opcode::p_wqm
, Definition(dst
), src
);
183 ctx
->program
->needs_wqm
|= program_needs_wqm
;
187 static Temp
emit_bpermute(isel_context
*ctx
, Builder
&bld
, Temp index
, Temp data
)
189 if (index
.regClass() == s1
)
190 return bld
.readlane(bld
.def(s1
), data
, index
);
192 if (ctx
->options
->chip_class
<= GFX7
) {
193 /* GFX6-7: there is no bpermute instruction */
194 Operand
index_op(index
);
195 Operand
input_data(data
);
196 index_op
.setLateKill(true);
197 input_data
.setLateKill(true);
199 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(bld
.lm
), bld
.def(bld
.lm
, vcc
), index_op
, input_data
);
200 } else if (ctx
->options
->chip_class
>= GFX10
&& ctx
->program
->wave_size
== 64) {
201 /* GFX10 wave64 mode: emulate full-wave bpermute */
202 if (!ctx
->has_gfx10_wave64_bpermute
) {
203 ctx
->has_gfx10_wave64_bpermute
= true;
204 ctx
->program
->config
->num_shared_vgprs
= 8; /* Shared VGPRs are allocated in groups of 8 */
205 ctx
->program
->vgpr_limit
-= 4; /* We allocate 8 shared VGPRs, so we'll have 4 fewer normal VGPRs */
208 Temp index_is_lo
= bld
.vopc(aco_opcode::v_cmp_ge_u32
, bld
.def(bld
.lm
), Operand(31u), index
);
209 Builder::Result index_is_lo_split
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), index_is_lo
);
210 Temp index_is_lo_n1
= bld
.sop1(aco_opcode::s_not_b32
, bld
.def(s1
), bld
.def(s1
, scc
), index_is_lo_split
.def(1).getTemp());
211 Operand same_half
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), index_is_lo_split
.def(0).getTemp(), index_is_lo_n1
);
212 Operand index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
213 Operand
input_data(data
);
215 index_x4
.setLateKill(true);
216 input_data
.setLateKill(true);
217 same_half
.setLateKill(true);
219 return bld
.pseudo(aco_opcode::p_bpermute
, bld
.def(v1
), bld
.def(s2
), bld
.def(s1
, scc
), index_x4
, input_data
, same_half
);
221 /* GFX8-9 or GFX10 wave32: bpermute works normally */
222 Temp index_x4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), index
);
223 return bld
.ds(aco_opcode::ds_bpermute_b32
, bld
.def(v1
), index_x4
, data
);
227 static Temp
emit_masked_swizzle(isel_context
*ctx
, Builder
&bld
, Temp src
, unsigned mask
)
229 if (ctx
->options
->chip_class
>= GFX8
) {
230 unsigned and_mask
= mask
& 0x1f;
231 unsigned or_mask
= (mask
>> 5) & 0x1f;
232 unsigned xor_mask
= (mask
>> 10) & 0x1f;
234 uint16_t dpp_ctrl
= 0xffff;
236 // TODO: we could use DPP8 for some swizzles
237 if (and_mask
== 0x1f && or_mask
< 4 && xor_mask
< 4) {
238 unsigned res
[4] = {0, 1, 2, 3};
239 for (unsigned i
= 0; i
< 4; i
++)
240 res
[i
] = ((res
[i
] | or_mask
) ^ xor_mask
) & 0x3;
241 dpp_ctrl
= dpp_quad_perm(res
[0], res
[1], res
[2], res
[3]);
242 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 8) {
243 dpp_ctrl
= dpp_row_rr(8);
244 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 0xf) {
245 dpp_ctrl
= dpp_row_mirror
;
246 } else if (and_mask
== 0x1f && !or_mask
&& xor_mask
== 0x7) {
247 dpp_ctrl
= dpp_row_half_mirror
;
250 if (dpp_ctrl
!= 0xffff)
251 return bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
254 return bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, mask
, 0, false);
257 Temp
as_vgpr(isel_context
*ctx
, Temp val
)
259 if (val
.type() == RegType::sgpr
) {
260 Builder
bld(ctx
->program
, ctx
->block
);
261 return bld
.copy(bld
.def(RegType::vgpr
, val
.size()), val
);
263 assert(val
.type() == RegType::vgpr
);
267 //assumes a != 0xffffffff
268 void emit_v_div_u32(isel_context
*ctx
, Temp dst
, Temp a
, uint32_t b
)
271 Builder
bld(ctx
->program
, ctx
->block
);
273 if (util_is_power_of_two_or_zero(b
)) {
274 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)util_logbase2(b
)), a
);
278 util_fast_udiv_info info
= util_compute_fast_udiv_info(b
, 32, 32);
280 assert(info
.multiplier
<= 0xffffffff);
282 bool pre_shift
= info
.pre_shift
!= 0;
283 bool increment
= info
.increment
!= 0;
284 bool multiply
= true;
285 bool post_shift
= info
.post_shift
!= 0;
287 if (!pre_shift
&& !increment
&& !multiply
&& !post_shift
) {
288 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), a
);
292 Temp pre_shift_dst
= a
;
294 pre_shift_dst
= (increment
|| multiply
|| post_shift
) ? bld
.tmp(v1
) : dst
;
295 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(pre_shift_dst
), Operand((uint32_t)info
.pre_shift
), a
);
298 Temp increment_dst
= pre_shift_dst
;
300 increment_dst
= (post_shift
|| multiply
) ? bld
.tmp(v1
) : dst
;
301 bld
.vadd32(Definition(increment_dst
), Operand((uint32_t) info
.increment
), pre_shift_dst
);
304 Temp multiply_dst
= increment_dst
;
306 multiply_dst
= post_shift
? bld
.tmp(v1
) : dst
;
307 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(multiply_dst
), increment_dst
,
308 bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand((uint32_t)info
.multiplier
)));
312 bld
.vop2(aco_opcode::v_lshrrev_b32
, Definition(dst
), Operand((uint32_t)info
.post_shift
), multiply_dst
);
316 void emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, Temp dst
)
318 Builder
bld(ctx
->program
, ctx
->block
);
319 bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(idx
));
323 Temp
emit_extract_vector(isel_context
* ctx
, Temp src
, uint32_t idx
, RegClass dst_rc
)
325 /* no need to extract the whole vector */
326 if (src
.regClass() == dst_rc
) {
331 assert(src
.bytes() > (idx
* dst_rc
.bytes()));
332 Builder
bld(ctx
->program
, ctx
->block
);
333 auto it
= ctx
->allocated_vec
.find(src
.id());
334 if (it
!= ctx
->allocated_vec
.end() && dst_rc
.bytes() == it
->second
[idx
].regClass().bytes()) {
335 if (it
->second
[idx
].regClass() == dst_rc
) {
336 return it
->second
[idx
];
338 assert(!dst_rc
.is_subdword());
339 assert(dst_rc
.type() == RegType::vgpr
&& it
->second
[idx
].type() == RegType::sgpr
);
340 return bld
.copy(bld
.def(dst_rc
), it
->second
[idx
]);
344 if (dst_rc
.is_subdword())
345 src
= as_vgpr(ctx
, src
);
347 if (src
.bytes() == dst_rc
.bytes()) {
349 return bld
.copy(bld
.def(dst_rc
), src
);
351 Temp dst
= bld
.tmp(dst_rc
);
352 emit_extract_vector(ctx
, src
, idx
, dst
);
357 void emit_split_vector(isel_context
* ctx
, Temp vec_src
, unsigned num_components
)
359 if (num_components
== 1)
361 if (ctx
->allocated_vec
.find(vec_src
.id()) != ctx
->allocated_vec
.end())
364 if (num_components
> vec_src
.size()) {
365 if (vec_src
.type() == RegType::sgpr
) {
366 /* should still help get_alu_src() */
367 emit_split_vector(ctx
, vec_src
, vec_src
.size());
370 /* sub-dword split */
371 rc
= RegClass(RegType::vgpr
, vec_src
.bytes() / num_components
).as_subdword();
373 rc
= RegClass(vec_src
.type(), vec_src
.size() / num_components
);
375 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, num_components
)};
376 split
->operands
[0] = Operand(vec_src
);
377 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
378 for (unsigned i
= 0; i
< num_components
; i
++) {
379 elems
[i
] = {ctx
->program
->allocateId(), rc
};
380 split
->definitions
[i
] = Definition(elems
[i
]);
382 ctx
->block
->instructions
.emplace_back(std::move(split
));
383 ctx
->allocated_vec
.emplace(vec_src
.id(), elems
);
386 /* This vector expansion uses a mask to determine which elements in the new vector
387 * come from the original vector. The other elements are undefined. */
388 void expand_vector(isel_context
* ctx
, Temp vec_src
, Temp dst
, unsigned num_components
, unsigned mask
)
390 emit_split_vector(ctx
, vec_src
, util_bitcount(mask
));
395 Builder
bld(ctx
->program
, ctx
->block
);
396 if (num_components
== 1) {
397 if (dst
.type() == RegType::sgpr
)
398 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec_src
);
400 bld
.copy(Definition(dst
), vec_src
);
404 unsigned component_size
= dst
.size() / num_components
;
405 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
407 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
408 vec
->definitions
[0] = Definition(dst
);
410 for (unsigned i
= 0; i
< num_components
; i
++) {
411 if (mask
& (1 << i
)) {
412 Temp src
= emit_extract_vector(ctx
, vec_src
, k
++, RegClass(vec_src
.type(), component_size
));
413 if (dst
.type() == RegType::sgpr
)
414 src
= bld
.as_uniform(src
);
415 vec
->operands
[i
] = Operand(src
);
417 vec
->operands
[i
] = Operand(0u);
419 elems
[i
] = vec
->operands
[i
].getTemp();
421 ctx
->block
->instructions
.emplace_back(std::move(vec
));
422 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
425 /* adjust misaligned small bit size loads */
426 void byte_align_scalar(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
)
428 Builder
bld(ctx
->program
, ctx
->block
);
430 Temp select
= Temp();
431 if (offset
.isConstant()) {
432 assert(offset
.constantValue() && offset
.constantValue() < 4);
433 shift
= Operand(offset
.constantValue() * 8);
435 /* bit_offset = 8 * (offset & 0x3) */
436 Temp tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(3u));
437 select
= bld
.tmp(s1
);
438 shift
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.scc(Definition(select
)), tmp
, Operand(3u));
441 if (vec
.size() == 1) {
442 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), vec
, shift
);
443 } else if (vec
.size() == 2) {
444 Temp tmp
= dst
.size() == 2 ? dst
: bld
.tmp(s2
);
445 bld
.sop2(aco_opcode::s_lshr_b64
, Definition(tmp
), bld
.def(s1
, scc
), vec
, shift
);
447 emit_split_vector(ctx
, dst
, 2);
449 emit_extract_vector(ctx
, tmp
, 0, dst
);
450 } else if (vec
.size() == 4) {
451 Temp lo
= bld
.tmp(s2
), hi
= bld
.tmp(s2
);
452 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), vec
);
453 hi
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(s1
), hi
, Operand(0u));
454 if (select
!= Temp())
455 hi
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), hi
, Operand(0u), bld
.scc(select
));
456 lo
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), lo
, shift
);
457 Temp mid
= bld
.tmp(s1
);
458 lo
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), Definition(mid
), lo
);
459 hi
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, shift
);
460 mid
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, mid
);
461 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, mid
);
462 emit_split_vector(ctx
, dst
, 2);
466 void byte_align_vector(isel_context
*ctx
, Temp vec
, Operand offset
, Temp dst
, unsigned component_size
)
468 Builder
bld(ctx
->program
, ctx
->block
);
469 if (offset
.isTemp()) {
470 Temp tmp
[4] = {vec
, vec
, vec
, vec
};
472 if (vec
.size() == 4) {
473 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
), tmp
[3] = bld
.tmp(v1
);
474 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), Definition(tmp
[3]), vec
);
475 } else if (vec
.size() == 3) {
476 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = bld
.tmp(v1
);
477 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), Definition(tmp
[2]), vec
);
478 } else if (vec
.size() == 2) {
479 tmp
[0] = bld
.tmp(v1
), tmp
[1] = bld
.tmp(v1
), tmp
[2] = tmp
[1];
480 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp
[0]), Definition(tmp
[1]), vec
);
482 for (unsigned i
= 0; i
< dst
.size(); i
++)
483 tmp
[i
] = bld
.vop3(aco_opcode::v_alignbyte_b32
, bld
.def(v1
), tmp
[i
+ 1], tmp
[i
], offset
);
487 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), tmp
[0], tmp
[1]);
489 offset
= Operand(0u);
492 unsigned num_components
= vec
.bytes() / component_size
;
493 if (vec
.regClass() == dst
.regClass()) {
494 assert(offset
.constantValue() == 0);
495 bld
.copy(Definition(dst
), vec
);
496 emit_split_vector(ctx
, dst
, num_components
);
500 emit_split_vector(ctx
, vec
, num_components
);
501 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> elems
;
502 RegClass rc
= RegClass(RegType::vgpr
, component_size
).as_subdword();
504 assert(offset
.constantValue() % component_size
== 0);
505 unsigned skip
= offset
.constantValue() / component_size
;
506 for (unsigned i
= skip
; i
< num_components
; i
++)
507 elems
[i
- skip
] = emit_extract_vector(ctx
, vec
, i
, rc
);
509 /* if dst is vgpr - split the src and create a shrunk version according to the mask. */
510 if (dst
.type() == RegType::vgpr
) {
511 num_components
= dst
.bytes() / component_size
;
512 aco_ptr
<Pseudo_instruction
> create_vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
513 for (unsigned i
= 0; i
< num_components
; i
++)
514 create_vec
->operands
[i
] = Operand(elems
[i
]);
515 create_vec
->definitions
[0] = Definition(dst
);
516 bld
.insert(std::move(create_vec
));
518 /* if dst is sgpr - split the src, but move the original to sgpr. */
520 vec
= bld
.pseudo(aco_opcode::p_as_uniform
, bld
.def(RegClass(RegType::sgpr
, vec
.size())), vec
);
521 byte_align_scalar(ctx
, vec
, offset
, dst
);
523 assert(dst
.size() == vec
.size());
524 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), vec
);
527 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
530 Temp
bool_to_vector_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s2
))
532 Builder
bld(ctx
->program
, ctx
->block
);
534 dst
= bld
.tmp(bld
.lm
);
536 assert(val
.regClass() == s1
);
537 assert(dst
.regClass() == bld
.lm
);
539 return bld
.sop2(Builder::s_cselect
, Definition(dst
), Operand((uint32_t) -1), Operand(0u), bld
.scc(val
));
542 Temp
bool_to_scalar_condition(isel_context
*ctx
, Temp val
, Temp dst
= Temp(0, s1
))
544 Builder
bld(ctx
->program
, ctx
->block
);
548 assert(val
.regClass() == bld
.lm
);
549 assert(dst
.regClass() == s1
);
551 /* if we're currently in WQM mode, ensure that the source is also computed in WQM */
552 Temp tmp
= bld
.tmp(s1
);
553 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.scc(Definition(tmp
)), val
, Operand(exec
, bld
.lm
));
554 return emit_wqm(ctx
, tmp
, dst
);
557 Temp
convert_int(isel_context
*ctx
, Builder
& bld
, Temp src
, unsigned src_bits
, unsigned dst_bits
, bool is_signed
, Temp dst
=Temp())
560 if (dst_bits
% 32 == 0 || src
.type() == RegType::sgpr
)
561 dst
= bld
.tmp(src
.type(), DIV_ROUND_UP(dst_bits
, 32u));
563 dst
= bld
.tmp(RegClass(RegType::vgpr
, dst_bits
/ 8u).as_subdword());
566 if (dst
.bytes() == src
.bytes() && dst_bits
< src_bits
)
567 return bld
.copy(Definition(dst
), src
);
568 else if (dst
.bytes() < src
.bytes())
569 return bld
.pseudo(aco_opcode::p_extract_vector
, Definition(dst
), src
, Operand(0u));
573 tmp
= src_bits
== 32 ? src
: bld
.tmp(src
.type(), 1);
576 } else if (src
.regClass() == s1
) {
578 bld
.sop1(src_bits
== 8 ? aco_opcode::s_sext_i32_i8
: aco_opcode::s_sext_i32_i16
, Definition(tmp
), src
);
580 bld
.sop2(aco_opcode::s_and_b32
, Definition(tmp
), bld
.def(s1
, scc
), Operand(src_bits
== 8 ? 0xFFu
: 0xFFFFu
), src
);
581 } else if (ctx
->options
->chip_class
>= GFX8
) {
582 assert(src_bits
!= 8 || src
.regClass() == v1b
);
583 assert(src_bits
!= 16 || src
.regClass() == v2b
);
584 aco_ptr
<SDWA_instruction
> sdwa
{create_instruction
<SDWA_instruction
>(aco_opcode::v_mov_b32
, asSDWA(Format::VOP1
), 1, 1)};
585 sdwa
->operands
[0] = Operand(src
);
586 sdwa
->definitions
[0] = Definition(tmp
);
588 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_sbyte
: sdwa_sword
;
590 sdwa
->sel
[0] = src_bits
== 8 ? sdwa_ubyte
: sdwa_uword
;
591 sdwa
->dst_sel
= tmp
.bytes() == 2 ? sdwa_uword
: sdwa_udword
;
592 bld
.insert(std::move(sdwa
));
594 assert(ctx
->options
->chip_class
== GFX6
|| ctx
->options
->chip_class
== GFX7
);
595 aco_opcode opcode
= is_signed
? aco_opcode::v_bfe_i32
: aco_opcode::v_bfe_u32
;
596 bld
.vop3(opcode
, Definition(tmp
), src
, Operand(0u), Operand(src_bits
== 8 ? 8u : 16u));
599 if (dst_bits
== 64) {
600 if (is_signed
&& dst
.regClass() == s2
) {
601 Temp high
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(31u));
602 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
603 } else if (is_signed
&& dst
.regClass() == v2
) {
604 Temp high
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), tmp
);
605 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, high
);
607 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
614 enum sgpr_extract_mode
{
620 Temp
extract_8_16_bit_sgpr_element(isel_context
*ctx
, Temp dst
, nir_alu_src
*src
, sgpr_extract_mode mode
)
622 Temp vec
= get_ssa_temp(ctx
, src
->src
.ssa
);
623 unsigned src_size
= src
->src
.ssa
->bit_size
;
624 unsigned swizzle
= src
->swizzle
[0];
626 if (vec
.size() > 1) {
627 assert(src_size
== 16);
628 vec
= emit_extract_vector(ctx
, vec
, swizzle
/ 2, s1
);
629 swizzle
= swizzle
& 1;
632 Builder
bld(ctx
->program
, ctx
->block
);
633 unsigned offset
= src_size
* swizzle
;
634 Temp tmp
= dst
.regClass() == s2
? bld
.tmp(s1
) : dst
;
636 if (mode
== sgpr_extract_undef
&& swizzle
== 0) {
637 bld
.copy(Definition(tmp
), vec
);
638 } else if (mode
== sgpr_extract_undef
|| (offset
== 24 && mode
== sgpr_extract_zext
)) {
639 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(tmp
), bld
.def(s1
, scc
), vec
, Operand(offset
));
640 } else if (src_size
== 8 && swizzle
== 0 && mode
== sgpr_extract_sext
) {
641 bld
.sop1(aco_opcode::s_sext_i32_i8
, Definition(tmp
), vec
);
642 } else if (src_size
== 16 && swizzle
== 0 && mode
== sgpr_extract_sext
) {
643 bld
.sop1(aco_opcode::s_sext_i32_i16
, Definition(tmp
), vec
);
645 aco_opcode op
= mode
== sgpr_extract_zext
? aco_opcode::s_bfe_u32
: aco_opcode::s_bfe_i32
;
646 bld
.sop2(op
, Definition(tmp
), bld
.def(s1
, scc
), vec
, Operand((src_size
<< 16) | offset
));
649 if (dst
.regClass() == s2
)
650 convert_int(ctx
, bld
, tmp
, 32, 64, mode
== sgpr_extract_sext
, dst
);
655 Temp
get_alu_src(struct isel_context
*ctx
, nir_alu_src src
, unsigned size
=1)
657 if (src
.src
.ssa
->num_components
== 1 && src
.swizzle
[0] == 0 && size
== 1)
658 return get_ssa_temp(ctx
, src
.src
.ssa
);
660 if (src
.src
.ssa
->num_components
== size
) {
661 bool identity_swizzle
= true;
662 for (unsigned i
= 0; identity_swizzle
&& i
< size
; i
++) {
663 if (src
.swizzle
[i
] != i
)
664 identity_swizzle
= false;
666 if (identity_swizzle
)
667 return get_ssa_temp(ctx
, src
.src
.ssa
);
670 Temp vec
= get_ssa_temp(ctx
, src
.src
.ssa
);
671 unsigned elem_size
= vec
.bytes() / src
.src
.ssa
->num_components
;
672 assert(elem_size
> 0);
673 assert(vec
.bytes() % elem_size
== 0);
675 if (elem_size
< 4 && vec
.type() == RegType::sgpr
) {
676 assert(src
.src
.ssa
->bit_size
== 8 || src
.src
.ssa
->bit_size
== 16);
678 return extract_8_16_bit_sgpr_element(
679 ctx
, Temp(ctx
->program
->allocateId(), s1
), &src
, sgpr_extract_undef
);
682 RegClass elem_rc
= elem_size
< 4 ? RegClass(vec
.type(), elem_size
).as_subdword() : RegClass(vec
.type(), elem_size
/ 4);
684 return emit_extract_vector(ctx
, vec
, src
.swizzle
[0], elem_rc
);
687 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
688 aco_ptr
<Pseudo_instruction
> vec_instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, size
, 1)};
689 for (unsigned i
= 0; i
< size
; ++i
) {
690 elems
[i
] = emit_extract_vector(ctx
, vec
, src
.swizzle
[i
], elem_rc
);
691 vec_instr
->operands
[i
] = Operand
{elems
[i
]};
693 Temp dst
{ctx
->program
->allocateId(), RegClass(vec
.type(), elem_size
* size
/ 4)};
694 vec_instr
->definitions
[0] = Definition(dst
);
695 ctx
->block
->instructions
.emplace_back(std::move(vec_instr
));
696 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
701 Temp
convert_pointer_to_64_bit(isel_context
*ctx
, Temp ptr
)
705 Builder
bld(ctx
->program
, ctx
->block
);
706 if (ptr
.type() == RegType::vgpr
)
707 ptr
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), ptr
);
708 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
),
709 ptr
, Operand((unsigned)ctx
->options
->address32_hi
));
712 void emit_sop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
, bool writes_scc
)
714 aco_ptr
<SOP2_instruction
> sop2
{create_instruction
<SOP2_instruction
>(op
, Format::SOP2
, 2, writes_scc
? 2 : 1)};
715 sop2
->operands
[0] = Operand(get_alu_src(ctx
, instr
->src
[0]));
716 sop2
->operands
[1] = Operand(get_alu_src(ctx
, instr
->src
[1]));
717 sop2
->definitions
[0] = Definition(dst
);
718 if (instr
->no_unsigned_wrap
)
719 sop2
->definitions
[0].setNUW(true);
721 sop2
->definitions
[1] = Definition(ctx
->program
->allocateId(), scc
, s1
);
722 ctx
->block
->instructions
.emplace_back(std::move(sop2
));
725 void emit_vop2_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
726 bool commutative
, bool swap_srcs
=false, bool flush_denorms
= false)
728 Builder
bld(ctx
->program
, ctx
->block
);
729 bld
.is_precise
= instr
->exact
;
731 Temp src0
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 1 : 0]);
732 Temp src1
= get_alu_src(ctx
, instr
->src
[swap_srcs
? 0 : 1]);
733 if (src1
.type() == RegType::sgpr
) {
734 if (commutative
&& src0
.type() == RegType::vgpr
) {
739 src1
= as_vgpr(ctx
, src1
);
743 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
744 assert(dst
.size() == 1);
745 Temp tmp
= bld
.vop2(op
, bld
.def(v1
), src0
, src1
);
746 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
748 bld
.vop2(op
, Definition(dst
), src0
, src1
);
752 void emit_vop2_instruction_logic64(isel_context
*ctx
, nir_alu_instr
*instr
,
753 aco_opcode op
, Temp dst
)
755 Builder
bld(ctx
->program
, ctx
->block
);
756 bld
.is_precise
= instr
->exact
;
758 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
759 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
761 if (src1
.type() == RegType::sgpr
) {
762 assert(src0
.type() == RegType::vgpr
);
763 std::swap(src0
, src1
);
766 Temp src00
= bld
.tmp(src0
.type(), 1);
767 Temp src01
= bld
.tmp(src0
.type(), 1);
768 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
769 Temp src10
= bld
.tmp(v1
);
770 Temp src11
= bld
.tmp(v1
);
771 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
772 Temp lo
= bld
.vop2(op
, bld
.def(v1
), src00
, src10
);
773 Temp hi
= bld
.vop2(op
, bld
.def(v1
), src01
, src11
);
774 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
777 void emit_vop3a_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
,
778 bool flush_denorms
= false)
780 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
781 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
782 Temp src2
= get_alu_src(ctx
, instr
->src
[2]);
784 /* ensure that the instruction has at most 1 sgpr operand
785 * The optimizer will inline constants for us */
786 if (src0
.type() == RegType::sgpr
&& src1
.type() == RegType::sgpr
)
787 src0
= as_vgpr(ctx
, src0
);
788 if (src1
.type() == RegType::sgpr
&& src2
.type() == RegType::sgpr
)
789 src1
= as_vgpr(ctx
, src1
);
790 if (src2
.type() == RegType::sgpr
&& src0
.type() == RegType::sgpr
)
791 src2
= as_vgpr(ctx
, src2
);
793 Builder
bld(ctx
->program
, ctx
->block
);
794 bld
.is_precise
= instr
->exact
;
795 if (flush_denorms
&& ctx
->program
->chip_class
< GFX9
) {
796 assert(dst
.size() == 1);
797 Temp tmp
= bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
798 bld
.vop2(aco_opcode::v_mul_f32
, Definition(dst
), Operand(0x3f800000u
), tmp
);
800 bld
.vop3(op
, Definition(dst
), src0
, src1
, src2
);
804 void emit_vop1_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
806 Builder
bld(ctx
->program
, ctx
->block
);
807 bld
.is_precise
= instr
->exact
;
808 if (dst
.type() == RegType::sgpr
)
809 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
810 bld
.vop1(op
, bld
.def(RegType::vgpr
, dst
.size()), get_alu_src(ctx
, instr
->src
[0])));
812 bld
.vop1(op
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
815 void emit_vopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
817 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
818 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
819 assert(src0
.size() == src1
.size());
821 aco_ptr
<Instruction
> vopc
;
822 if (src1
.type() == RegType::sgpr
) {
823 if (src0
.type() == RegType::vgpr
) {
824 /* to swap the operands, we might also have to change the opcode */
826 case aco_opcode::v_cmp_lt_f16
:
827 op
= aco_opcode::v_cmp_gt_f16
;
829 case aco_opcode::v_cmp_ge_f16
:
830 op
= aco_opcode::v_cmp_le_f16
;
832 case aco_opcode::v_cmp_lt_i16
:
833 op
= aco_opcode::v_cmp_gt_i16
;
835 case aco_opcode::v_cmp_ge_i16
:
836 op
= aco_opcode::v_cmp_le_i16
;
838 case aco_opcode::v_cmp_lt_u16
:
839 op
= aco_opcode::v_cmp_gt_u16
;
841 case aco_opcode::v_cmp_ge_u16
:
842 op
= aco_opcode::v_cmp_le_u16
;
844 case aco_opcode::v_cmp_lt_f32
:
845 op
= aco_opcode::v_cmp_gt_f32
;
847 case aco_opcode::v_cmp_ge_f32
:
848 op
= aco_opcode::v_cmp_le_f32
;
850 case aco_opcode::v_cmp_lt_i32
:
851 op
= aco_opcode::v_cmp_gt_i32
;
853 case aco_opcode::v_cmp_ge_i32
:
854 op
= aco_opcode::v_cmp_le_i32
;
856 case aco_opcode::v_cmp_lt_u32
:
857 op
= aco_opcode::v_cmp_gt_u32
;
859 case aco_opcode::v_cmp_ge_u32
:
860 op
= aco_opcode::v_cmp_le_u32
;
862 case aco_opcode::v_cmp_lt_f64
:
863 op
= aco_opcode::v_cmp_gt_f64
;
865 case aco_opcode::v_cmp_ge_f64
:
866 op
= aco_opcode::v_cmp_le_f64
;
868 case aco_opcode::v_cmp_lt_i64
:
869 op
= aco_opcode::v_cmp_gt_i64
;
871 case aco_opcode::v_cmp_ge_i64
:
872 op
= aco_opcode::v_cmp_le_i64
;
874 case aco_opcode::v_cmp_lt_u64
:
875 op
= aco_opcode::v_cmp_gt_u64
;
877 case aco_opcode::v_cmp_ge_u64
:
878 op
= aco_opcode::v_cmp_le_u64
;
880 default: /* eq and ne are commutative */
887 src1
= as_vgpr(ctx
, src1
);
891 Builder
bld(ctx
->program
, ctx
->block
);
892 bld
.vopc(op
, bld
.hint_vcc(Definition(dst
)), src0
, src1
);
895 void emit_sopc_instruction(isel_context
*ctx
, nir_alu_instr
*instr
, aco_opcode op
, Temp dst
)
897 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
898 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
899 Builder
bld(ctx
->program
, ctx
->block
);
901 assert(dst
.regClass() == bld
.lm
);
902 assert(src0
.type() == RegType::sgpr
);
903 assert(src1
.type() == RegType::sgpr
);
904 assert(src0
.regClass() == src1
.regClass());
906 /* Emit the SALU comparison instruction */
907 Temp cmp
= bld
.sopc(op
, bld
.scc(bld
.def(s1
)), src0
, src1
);
908 /* Turn the result into a per-lane bool */
909 bool_to_vector_condition(ctx
, cmp
, dst
);
912 void emit_comparison(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
,
913 aco_opcode v16_op
, aco_opcode v32_op
, aco_opcode v64_op
, aco_opcode s32_op
= aco_opcode::num_opcodes
, aco_opcode s64_op
= aco_opcode::num_opcodes
)
915 aco_opcode s_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? s64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? s32_op
: aco_opcode::num_opcodes
;
916 aco_opcode v_op
= instr
->src
[0].src
.ssa
->bit_size
== 64 ? v64_op
: instr
->src
[0].src
.ssa
->bit_size
== 32 ? v32_op
: v16_op
;
917 bool use_valu
= s_op
== aco_opcode::num_opcodes
||
918 nir_dest_is_divergent(instr
->dest
.dest
) ||
919 ctx
->allocated
[instr
->src
[0].src
.ssa
->index
].type() == RegType::vgpr
||
920 ctx
->allocated
[instr
->src
[1].src
.ssa
->index
].type() == RegType::vgpr
;
921 aco_opcode op
= use_valu
? v_op
: s_op
;
922 assert(op
!= aco_opcode::num_opcodes
);
923 assert(dst
.regClass() == ctx
->program
->lane_mask
);
926 emit_vopc_instruction(ctx
, instr
, op
, dst
);
928 emit_sopc_instruction(ctx
, instr
, op
, dst
);
931 void emit_boolean_logic(isel_context
*ctx
, nir_alu_instr
*instr
, Builder::WaveSpecificOpcode op
, Temp dst
)
933 Builder
bld(ctx
->program
, ctx
->block
);
934 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
935 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
937 assert(dst
.regClass() == bld
.lm
);
938 assert(src0
.regClass() == bld
.lm
);
939 assert(src1
.regClass() == bld
.lm
);
941 bld
.sop2(op
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
944 void emit_bcsel(isel_context
*ctx
, nir_alu_instr
*instr
, Temp dst
)
946 Builder
bld(ctx
->program
, ctx
->block
);
947 Temp cond
= get_alu_src(ctx
, instr
->src
[0]);
948 Temp then
= get_alu_src(ctx
, instr
->src
[1]);
949 Temp els
= get_alu_src(ctx
, instr
->src
[2]);
951 assert(cond
.regClass() == bld
.lm
);
953 if (dst
.type() == RegType::vgpr
) {
954 aco_ptr
<Instruction
> bcsel
;
955 if (dst
.size() == 1) {
956 then
= as_vgpr(ctx
, then
);
957 els
= as_vgpr(ctx
, els
);
959 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), els
, then
, cond
);
960 } else if (dst
.size() == 2) {
961 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
962 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), then
);
963 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
964 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), els
);
966 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, cond
);
967 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, cond
);
969 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
971 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
976 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
977 assert(dst
.regClass() == bld
.lm
);
978 assert(then
.regClass() == bld
.lm
);
979 assert(els
.regClass() == bld
.lm
);
982 if (!nir_src_is_divergent(instr
->src
[0].src
)) { /* uniform condition and values in sgpr */
983 if (dst
.regClass() == s1
|| dst
.regClass() == s2
) {
984 assert((then
.regClass() == s1
|| then
.regClass() == s2
) && els
.regClass() == then
.regClass());
985 assert(dst
.size() == then
.size());
986 aco_opcode op
= dst
.regClass() == s1
? aco_opcode::s_cselect_b32
: aco_opcode::s_cselect_b64
;
987 bld
.sop2(op
, Definition(dst
), then
, els
, bld
.scc(bool_to_scalar_condition(ctx
, cond
)));
989 isel_err(&instr
->instr
, "Unimplemented uniform bcsel bit size");
994 /* divergent boolean bcsel
995 * this implements bcsel on bools: dst = s0 ? s1 : s2
996 * are going to be: dst = (s0 & s1) | (~s0 & s2) */
997 assert(instr
->dest
.dest
.ssa
.bit_size
== 1);
999 if (cond
.id() != then
.id())
1000 then
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
, then
);
1002 if (cond
.id() == els
.id())
1003 bld
.sop1(Builder::s_mov
, Definition(dst
), then
);
1005 bld
.sop2(Builder::s_or
, Definition(dst
), bld
.def(s1
, scc
), then
,
1006 bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), els
, cond
));
1009 void emit_scaled_op(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
,
1010 aco_opcode op
, uint32_t undo
)
1012 /* multiply by 16777216 to handle denormals */
1013 Temp is_denormal
= bld
.vopc(aco_opcode::v_cmp_class_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
1014 as_vgpr(ctx
, val
), bld
.copy(bld
.def(v1
), Operand((1u << 7) | (1u << 4))));
1015 Temp scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x4b800000u
), val
);
1016 scaled
= bld
.vop1(op
, bld
.def(v1
), scaled
);
1017 scaled
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(undo
), scaled
);
1019 Temp not_scaled
= bld
.vop1(op
, bld
.def(v1
), val
);
1021 bld
.vop2(aco_opcode::v_cndmask_b32
, dst
, not_scaled
, scaled
, is_denormal
);
1024 void emit_rcp(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1026 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1027 bld
.vop1(aco_opcode::v_rcp_f32
, dst
, val
);
1031 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rcp_f32
, 0x4b800000u
);
1034 void emit_rsq(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1036 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1037 bld
.vop1(aco_opcode::v_rsq_f32
, dst
, val
);
1041 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_rsq_f32
, 0x45800000u
);
1044 void emit_sqrt(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1046 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1047 bld
.vop1(aco_opcode::v_sqrt_f32
, dst
, val
);
1051 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_sqrt_f32
, 0x39800000u
);
1054 void emit_log2(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1056 if (ctx
->block
->fp_mode
.denorm32
== 0) {
1057 bld
.vop1(aco_opcode::v_log_f32
, dst
, val
);
1061 emit_scaled_op(ctx
, bld
, dst
, val
, aco_opcode::v_log_f32
, 0xc1c00000u
);
1064 Temp
emit_trunc_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1066 if (ctx
->options
->chip_class
>= GFX7
)
1067 return bld
.vop1(aco_opcode::v_trunc_f64
, Definition(dst
), val
);
1069 /* GFX6 doesn't support V_TRUNC_F64, lower it. */
1070 /* TODO: create more efficient code! */
1071 if (val
.type() == RegType::sgpr
)
1072 val
= as_vgpr(ctx
, val
);
1074 /* Split the input value. */
1075 Temp val_lo
= bld
.tmp(v1
), val_hi
= bld
.tmp(v1
);
1076 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
1078 /* Extract the exponent and compute the unbiased value. */
1079 Temp exponent
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), val_hi
, Operand(20u), Operand(11u));
1080 exponent
= bld
.vsub32(bld
.def(v1
), exponent
, Operand(1023u));
1082 /* Extract the fractional part. */
1083 Temp fract_mask
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x000fffffu
));
1084 fract_mask
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), fract_mask
, exponent
);
1086 Temp fract_mask_lo
= bld
.tmp(v1
), fract_mask_hi
= bld
.tmp(v1
);
1087 bld
.pseudo(aco_opcode::p_split_vector
, Definition(fract_mask_lo
), Definition(fract_mask_hi
), fract_mask
);
1089 Temp fract_lo
= bld
.tmp(v1
), fract_hi
= bld
.tmp(v1
);
1090 Temp tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_lo
);
1091 fract_lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_lo
, tmp
);
1092 tmp
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), fract_mask_hi
);
1093 fract_hi
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), val_hi
, tmp
);
1095 /* Get the sign bit. */
1096 Temp sign
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x80000000u
), val_hi
);
1098 /* Decide the operation to apply depending on the unbiased exponent. */
1099 Temp exp_lt0
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), exponent
, Operand(0u));
1100 Temp dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_lo
, bld
.copy(bld
.def(v1
), Operand(0u)), exp_lt0
);
1101 Temp dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), fract_hi
, sign
, exp_lt0
);
1102 Temp exp_gt51
= bld
.vopc_e64(aco_opcode::v_cmp_gt_i32
, bld
.def(s2
), exponent
, Operand(51u));
1103 dst_lo
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_lo
, val_lo
, exp_gt51
);
1104 dst_hi
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), dst_hi
, val_hi
, exp_gt51
);
1106 return bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst_lo
, dst_hi
);
1109 Temp
emit_floor_f64(isel_context
*ctx
, Builder
& bld
, Definition dst
, Temp val
)
1111 if (ctx
->options
->chip_class
>= GFX7
)
1112 return bld
.vop1(aco_opcode::v_floor_f64
, Definition(dst
), val
);
1114 /* GFX6 doesn't support V_FLOOR_F64, lower it (note that it's actually
1115 * lowered at NIR level for precision reasons). */
1116 Temp src0
= as_vgpr(ctx
, val
);
1118 Temp mask
= bld
.copy(bld
.def(s1
), Operand(3u)); /* isnan */
1119 Temp min_val
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(-1u), Operand(0x3fefffffu
));
1121 Temp isnan
= bld
.vopc_e64(aco_opcode::v_cmp_class_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, mask
);
1122 Temp fract
= bld
.vop1(aco_opcode::v_fract_f64
, bld
.def(v2
), src0
);
1123 Temp min
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), fract
, min_val
);
1125 Temp then_lo
= bld
.tmp(v1
), then_hi
= bld
.tmp(v1
);
1126 bld
.pseudo(aco_opcode::p_split_vector
, Definition(then_lo
), Definition(then_hi
), src0
);
1127 Temp else_lo
= bld
.tmp(v1
), else_hi
= bld
.tmp(v1
);
1128 bld
.pseudo(aco_opcode::p_split_vector
, Definition(else_lo
), Definition(else_hi
), min
);
1130 Temp dst0
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_lo
, then_lo
, isnan
);
1131 Temp dst1
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), else_hi
, then_hi
, isnan
);
1133 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), dst0
, dst1
);
1135 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, v
);
1136 static_cast<VOP3A_instruction
*>(add
)->neg
[1] = true;
1138 return add
->definitions
[0].getTemp();
1141 void visit_alu_instr(isel_context
*ctx
, nir_alu_instr
*instr
)
1143 if (!instr
->dest
.dest
.is_ssa
) {
1144 isel_err(&instr
->instr
, "nir alu dst not in ssa");
1147 Builder
bld(ctx
->program
, ctx
->block
);
1148 bld
.is_precise
= instr
->exact
;
1149 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.dest
.ssa
);
1154 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
1155 unsigned num
= instr
->dest
.dest
.ssa
.num_components
;
1156 for (unsigned i
= 0; i
< num
; ++i
)
1157 elems
[i
] = get_alu_src(ctx
, instr
->src
[i
]);
1159 if (instr
->dest
.dest
.ssa
.bit_size
>= 32 || dst
.type() == RegType::vgpr
) {
1160 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.dest
.ssa
.num_components
, 1)};
1161 RegClass elem_rc
= RegClass::get(RegType::vgpr
, instr
->dest
.dest
.ssa
.bit_size
/ 8u);
1162 for (unsigned i
= 0; i
< num
; ++i
) {
1163 if (elems
[i
].type() == RegType::sgpr
&& elem_rc
.is_subdword())
1164 vec
->operands
[i
] = Operand(emit_extract_vector(ctx
, elems
[i
], 0, elem_rc
));
1166 vec
->operands
[i
] = Operand
{elems
[i
]};
1168 vec
->definitions
[0] = Definition(dst
);
1169 ctx
->block
->instructions
.emplace_back(std::move(vec
));
1170 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
1172 // TODO: that is a bit suboptimal..
1173 Temp mask
= bld
.copy(bld
.def(s1
), Operand((1u << instr
->dest
.dest
.ssa
.bit_size
) - 1));
1174 for (unsigned i
= 0; i
< num
- 1; ++i
)
1175 if (((i
+1) * instr
->dest
.dest
.ssa
.bit_size
) % 32)
1176 elems
[i
] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[i
], mask
);
1177 for (unsigned i
= 0; i
< num
; ++i
) {
1178 unsigned bit
= i
* instr
->dest
.dest
.ssa
.bit_size
;
1179 if (bit
% 32 == 0) {
1180 elems
[bit
/ 32] = elems
[i
];
1182 elems
[i
] = bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
1183 elems
[i
], Operand((i
* instr
->dest
.dest
.ssa
.bit_size
) % 32));
1184 elems
[bit
/ 32] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), elems
[bit
/ 32], elems
[i
]);
1187 if (dst
.size() == 1)
1188 bld
.copy(Definition(dst
), elems
[0]);
1190 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), elems
[0], elems
[1]);
1195 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1196 aco_ptr
<Instruction
> mov
;
1197 if (dst
.type() == RegType::sgpr
) {
1198 if (src
.type() == RegType::vgpr
)
1199 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), src
);
1200 else if (src
.regClass() == s1
)
1201 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
1202 else if (src
.regClass() == s2
)
1203 bld
.sop1(aco_opcode::s_mov_b64
, Definition(dst
), src
);
1205 unreachable("wrong src register class for nir_op_imov");
1207 if (dst
.regClass() == v1
)
1208 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), src
);
1209 else if (dst
.regClass() == v1b
||
1210 dst
.regClass() == v2b
||
1211 dst
.regClass() == v2
)
1212 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
1214 unreachable("wrong src register class for nir_op_imov");
1219 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1220 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1221 assert(src
.regClass() == bld
.lm
);
1222 assert(dst
.regClass() == bld
.lm
);
1223 /* Don't use s_andn2 here, this allows the optimizer to make a better decision */
1224 Temp tmp
= bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
);
1225 bld
.sop2(Builder::s_and
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(exec
, bld
.lm
));
1226 } else if (dst
.regClass() == v1
) {
1227 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_not_b32
, dst
);
1228 } else if (dst
.regClass() == v2
) {
1229 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
1230 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
1231 lo
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), lo
);
1232 hi
= bld
.vop1(aco_opcode::v_not_b32
, bld
.def(v1
), hi
);
1233 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
1234 } else if (dst
.type() == RegType::sgpr
) {
1235 aco_opcode opcode
= dst
.size() == 1 ? aco_opcode::s_not_b32
: aco_opcode::s_not_b64
;
1236 bld
.sop1(opcode
, Definition(dst
), bld
.def(s1
, scc
), src
);
1238 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1243 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1244 if (dst
.regClass() == v1
) {
1245 bld
.vsub32(Definition(dst
), Operand(0u), Operand(src
));
1246 } else if (dst
.regClass() == s1
) {
1247 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand((uint32_t) -1), src
);
1248 } else if (dst
.size() == 2) {
1249 Temp src0
= bld
.tmp(dst
.type(), 1);
1250 Temp src1
= bld
.tmp(dst
.type(), 1);
1251 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
1253 if (dst
.regClass() == s2
) {
1254 Temp carry
= bld
.tmp(s1
);
1255 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), Operand(0u), src0
);
1256 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), src1
, carry
);
1257 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1259 Temp lower
= bld
.tmp(v1
);
1260 Temp borrow
= bld
.vsub32(Definition(lower
), Operand(0u), src0
, true).def(1).getTemp();
1261 Temp upper
= bld
.vsub32(bld
.def(v1
), Operand(0u), src1
, false, borrow
);
1262 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1265 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1270 if (dst
.regClass() == s1
) {
1271 bld
.sop1(aco_opcode::s_abs_i32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]));
1272 } else if (dst
.regClass() == v1
) {
1273 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1274 bld
.vop2(aco_opcode::v_max_i32
, Definition(dst
), src
, bld
.vsub32(bld
.def(v1
), Operand(0u), src
));
1276 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1280 case nir_op_isign
: {
1281 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1282 if (dst
.regClass() == s1
) {
1283 Temp tmp
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand((uint32_t)-1));
1284 bld
.sop2(aco_opcode::s_min_i32
, Definition(dst
), bld
.def(s1
, scc
), tmp
, Operand(1u));
1285 } else if (dst
.regClass() == s2
) {
1286 Temp neg
= bld
.sop2(aco_opcode::s_ashr_i64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(63u));
1288 if (ctx
->program
->chip_class
>= GFX8
)
1289 neqz
= bld
.sopc(aco_opcode::s_cmp_lg_u64
, bld
.def(s1
, scc
), src
, Operand(0u));
1291 neqz
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(0u)).def(1).getTemp();
1292 /* SCC gets zero-extended to 64 bit */
1293 bld
.sop2(aco_opcode::s_or_b64
, Definition(dst
), bld
.def(s1
, scc
), neg
, bld
.scc(neqz
));
1294 } else if (dst
.regClass() == v1
) {
1295 bld
.vop3(aco_opcode::v_med3_i32
, Definition(dst
), Operand((uint32_t)-1), src
, Operand(1u));
1296 } else if (dst
.regClass() == v2
) {
1297 Temp upper
= emit_extract_vector(ctx
, src
, 1, v1
);
1298 Temp neg
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), upper
);
1299 Temp gtz
= bld
.vopc(aco_opcode::v_cmp_ge_i64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
1300 Temp lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(1u), neg
, gtz
);
1301 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), neg
, gtz
);
1302 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1304 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1309 if (dst
.regClass() == v1
) {
1310 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_i32
, dst
, true);
1311 } else if (dst
.regClass() == s1
) {
1312 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_i32
, dst
, true);
1314 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1319 if (dst
.regClass() == v1
) {
1320 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_u32
, dst
, true);
1321 } else if (dst
.regClass() == s1
) {
1322 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_max_u32
, dst
, true);
1324 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1329 if (dst
.regClass() == v1
) {
1330 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_i32
, dst
, true);
1331 } else if (dst
.regClass() == s1
) {
1332 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_i32
, dst
, true);
1334 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1339 if (dst
.regClass() == v1
) {
1340 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_u32
, dst
, true);
1341 } else if (dst
.regClass() == s1
) {
1342 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_min_u32
, dst
, true);
1344 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1349 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1350 emit_boolean_logic(ctx
, instr
, Builder::s_or
, dst
);
1351 } else if (dst
.regClass() == v1
) {
1352 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_or_b32
, dst
, true);
1353 } else if (dst
.regClass() == v2
) {
1354 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_or_b32
, dst
);
1355 } else if (dst
.regClass() == s1
) {
1356 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b32
, dst
, true);
1357 } else if (dst
.regClass() == s2
) {
1358 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_or_b64
, dst
, true);
1360 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1365 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1366 emit_boolean_logic(ctx
, instr
, Builder::s_and
, dst
);
1367 } else if (dst
.regClass() == v1
) {
1368 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_and_b32
, dst
, true);
1369 } else if (dst
.regClass() == v2
) {
1370 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_and_b32
, dst
);
1371 } else if (dst
.regClass() == s1
) {
1372 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b32
, dst
, true);
1373 } else if (dst
.regClass() == s2
) {
1374 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_and_b64
, dst
, true);
1376 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1381 if (instr
->dest
.dest
.ssa
.bit_size
== 1) {
1382 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
1383 } else if (dst
.regClass() == v1
) {
1384 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_xor_b32
, dst
, true);
1385 } else if (dst
.regClass() == v2
) {
1386 emit_vop2_instruction_logic64(ctx
, instr
, aco_opcode::v_xor_b32
, dst
);
1387 } else if (dst
.regClass() == s1
) {
1388 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b32
, dst
, true);
1389 } else if (dst
.regClass() == s2
) {
1390 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_xor_b64
, dst
, true);
1392 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1397 if (dst
.regClass() == v1
) {
1398 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshrrev_b32
, dst
, false, true);
1399 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1400 bld
.vop3(aco_opcode::v_lshrrev_b64
, Definition(dst
),
1401 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1402 } else if (dst
.regClass() == v2
) {
1403 bld
.vop3(aco_opcode::v_lshr_b64
, Definition(dst
),
1404 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1405 } else if (dst
.regClass() == s2
) {
1406 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b64
, dst
, true);
1407 } else if (dst
.regClass() == s1
) {
1408 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshr_b32
, dst
, true);
1410 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1415 if (dst
.regClass() == v1
) {
1416 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_lshlrev_b32
, dst
, false, true);
1417 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1418 bld
.vop3(aco_opcode::v_lshlrev_b64
, Definition(dst
),
1419 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1420 } else if (dst
.regClass() == v2
) {
1421 bld
.vop3(aco_opcode::v_lshl_b64
, Definition(dst
),
1422 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1423 } else if (dst
.regClass() == s1
) {
1424 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b32
, dst
, true);
1425 } else if (dst
.regClass() == s2
) {
1426 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_lshl_b64
, dst
, true);
1428 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1433 if (dst
.regClass() == v1
) {
1434 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ashrrev_i32
, dst
, false, true);
1435 } else if (dst
.regClass() == v2
&& ctx
->program
->chip_class
>= GFX8
) {
1436 bld
.vop3(aco_opcode::v_ashrrev_i64
, Definition(dst
),
1437 get_alu_src(ctx
, instr
->src
[1]), get_alu_src(ctx
, instr
->src
[0]));
1438 } else if (dst
.regClass() == v2
) {
1439 bld
.vop3(aco_opcode::v_ashr_i64
, Definition(dst
),
1440 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1441 } else if (dst
.regClass() == s1
) {
1442 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i32
, dst
, true);
1443 } else if (dst
.regClass() == s2
) {
1444 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_ashr_i64
, dst
, true);
1446 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1450 case nir_op_find_lsb
: {
1451 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1452 if (src
.regClass() == s1
) {
1453 bld
.sop1(aco_opcode::s_ff1_i32_b32
, Definition(dst
), src
);
1454 } else if (src
.regClass() == v1
) {
1455 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ffbl_b32
, dst
);
1456 } else if (src
.regClass() == s2
) {
1457 bld
.sop1(aco_opcode::s_ff1_i32_b64
, Definition(dst
), src
);
1459 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1463 case nir_op_ufind_msb
:
1464 case nir_op_ifind_msb
: {
1465 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1466 if (src
.regClass() == s1
|| src
.regClass() == s2
) {
1467 aco_opcode op
= src
.regClass() == s2
?
1468 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b64
: aco_opcode::s_flbit_i32_i64
) :
1469 (instr
->op
== nir_op_ufind_msb
? aco_opcode::s_flbit_i32_b32
: aco_opcode::s_flbit_i32
);
1470 Temp msb_rev
= bld
.sop1(op
, bld
.def(s1
), src
);
1472 Builder::Result sub
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
1473 Operand(src
.size() * 32u - 1u), msb_rev
);
1474 Temp msb
= sub
.def(0).getTemp();
1475 Temp carry
= sub
.def(1).getTemp();
1477 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t)-1), msb
, bld
.scc(carry
));
1478 } else if (src
.regClass() == v1
) {
1479 aco_opcode op
= instr
->op
== nir_op_ufind_msb
? aco_opcode::v_ffbh_u32
: aco_opcode::v_ffbh_i32
;
1480 Temp msb_rev
= bld
.tmp(v1
);
1481 emit_vop1_instruction(ctx
, instr
, op
, msb_rev
);
1482 Temp msb
= bld
.tmp(v1
);
1483 Temp carry
= bld
.vsub32(Definition(msb
), Operand(31u), Operand(msb_rev
), true).def(1).getTemp();
1484 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), msb
, Operand((uint32_t)-1), carry
);
1486 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1490 case nir_op_bitfield_reverse
: {
1491 if (dst
.regClass() == s1
) {
1492 bld
.sop1(aco_opcode::s_brev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1493 } else if (dst
.regClass() == v1
) {
1494 bld
.vop1(aco_opcode::v_bfrev_b32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
1496 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1501 if (dst
.regClass() == s1
) {
1502 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_add_u32
, dst
, true);
1506 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1507 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1508 if (dst
.regClass() == v1
) {
1509 bld
.vadd32(Definition(dst
), Operand(src0
), Operand(src1
));
1513 assert(src0
.size() == 2 && src1
.size() == 2);
1514 Temp src00
= bld
.tmp(src0
.type(), 1);
1515 Temp src01
= bld
.tmp(dst
.type(), 1);
1516 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1517 Temp src10
= bld
.tmp(src1
.type(), 1);
1518 Temp src11
= bld
.tmp(dst
.type(), 1);
1519 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1521 if (dst
.regClass() == s2
) {
1522 Temp carry
= bld
.tmp(s1
);
1523 Temp dst0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1524 Temp dst1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, bld
.scc(carry
));
1525 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1526 } else if (dst
.regClass() == v2
) {
1527 Temp dst0
= bld
.tmp(v1
);
1528 Temp carry
= bld
.vadd32(Definition(dst0
), src00
, src10
, true).def(1).getTemp();
1529 Temp dst1
= bld
.vadd32(bld
.def(v1
), src01
, src11
, false, carry
);
1530 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1532 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1536 case nir_op_uadd_sat
: {
1537 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1538 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1539 if (dst
.regClass() == s1
) {
1540 Temp tmp
= bld
.tmp(s1
), carry
= bld
.tmp(s1
);
1541 bld
.sop2(aco_opcode::s_add_u32
, Definition(tmp
), bld
.scc(Definition(carry
)),
1543 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(dst
), Operand((uint32_t) -1), tmp
, bld
.scc(carry
));
1544 } else if (dst
.regClass() == v1
) {
1545 if (ctx
->options
->chip_class
>= GFX9
) {
1546 aco_ptr
<VOP3A_instruction
> add
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_add_u32
, asVOP3(Format::VOP2
), 2, 1)};
1547 add
->operands
[0] = Operand(src0
);
1548 add
->operands
[1] = Operand(src1
);
1549 add
->definitions
[0] = Definition(dst
);
1551 ctx
->block
->instructions
.emplace_back(std::move(add
));
1553 if (src1
.regClass() != v1
)
1554 std::swap(src0
, src1
);
1555 assert(src1
.regClass() == v1
);
1556 Temp tmp
= bld
.tmp(v1
);
1557 Temp carry
= bld
.vadd32(Definition(tmp
), src0
, src1
, true).def(1).getTemp();
1558 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), tmp
, Operand((uint32_t) -1), carry
);
1561 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1565 case nir_op_uadd_carry
: {
1566 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1567 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1568 if (dst
.regClass() == s1
) {
1569 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1572 if (dst
.regClass() == v1
) {
1573 Temp carry
= bld
.vadd32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1574 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), carry
);
1578 Temp src00
= bld
.tmp(src0
.type(), 1);
1579 Temp src01
= bld
.tmp(dst
.type(), 1);
1580 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1581 Temp src10
= bld
.tmp(src1
.type(), 1);
1582 Temp src11
= bld
.tmp(dst
.type(), 1);
1583 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1584 if (dst
.regClass() == s2
) {
1585 Temp carry
= bld
.tmp(s1
);
1586 bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1587 carry
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(carry
)).def(1).getTemp();
1588 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1589 } else if (dst
.regClass() == v2
) {
1590 Temp carry
= bld
.vadd32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1591 carry
= bld
.vadd32(bld
.def(v1
), src01
, src11
, true, carry
).def(1).getTemp();
1592 carry
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), carry
);
1593 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), carry
, Operand(0u));
1595 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1600 if (dst
.regClass() == s1
) {
1601 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_sub_i32
, dst
, true);
1605 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1606 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1607 if (dst
.regClass() == v1
) {
1608 bld
.vsub32(Definition(dst
), src0
, src1
);
1612 Temp src00
= bld
.tmp(src0
.type(), 1);
1613 Temp src01
= bld
.tmp(dst
.type(), 1);
1614 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1615 Temp src10
= bld
.tmp(src1
.type(), 1);
1616 Temp src11
= bld
.tmp(dst
.type(), 1);
1617 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1618 if (dst
.regClass() == s2
) {
1619 Temp carry
= bld
.tmp(s1
);
1620 Temp dst0
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), src00
, src10
);
1621 Temp dst1
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src01
, src11
, carry
);
1622 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
1623 } else if (dst
.regClass() == v2
) {
1624 Temp lower
= bld
.tmp(v1
);
1625 Temp borrow
= bld
.vsub32(Definition(lower
), src00
, src10
, true).def(1).getTemp();
1626 Temp upper
= bld
.vsub32(bld
.def(v1
), src01
, src11
, false, borrow
);
1627 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1629 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1633 case nir_op_usub_borrow
: {
1634 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1635 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1636 if (dst
.regClass() == s1
) {
1637 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(dst
)), src0
, src1
);
1639 } else if (dst
.regClass() == v1
) {
1640 Temp borrow
= bld
.vsub32(bld
.def(v1
), src0
, src1
, true).def(1).getTemp();
1641 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(1u), borrow
);
1645 Temp src00
= bld
.tmp(src0
.type(), 1);
1646 Temp src01
= bld
.tmp(dst
.type(), 1);
1647 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src00
), Definition(src01
), src0
);
1648 Temp src10
= bld
.tmp(src1
.type(), 1);
1649 Temp src11
= bld
.tmp(dst
.type(), 1);
1650 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src10
), Definition(src11
), src1
);
1651 if (dst
.regClass() == s2
) {
1652 Temp borrow
= bld
.tmp(s1
);
1653 bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), src00
, src10
);
1654 borrow
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.scc(bld
.def(s1
)), src01
, src11
, bld
.scc(borrow
)).def(1).getTemp();
1655 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1656 } else if (dst
.regClass() == v2
) {
1657 Temp borrow
= bld
.vsub32(bld
.def(v1
), src00
, src10
, true).def(1).getTemp();
1658 borrow
= bld
.vsub32(bld
.def(v1
), src01
, src11
, true, Operand(borrow
)).def(1).getTemp();
1659 borrow
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand(1u), borrow
);
1660 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), borrow
, Operand(0u));
1662 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1667 if (dst
.regClass() == v1
) {
1668 bld
.vop3(aco_opcode::v_mul_lo_u32
, Definition(dst
),
1669 get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1670 } else if (dst
.regClass() == s1
) {
1671 emit_sop2_instruction(ctx
, instr
, aco_opcode::s_mul_i32
, dst
, false);
1673 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1677 case nir_op_umul_high
: {
1678 if (dst
.regClass() == v1
) {
1679 bld
.vop3(aco_opcode::v_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1680 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1681 bld
.sop2(aco_opcode::s_mul_hi_u32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1682 } else if (dst
.regClass() == s1
) {
1683 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1684 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1685 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1687 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1691 case nir_op_imul_high
: {
1692 if (dst
.regClass() == v1
) {
1693 bld
.vop3(aco_opcode::v_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1694 } else if (dst
.regClass() == s1
&& ctx
->options
->chip_class
>= GFX9
) {
1695 bld
.sop2(aco_opcode::s_mul_hi_i32
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]), get_alu_src(ctx
, instr
->src
[1]));
1696 } else if (dst
.regClass() == s1
) {
1697 Temp tmp
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), get_alu_src(ctx
, instr
->src
[0]),
1698 as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1])));
1699 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
1701 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1706 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1707 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1708 if (dst
.regClass() == v2b
) {
1709 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f16
, dst
, true);
1710 } else if (dst
.regClass() == v1
) {
1711 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_mul_f32
, dst
, true);
1712 } else if (dst
.regClass() == v2
) {
1713 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), src0
, src1
);
1715 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1720 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1721 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1722 if (dst
.regClass() == v2b
) {
1723 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f16
, dst
, true);
1724 } else if (dst
.regClass() == v1
) {
1725 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_add_f32
, dst
, true);
1726 } else if (dst
.regClass() == v2
) {
1727 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src0
, src1
);
1729 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1734 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1735 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
1736 if (dst
.regClass() == v2b
) {
1737 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1738 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f16
, dst
, false);
1740 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f16
, dst
, true);
1741 } else if (dst
.regClass() == v1
) {
1742 if (src1
.type() == RegType::vgpr
|| src0
.type() != RegType::vgpr
)
1743 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_sub_f32
, dst
, false);
1745 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_subrev_f32
, dst
, true);
1746 } else if (dst
.regClass() == v2
) {
1747 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
),
1748 as_vgpr(ctx
, src0
), as_vgpr(ctx
, src1
));
1749 VOP3A_instruction
* sub
= static_cast<VOP3A_instruction
*>(add
);
1752 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1757 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1758 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1759 if (dst
.regClass() == v2b
) {
1760 // TODO: check fp_mode.must_flush_denorms16_64
1761 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f16
, dst
, true);
1762 } else if (dst
.regClass() == v1
) {
1763 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_max_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1764 } else if (dst
.regClass() == v2
) {
1765 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1766 Temp tmp
= bld
.vop3(aco_opcode::v_max_f64
, bld
.def(v2
), src0
, src1
);
1767 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1769 bld
.vop3(aco_opcode::v_max_f64
, Definition(dst
), src0
, src1
);
1772 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1777 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1778 Temp src1
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[1]));
1779 if (dst
.regClass() == v2b
) {
1780 // TODO: check fp_mode.must_flush_denorms16_64
1781 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f16
, dst
, true);
1782 } else if (dst
.regClass() == v1
) {
1783 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_min_f32
, dst
, true, false, ctx
->block
->fp_mode
.must_flush_denorms32
);
1784 } else if (dst
.regClass() == v2
) {
1785 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
&& ctx
->program
->chip_class
< GFX9
) {
1786 Temp tmp
= bld
.vop3(aco_opcode::v_min_f64
, bld
.def(v2
), src0
, src1
);
1787 bld
.vop3(aco_opcode::v_mul_f64
, Definition(dst
), Operand(0x3FF0000000000000lu
), tmp
);
1789 bld
.vop3(aco_opcode::v_min_f64
, Definition(dst
), src0
, src1
);
1792 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1796 case nir_op_cube_face_coord
: {
1797 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1798 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1799 emit_extract_vector(ctx
, in
, 1, v1
),
1800 emit_extract_vector(ctx
, in
, 2, v1
) };
1801 Temp ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1802 ma
= bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), ma
);
1803 Temp sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1804 Temp tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), src
[0], src
[1], src
[2]);
1805 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
),
1806 Operand(0x3f000000u
/*0.5*/),
1807 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, ma
));
1808 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
),
1809 Operand(0x3f000000u
/*0.5*/),
1810 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, ma
));
1811 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), sc
, tc
);
1814 case nir_op_cube_face_index
: {
1815 Temp in
= get_alu_src(ctx
, instr
->src
[0], 3);
1816 Temp src
[3] = { emit_extract_vector(ctx
, in
, 0, v1
),
1817 emit_extract_vector(ctx
, in
, 1, v1
),
1818 emit_extract_vector(ctx
, in
, 2, v1
) };
1819 bld
.vop3(aco_opcode::v_cubeid_f32
, Definition(dst
), src
[0], src
[1], src
[2]);
1822 case nir_op_bcsel
: {
1823 emit_bcsel(ctx
, instr
, dst
);
1827 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1828 if (dst
.regClass() == v2b
) {
1829 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f16
, dst
);
1830 } else if (dst
.regClass() == v1
) {
1831 emit_rsq(ctx
, bld
, Definition(dst
), src
);
1832 } else if (dst
.regClass() == v2
) {
1833 /* Lowered at NIR level for precision reasons. */
1834 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rsq_f64
, dst
);
1836 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1841 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1842 if (dst
.regClass() == v2b
) {
1843 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1844 src
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v2b
), Operand((uint16_t)0x3C00), as_vgpr(ctx
, src
));
1845 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x8000u
), as_vgpr(ctx
, src
));
1846 } else if (dst
.regClass() == v1
) {
1847 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1848 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1849 bld
.vop2(aco_opcode::v_xor_b32
, Definition(dst
), Operand(0x80000000u
), as_vgpr(ctx
, src
));
1850 } else if (dst
.regClass() == v2
) {
1851 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1852 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1853 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1854 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1855 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), Operand(0x80000000u
), upper
);
1856 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1858 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1863 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1864 if (dst
.regClass() == v2b
) {
1865 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1866 src
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v2b
), Operand((uint16_t)0x3C00), as_vgpr(ctx
, src
));
1867 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFu
), as_vgpr(ctx
, src
));
1868 } else if (dst
.regClass() == v1
) {
1869 if (ctx
->block
->fp_mode
.must_flush_denorms32
)
1870 src
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0x3f800000u
), as_vgpr(ctx
, src
));
1871 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), Operand(0x7FFFFFFFu
), as_vgpr(ctx
, src
));
1872 } else if (dst
.regClass() == v2
) {
1873 if (ctx
->block
->fp_mode
.must_flush_denorms16_64
)
1874 src
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), Operand(0x3FF0000000000000lu
), as_vgpr(ctx
, src
));
1875 Temp upper
= bld
.tmp(v1
), lower
= bld
.tmp(v1
);
1876 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
1877 upper
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7FFFFFFFu
), upper
);
1878 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
1880 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1885 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1886 if (dst
.regClass() == v2b
) {
1887 bld
.vop3(aco_opcode::v_med3_f16
, Definition(dst
), Operand((uint16_t)0u), Operand((uint16_t)0x3c00), src
);
1888 } else if (dst
.regClass() == v1
) {
1889 bld
.vop3(aco_opcode::v_med3_f32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
1890 /* apparently, it is not necessary to flush denorms if this instruction is used with these operands */
1891 // TODO: confirm that this holds under any circumstances
1892 } else if (dst
.regClass() == v2
) {
1893 Instruction
* add
= bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), src
, Operand(0u));
1894 VOP3A_instruction
* vop3
= static_cast<VOP3A_instruction
*>(add
);
1897 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1901 case nir_op_flog2
: {
1902 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1903 if (dst
.regClass() == v2b
) {
1904 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_log_f16
, dst
);
1905 } else if (dst
.regClass() == v1
) {
1906 emit_log2(ctx
, bld
, Definition(dst
), src
);
1908 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1913 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1914 if (dst
.regClass() == v2b
) {
1915 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f16
, dst
);
1916 } else if (dst
.regClass() == v1
) {
1917 emit_rcp(ctx
, bld
, Definition(dst
), src
);
1918 } else if (dst
.regClass() == v2
) {
1919 /* Lowered at NIR level for precision reasons. */
1920 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rcp_f64
, dst
);
1922 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1926 case nir_op_fexp2
: {
1927 if (dst
.regClass() == v2b
) {
1928 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f16
, dst
);
1929 } else if (dst
.regClass() == v1
) {
1930 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_exp_f32
, dst
);
1932 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1936 case nir_op_fsqrt
: {
1937 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1938 if (dst
.regClass() == v2b
) {
1939 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f16
, dst
);
1940 } else if (dst
.regClass() == v1
) {
1941 emit_sqrt(ctx
, bld
, Definition(dst
), src
);
1942 } else if (dst
.regClass() == v2
) {
1943 /* Lowered at NIR level for precision reasons. */
1944 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_sqrt_f64
, dst
);
1946 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1950 case nir_op_ffract
: {
1951 if (dst
.regClass() == v2b
) {
1952 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f16
, dst
);
1953 } else if (dst
.regClass() == v1
) {
1954 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f32
, dst
);
1955 } else if (dst
.regClass() == v2
) {
1956 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_fract_f64
, dst
);
1958 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1962 case nir_op_ffloor
: {
1963 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
1964 if (dst
.regClass() == v2b
) {
1965 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f16
, dst
);
1966 } else if (dst
.regClass() == v1
) {
1967 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_floor_f32
, dst
);
1968 } else if (dst
.regClass() == v2
) {
1969 emit_floor_f64(ctx
, bld
, Definition(dst
), src
);
1971 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
1975 case nir_op_fceil
: {
1976 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
1977 if (dst
.regClass() == v2b
) {
1978 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f16
, dst
);
1979 } else if (dst
.regClass() == v1
) {
1980 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f32
, dst
);
1981 } else if (dst
.regClass() == v2
) {
1982 if (ctx
->options
->chip_class
>= GFX7
) {
1983 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_ceil_f64
, dst
);
1985 /* GFX6 doesn't support V_CEIL_F64, lower it. */
1986 /* trunc = trunc(src0)
1987 * if (src0 > 0.0 && src0 != trunc)
1990 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src0
);
1991 Temp tmp0
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.def(bld
.lm
), src0
, Operand(0u));
1992 Temp tmp1
= bld
.vopc(aco_opcode::v_cmp_lg_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, trunc
);
1993 Temp cond
= bld
.sop2(aco_opcode::s_and_b64
, bld
.hint_vcc(bld
.def(s2
)), bld
.def(s1
, scc
), tmp0
, tmp1
);
1994 Temp add
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0u)), bld
.copy(bld
.def(v1
), Operand(0x3ff00000u
)), cond
);
1995 add
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), bld
.copy(bld
.def(v1
), Operand(0u)), add
);
1996 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), trunc
, add
);
1999 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2003 case nir_op_ftrunc
: {
2004 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2005 if (dst
.regClass() == v2b
) {
2006 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f16
, dst
);
2007 } else if (dst
.regClass() == v1
) {
2008 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_trunc_f32
, dst
);
2009 } else if (dst
.regClass() == v2
) {
2010 emit_trunc_f64(ctx
, bld
, Definition(dst
), src
);
2012 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2016 case nir_op_fround_even
: {
2017 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2018 if (dst
.regClass() == v2b
) {
2019 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f16
, dst
);
2020 } else if (dst
.regClass() == v1
) {
2021 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f32
, dst
);
2022 } else if (dst
.regClass() == v2
) {
2023 if (ctx
->options
->chip_class
>= GFX7
) {
2024 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_rndne_f64
, dst
);
2026 /* GFX6 doesn't support V_RNDNE_F64, lower it. */
2027 Temp src0_lo
= bld
.tmp(v1
), src0_hi
= bld
.tmp(v1
);
2028 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0_lo
), Definition(src0_hi
), src0
);
2030 Temp bitmask
= bld
.sop1(aco_opcode::s_brev_b32
, bld
.def(s1
), bld
.copy(bld
.def(s1
), Operand(-2u)));
2031 Temp bfi
= bld
.vop3(aco_opcode::v_bfi_b32
, bld
.def(v1
), bitmask
, bld
.copy(bld
.def(v1
), Operand(0x43300000u
)), as_vgpr(ctx
, src0_hi
));
2032 Temp tmp
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), src0
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2033 Instruction
*sub
= bld
.vop3(aco_opcode::v_add_f64
, bld
.def(v2
), tmp
, bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), bfi
));
2034 static_cast<VOP3A_instruction
*>(sub
)->neg
[1] = true;
2035 tmp
= sub
->definitions
[0].getTemp();
2037 Temp v
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(-1u), Operand(0x432fffffu
));
2038 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_gt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), src0
, v
);
2039 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2040 Temp cond
= vop3
->definitions
[0].getTemp();
2042 Temp tmp_lo
= bld
.tmp(v1
), tmp_hi
= bld
.tmp(v1
);
2043 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp_lo
), Definition(tmp_hi
), tmp
);
2044 Temp dst0
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_lo
, as_vgpr(ctx
, src0_lo
), cond
);
2045 Temp dst1
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp_hi
, as_vgpr(ctx
, src0_hi
), cond
);
2047 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), dst0
, dst1
);
2050 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2056 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2057 aco_ptr
<Instruction
> norm
;
2058 if (dst
.regClass() == v2b
) {
2059 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3118u
));
2060 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f16
, bld
.def(v1
), half_pi
, src
);
2061 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f16
: aco_opcode::v_cos_f16
;
2062 bld
.vop1(opcode
, Definition(dst
), tmp
);
2063 } else if (dst
.regClass() == v1
) {
2064 Temp half_pi
= bld
.copy(bld
.def(s1
), Operand(0x3e22f983u
));
2065 Temp tmp
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), half_pi
, src
);
2067 /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */
2068 if (ctx
->options
->chip_class
< GFX9
)
2069 tmp
= bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), tmp
);
2071 aco_opcode opcode
= instr
->op
== nir_op_fsin
? aco_opcode::v_sin_f32
: aco_opcode::v_cos_f32
;
2072 bld
.vop1(opcode
, Definition(dst
), tmp
);
2074 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2078 case nir_op_ldexp
: {
2079 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2080 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2081 if (dst
.regClass() == v2b
) {
2082 emit_vop2_instruction(ctx
, instr
, aco_opcode::v_ldexp_f16
, dst
, false);
2083 } else if (dst
.regClass() == v1
) {
2084 bld
.vop3(aco_opcode::v_ldexp_f32
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2085 } else if (dst
.regClass() == v2
) {
2086 bld
.vop3(aco_opcode::v_ldexp_f64
, Definition(dst
), as_vgpr(ctx
, src0
), src1
);
2088 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2092 case nir_op_frexp_sig
: {
2093 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2094 if (dst
.regClass() == v2b
) {
2095 bld
.vop1(aco_opcode::v_frexp_mant_f16
, Definition(dst
), src
);
2096 } else if (dst
.regClass() == v1
) {
2097 bld
.vop1(aco_opcode::v_frexp_mant_f32
, Definition(dst
), src
);
2098 } else if (dst
.regClass() == v2
) {
2099 bld
.vop1(aco_opcode::v_frexp_mant_f64
, Definition(dst
), src
);
2101 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2105 case nir_op_frexp_exp
: {
2106 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2107 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2108 Temp tmp
= bld
.vop1(aco_opcode::v_frexp_exp_i16_f16
, bld
.def(v1
), src
);
2109 tmp
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(v1b
), tmp
, Operand(0u));
2110 convert_int(ctx
, bld
, tmp
, 8, 32, true, dst
);
2111 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2112 bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, Definition(dst
), src
);
2113 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2114 bld
.vop1(aco_opcode::v_frexp_exp_i32_f64
, Definition(dst
), src
);
2116 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2120 case nir_op_fsign
: {
2121 Temp src
= as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]));
2122 if (dst
.regClass() == v2b
) {
2123 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2124 Temp minus_one
= bld
.copy(bld
.def(v1
), Operand(0xbc00u
));
2125 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2126 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), one
, src
, cond
);
2127 cond
= bld
.vopc(aco_opcode::v_cmp_le_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2128 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), minus_one
, src
, cond
);
2129 } else if (dst
.regClass() == v1
) {
2130 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2131 src
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0x3f800000u
), src
, cond
);
2132 cond
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2133 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0xbf800000u
), src
, cond
);
2134 } else if (dst
.regClass() == v2
) {
2135 Temp cond
= bld
.vopc(aco_opcode::v_cmp_nlt_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2136 Temp tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0x3FF00000u
));
2137 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, emit_extract_vector(ctx
, src
, 1, v1
), cond
);
2139 cond
= bld
.vopc(aco_opcode::v_cmp_le_f64
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), src
);
2140 tmp
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0xBFF00000u
));
2141 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), tmp
, upper
, cond
);
2143 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2145 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2150 case nir_op_f2f16_rtne
: {
2151 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2152 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2153 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2154 if (instr
->op
== nir_op_f2f16_rtne
&& ctx
->block
->fp_mode
.round16_64
!= fp_round_ne
)
2155 /* We emit s_round_mode/s_setreg_imm32 in lower_to_hw_instr to
2156 * keep value numbering and the scheduler simpler.
2158 bld
.vop1(aco_opcode::p_cvt_f16_f32_rtne
, Definition(dst
), src
);
2160 bld
.vop1(aco_opcode::v_cvt_f16_f32
, Definition(dst
), src
);
2163 case nir_op_f2f16_rtz
: {
2164 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2165 if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2166 src
= bld
.vop1(aco_opcode::v_cvt_f32_f64
, bld
.def(v1
), src
);
2167 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src
, Operand(0u));
2170 case nir_op_f2f32
: {
2171 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2172 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f16
, dst
);
2173 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2174 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_f32_f64
, dst
);
2176 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2180 case nir_op_f2f64
: {
2181 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2182 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2183 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2184 bld
.vop1(aco_opcode::v_cvt_f64_f32
, Definition(dst
), src
);
2187 case nir_op_i2f16
: {
2188 assert(dst
.regClass() == v2b
);
2189 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2190 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2191 src
= convert_int(ctx
, bld
, src
, 8, 16, true);
2192 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2193 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2194 bld
.vop1(aco_opcode::v_cvt_f16_i16
, Definition(dst
), src
);
2197 case nir_op_i2f32
: {
2198 assert(dst
.size() == 1);
2199 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2200 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2201 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2202 bld
.vop1(aco_opcode::v_cvt_f32_i32
, Definition(dst
), src
);
2205 case nir_op_i2f64
: {
2206 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2207 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2208 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2209 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2210 bld
.vop1(aco_opcode::v_cvt_f64_i32
, Definition(dst
), src
);
2211 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2212 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2213 RegClass rc
= RegClass(src
.type(), 1);
2214 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2215 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2216 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2217 upper
= bld
.vop1(aco_opcode::v_cvt_f64_i32
, bld
.def(v2
), upper
);
2218 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2219 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2222 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2226 case nir_op_u2f16
: {
2227 assert(dst
.regClass() == v2b
);
2228 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2229 if (instr
->src
[0].src
.ssa
->bit_size
== 8)
2230 src
= convert_int(ctx
, bld
, src
, 8, 16, false);
2231 else if (instr
->src
[0].src
.ssa
->bit_size
== 64)
2232 src
= convert_int(ctx
, bld
, src
, 64, 32, false);
2233 bld
.vop1(aco_opcode::v_cvt_f16_u16
, Definition(dst
), src
);
2236 case nir_op_u2f32
: {
2237 assert(dst
.size() == 1);
2238 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2239 if (instr
->src
[0].src
.ssa
->bit_size
== 8) {
2240 bld
.vop1(aco_opcode::v_cvt_f32_ubyte0
, Definition(dst
), src
);
2242 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2243 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, true);
2244 bld
.vop1(aco_opcode::v_cvt_f32_u32
, Definition(dst
), src
);
2248 case nir_op_u2f64
: {
2249 if (instr
->src
[0].src
.ssa
->bit_size
<= 32) {
2250 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2251 if (instr
->src
[0].src
.ssa
->bit_size
<= 16)
2252 src
= convert_int(ctx
, bld
, src
, instr
->src
[0].src
.ssa
->bit_size
, 32, false);
2253 bld
.vop1(aco_opcode::v_cvt_f64_u32
, Definition(dst
), src
);
2254 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2255 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2256 RegClass rc
= RegClass(src
.type(), 1);
2257 Temp lower
= bld
.tmp(rc
), upper
= bld
.tmp(rc
);
2258 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), src
);
2259 lower
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), lower
);
2260 upper
= bld
.vop1(aco_opcode::v_cvt_f64_u32
, bld
.def(v2
), upper
);
2261 upper
= bld
.vop3(aco_opcode::v_ldexp_f64
, bld
.def(v2
), upper
, Operand(32u));
2262 bld
.vop3(aco_opcode::v_add_f64
, Definition(dst
), lower
, upper
);
2264 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2269 case nir_op_f2i16
: {
2270 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2271 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i16_f16
, dst
);
2272 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2273 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2275 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2279 case nir_op_f2u16
: {
2280 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2281 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u16_f16
, dst
);
2282 else if (instr
->src
[0].src
.ssa
->bit_size
== 32)
2283 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2285 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2288 case nir_op_f2i32
: {
2289 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2290 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2291 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2292 if (dst
.type() == RegType::vgpr
) {
2293 bld
.vop1(aco_opcode::v_cvt_i32_f32
, Definition(dst
), tmp
);
2295 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2296 bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), tmp
));
2298 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2299 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f32
, dst
);
2300 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2301 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_i32_f64
, dst
);
2303 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2307 case nir_op_f2u32
: {
2308 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2309 if (instr
->src
[0].src
.ssa
->bit_size
== 16) {
2310 Temp tmp
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2311 if (dst
.type() == RegType::vgpr
) {
2312 bld
.vop1(aco_opcode::v_cvt_u32_f32
, Definition(dst
), tmp
);
2314 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
),
2315 bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), tmp
));
2317 } else if (instr
->src
[0].src
.ssa
->bit_size
== 32) {
2318 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f32
, dst
);
2319 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2320 emit_vop1_instruction(ctx
, instr
, aco_opcode::v_cvt_u32_f64
, dst
);
2322 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2326 case nir_op_f2i64
: {
2327 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2328 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2329 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2331 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2332 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2333 exponent
= bld
.vop3(aco_opcode::v_med3_i32
, bld
.def(v1
), Operand(0x0u
), exponent
, Operand(64u));
2334 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2335 Temp sign
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(31u), src
);
2336 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2337 mantissa
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(7u), mantissa
);
2338 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2339 Temp new_exponent
= bld
.tmp(v1
);
2340 Temp borrow
= bld
.vsub32(Definition(new_exponent
), Operand(63u), exponent
, true).def(1).getTemp();
2341 if (ctx
->program
->chip_class
>= GFX8
)
2342 mantissa
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2344 mantissa
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2345 Temp saturate
= bld
.vop1(aco_opcode::v_bfrev_b32
, bld
.def(v1
), Operand(0xfffffffeu
));
2346 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2347 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2348 lower
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, Operand(0xffffffffu
), borrow
);
2349 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, saturate
, borrow
);
2350 lower
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, lower
);
2351 upper
= bld
.vop2(aco_opcode::v_xor_b32
, bld
.def(v1
), sign
, upper
);
2352 Temp new_lower
= bld
.tmp(v1
);
2353 borrow
= bld
.vsub32(Definition(new_lower
), lower
, sign
, true).def(1).getTemp();
2354 Temp new_upper
= bld
.vsub32(bld
.def(v1
), upper
, sign
, false, borrow
);
2355 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), new_lower
, new_upper
);
2357 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2358 if (src
.type() == RegType::vgpr
)
2359 src
= bld
.as_uniform(src
);
2360 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2361 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2362 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2363 exponent
= bld
.sop2(aco_opcode::s_min_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(64u), exponent
);
2364 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2365 Temp sign
= bld
.sop2(aco_opcode::s_ashr_i32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(31u));
2366 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2367 mantissa
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, Operand(7u));
2368 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2369 exponent
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(63u), exponent
);
2370 mantissa
= bld
.sop2(aco_opcode::s_lshr_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent
);
2371 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), exponent
, Operand(0xffffffffu
)); // exp >= 64
2372 Temp saturate
= bld
.sop1(aco_opcode::s_brev_b64
, bld
.def(s2
), Operand(0xfffffffeu
));
2373 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), saturate
, mantissa
, cond
);
2374 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2375 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2376 lower
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, lower
);
2377 upper
= bld
.sop2(aco_opcode::s_xor_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sign
, upper
);
2378 Temp borrow
= bld
.tmp(s1
);
2379 lower
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.scc(Definition(borrow
)), lower
, sign
);
2380 upper
= bld
.sop2(aco_opcode::s_subb_u32
, bld
.def(s1
), bld
.def(s1
, scc
), upper
, sign
, borrow
);
2381 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2383 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2384 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2385 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2386 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2387 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2388 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2389 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2390 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2391 Temp upper
= bld
.vop1(aco_opcode::v_cvt_i32_f64
, bld
.def(v1
), floor
);
2392 if (dst
.type() == RegType::sgpr
) {
2393 lower
= bld
.as_uniform(lower
);
2394 upper
= bld
.as_uniform(upper
);
2396 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2399 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2403 case nir_op_f2u64
: {
2404 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2405 if (instr
->src
[0].src
.ssa
->bit_size
== 16)
2406 src
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), src
);
2408 if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::vgpr
) {
2409 Temp exponent
= bld
.vop1(aco_opcode::v_frexp_exp_i32_f32
, bld
.def(v1
), src
);
2410 Temp exponent_in_range
= bld
.vopc(aco_opcode::v_cmp_ge_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(64u), exponent
);
2411 exponent
= bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
), Operand(0x0u
), exponent
);
2412 Temp mantissa
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffu
), src
);
2413 mantissa
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(0x800000u
), mantissa
);
2414 Temp exponent_small
= bld
.vsub32(bld
.def(v1
), Operand(24u), exponent
);
2415 Temp small
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), exponent_small
, mantissa
);
2416 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), Operand(0u), mantissa
);
2417 Temp new_exponent
= bld
.tmp(v1
);
2418 Temp cond_small
= bld
.vsub32(Definition(new_exponent
), exponent
, Operand(24u), true).def(1).getTemp();
2419 if (ctx
->program
->chip_class
>= GFX8
)
2420 mantissa
= bld
.vop3(aco_opcode::v_lshlrev_b64
, bld
.def(v2
), new_exponent
, mantissa
);
2422 mantissa
= bld
.vop3(aco_opcode::v_lshl_b64
, bld
.def(v2
), mantissa
, new_exponent
);
2423 Temp lower
= bld
.tmp(v1
), upper
= bld
.tmp(v1
);
2424 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2425 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), lower
, small
, cond_small
);
2426 upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), upper
, Operand(0u), cond_small
);
2427 lower
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), lower
, exponent_in_range
);
2428 upper
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xffffffffu
), upper
, exponent_in_range
);
2429 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2431 } else if (instr
->src
[0].src
.ssa
->bit_size
<= 32 && dst
.type() == RegType::sgpr
) {
2432 if (src
.type() == RegType::vgpr
)
2433 src
= bld
.as_uniform(src
);
2434 Temp exponent
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), src
, Operand(0x80017u
));
2435 exponent
= bld
.sop2(aco_opcode::s_sub_i32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(126u));
2436 exponent
= bld
.sop2(aco_opcode::s_max_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0u), exponent
);
2437 Temp mantissa
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x7fffffu
), src
);
2438 mantissa
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0x800000u
), mantissa
);
2439 Temp exponent_small
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(24u), exponent
);
2440 Temp small
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), mantissa
, exponent_small
);
2441 mantissa
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), mantissa
);
2442 Temp exponent_large
= bld
.sop2(aco_opcode::s_sub_u32
, bld
.def(s1
), bld
.def(s1
, scc
), exponent
, Operand(24u));
2443 mantissa
= bld
.sop2(aco_opcode::s_lshl_b64
, bld
.def(s2
), bld
.def(s1
, scc
), mantissa
, exponent_large
);
2444 Temp cond
= bld
.sopc(aco_opcode::s_cmp_ge_i32
, bld
.def(s1
, scc
), Operand(64u), exponent
);
2445 mantissa
= bld
.sop2(aco_opcode::s_cselect_b64
, bld
.def(s2
), mantissa
, Operand(0xffffffffu
), cond
);
2446 Temp lower
= bld
.tmp(s1
), upper
= bld
.tmp(s1
);
2447 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lower
), Definition(upper
), mantissa
);
2448 Temp cond_small
= bld
.sopc(aco_opcode::s_cmp_le_i32
, bld
.def(s1
, scc
), exponent
, Operand(24u));
2449 lower
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), small
, lower
, cond_small
);
2450 upper
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), Operand(0u), upper
, cond_small
);
2451 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2453 } else if (instr
->src
[0].src
.ssa
->bit_size
== 64) {
2454 Temp vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0x3df00000u
));
2455 Temp trunc
= emit_trunc_f64(ctx
, bld
, bld
.def(v2
), src
);
2456 Temp mul
= bld
.vop3(aco_opcode::v_mul_f64
, bld
.def(v2
), trunc
, vec
);
2457 vec
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(0u), Operand(0xc1f00000u
));
2458 Temp floor
= emit_floor_f64(ctx
, bld
, bld
.def(v2
), mul
);
2459 Temp fma
= bld
.vop3(aco_opcode::v_fma_f64
, bld
.def(v2
), floor
, vec
, trunc
);
2460 Temp lower
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), fma
);
2461 Temp upper
= bld
.vop1(aco_opcode::v_cvt_u32_f64
, bld
.def(v1
), floor
);
2462 if (dst
.type() == RegType::sgpr
) {
2463 lower
= bld
.as_uniform(lower
);
2464 upper
= bld
.as_uniform(upper
);
2466 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lower
, upper
);
2469 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2473 case nir_op_b2f16
: {
2474 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2475 assert(src
.regClass() == bld
.lm
);
2477 if (dst
.regClass() == s1
) {
2478 src
= bool_to_scalar_condition(ctx
, src
);
2479 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3c00u
), src
);
2480 } else if (dst
.regClass() == v2b
) {
2481 Temp one
= bld
.copy(bld
.def(v1
), Operand(0x3c00u
));
2482 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), one
, src
);
2484 unreachable("Wrong destination register class for nir_op_b2f16.");
2488 case nir_op_b2f32
: {
2489 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2490 assert(src
.regClass() == bld
.lm
);
2492 if (dst
.regClass() == s1
) {
2493 src
= bool_to_scalar_condition(ctx
, src
);
2494 bld
.sop2(aco_opcode::s_mul_i32
, Definition(dst
), Operand(0x3f800000u
), src
);
2495 } else if (dst
.regClass() == v1
) {
2496 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand(0x3f800000u
), src
);
2498 unreachable("Wrong destination register class for nir_op_b2f32.");
2502 case nir_op_b2f64
: {
2503 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2504 assert(src
.regClass() == bld
.lm
);
2506 if (dst
.regClass() == s2
) {
2507 src
= bool_to_scalar_condition(ctx
, src
);
2508 bld
.sop2(aco_opcode::s_cselect_b64
, Definition(dst
), Operand(0x3f800000u
), Operand(0u), bld
.scc(src
));
2509 } else if (dst
.regClass() == v2
) {
2510 Temp one
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v2
), Operand(0x3FF00000u
));
2511 Temp upper
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), one
, src
);
2512 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), Operand(0u), upper
);
2514 unreachable("Wrong destination register class for nir_op_b2f64.");
2521 case nir_op_i2i64
: {
2522 if (dst
.type() == RegType::sgpr
&& instr
->src
[0].src
.ssa
->bit_size
< 32) {
2523 /* no need to do the extract in get_alu_src() */
2524 sgpr_extract_mode mode
= instr
->dest
.dest
.ssa
.bit_size
> instr
->src
[0].src
.ssa
->bit_size
?
2525 sgpr_extract_sext
: sgpr_extract_undef
;
2526 extract_8_16_bit_sgpr_element(ctx
, dst
, &instr
->src
[0], mode
);
2528 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2529 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, true, dst
);
2536 case nir_op_u2u64
: {
2537 if (dst
.type() == RegType::sgpr
&& instr
->src
[0].src
.ssa
->bit_size
< 32) {
2538 /* no need to do the extract in get_alu_src() */
2539 sgpr_extract_mode mode
= instr
->dest
.dest
.ssa
.bit_size
> instr
->src
[0].src
.ssa
->bit_size
?
2540 sgpr_extract_zext
: sgpr_extract_undef
;
2541 extract_8_16_bit_sgpr_element(ctx
, dst
, &instr
->src
[0], mode
);
2543 convert_int(ctx
, bld
, get_alu_src(ctx
, instr
->src
[0]),
2544 instr
->src
[0].src
.ssa
->bit_size
, instr
->dest
.dest
.ssa
.bit_size
, false, dst
);
2552 case nir_op_b2i64
: {
2553 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2554 assert(src
.regClass() == bld
.lm
);
2556 Temp tmp
= dst
.bytes() == 8 ? bld
.tmp(RegClass::get(dst
.type(), 4)) : dst
;
2557 if (tmp
.regClass() == s1
) {
2558 // TODO: in a post-RA optimization, we can check if src is in VCC, and directly use VCCNZ
2559 bool_to_scalar_condition(ctx
, src
, tmp
);
2560 } else if (tmp
.type() == RegType::vgpr
) {
2561 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(tmp
), Operand(0u), Operand(1u), src
);
2563 unreachable("Invalid register class for b2i32");
2567 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tmp
, Operand(0u));
2572 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2573 assert(dst
.regClass() == bld
.lm
);
2575 if (src
.type() == RegType::vgpr
) {
2576 assert(src
.regClass() == v1
|| src
.regClass() == v2
);
2577 assert(dst
.regClass() == bld
.lm
);
2578 bld
.vopc(src
.size() == 2 ? aco_opcode::v_cmp_lg_u64
: aco_opcode::v_cmp_lg_u32
,
2579 Definition(dst
), Operand(0u), src
).def(0).setHint(vcc
);
2581 assert(src
.regClass() == s1
|| src
.regClass() == s2
);
2583 if (src
.regClass() == s2
&& ctx
->program
->chip_class
<= GFX7
) {
2584 tmp
= bld
.sop2(aco_opcode::s_or_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(0u), src
).def(1).getTemp();
2586 tmp
= bld
.sopc(src
.size() == 2 ? aco_opcode::s_cmp_lg_u64
: aco_opcode::s_cmp_lg_u32
,
2587 bld
.scc(bld
.def(s1
)), Operand(0u), src
);
2589 bool_to_vector_condition(ctx
, tmp
, dst
);
2593 case nir_op_pack_64_2x32_split
: {
2594 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2595 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2597 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2600 case nir_op_unpack_64_2x32_split_x
:
2601 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2603 case nir_op_unpack_64_2x32_split_y
:
2604 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2606 case nir_op_unpack_32_2x16_split_x
:
2607 if (dst
.type() == RegType::vgpr
) {
2608 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(dst
.regClass()), get_alu_src(ctx
, instr
->src
[0]));
2610 bld
.copy(Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2613 case nir_op_unpack_32_2x16_split_y
:
2614 if (dst
.type() == RegType::vgpr
) {
2615 bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(dst
.regClass()), Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2617 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(dst
), bld
.def(s1
, scc
), get_alu_src(ctx
, instr
->src
[0]), Operand(uint32_t(16 << 16 | 16)));
2620 case nir_op_pack_32_2x16_split
: {
2621 Temp src0
= get_alu_src(ctx
, instr
->src
[0]);
2622 Temp src1
= get_alu_src(ctx
, instr
->src
[1]);
2623 if (dst
.regClass() == v1
) {
2624 src0
= emit_extract_vector(ctx
, src0
, 0, v2b
);
2625 src1
= emit_extract_vector(ctx
, src1
, 0, v2b
);
2626 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src0
, src1
);
2628 src0
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src0
, Operand(0xFFFFu
));
2629 src1
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), src1
, Operand(16u));
2630 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), src0
, src1
);
2634 case nir_op_pack_half_2x16
: {
2635 Temp src
= get_alu_src(ctx
, instr
->src
[0], 2);
2637 if (dst
.regClass() == v1
) {
2638 Temp src0
= bld
.tmp(v1
);
2639 Temp src1
= bld
.tmp(v1
);
2640 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src0
), Definition(src1
), src
);
2641 if (0 && (!ctx
->block
->fp_mode
.care_about_round32
|| ctx
->block
->fp_mode
.round32
== fp_round_tz
)) {
2642 bld
.vop3(aco_opcode::v_cvt_pkrtz_f16_f32
, Definition(dst
), src0
, src1
);
2644 src0
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src0
);
2645 src1
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src1
);
2646 if (ctx
->program
->chip_class
>= GFX10
) {
2647 /* the high bits of v_cvt_f16_f32 isn't zero'd on GFX10 */
2648 bld
.vop3(aco_opcode::v_pack_b32_f16
, Definition(dst
), src0
, src1
);
2650 bld
.vop3(aco_opcode::v_cvt_pk_u16_u32
, Definition(dst
), src0
, src1
);
2654 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2658 case nir_op_unpack_half_2x16_split_x
: {
2659 if (dst
.regClass() == v1
) {
2660 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
), get_alu_src(ctx
, instr
->src
[0]));
2662 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2666 case nir_op_unpack_half_2x16_split_y
: {
2667 if (dst
.regClass() == v1
) {
2668 /* TODO: use SDWA here */
2669 bld
.vop1(aco_opcode::v_cvt_f32_f16
, Definition(dst
),
2670 bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), as_vgpr(ctx
, get_alu_src(ctx
, instr
->src
[0]))));
2672 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2676 case nir_op_fquantize2f16
: {
2677 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2678 Temp f16
= bld
.vop1(aco_opcode::v_cvt_f16_f32
, bld
.def(v1
), src
);
2681 if (ctx
->program
->chip_class
>= GFX8
) {
2682 Temp mask
= bld
.copy(bld
.def(s1
), Operand(0x36Fu
)); /* value is NOT negative/positive denormal value */
2683 cmp_res
= bld
.vopc_e64(aco_opcode::v_cmp_class_f16
, bld
.hint_vcc(bld
.def(bld
.lm
)), f16
, mask
);
2684 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2686 /* 0x38800000 is smallest half float value (2^-14) in 32-bit float,
2687 * so compare the result and flush to 0 if it's smaller.
2689 f32
= bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), f16
);
2690 Temp smallest
= bld
.copy(bld
.def(s1
), Operand(0x38800000u
));
2691 Instruction
* vop3
= bld
.vopc_e64(aco_opcode::v_cmp_nlt_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), f32
, smallest
);
2692 static_cast<VOP3A_instruction
*>(vop3
)->abs
[0] = true;
2693 cmp_res
= vop3
->definitions
[0].getTemp();
2696 if (ctx
->block
->fp_mode
.preserve_signed_zero_inf_nan32
|| ctx
->program
->chip_class
< GFX8
) {
2697 Temp copysign_0
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0u), as_vgpr(ctx
, src
));
2698 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), copysign_0
, f32
, cmp_res
);
2700 bld
.vop2(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), f32
, cmp_res
);
2705 Temp bits
= get_alu_src(ctx
, instr
->src
[0]);
2706 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2708 if (dst
.regClass() == s1
) {
2709 bld
.sop2(aco_opcode::s_bfm_b32
, Definition(dst
), bits
, offset
);
2710 } else if (dst
.regClass() == v1
) {
2711 bld
.vop3(aco_opcode::v_bfm_b32
, Definition(dst
), bits
, offset
);
2713 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2717 case nir_op_bitfield_select
: {
2718 /* (mask & insert) | (~mask & base) */
2719 Temp bitmask
= get_alu_src(ctx
, instr
->src
[0]);
2720 Temp insert
= get_alu_src(ctx
, instr
->src
[1]);
2721 Temp base
= get_alu_src(ctx
, instr
->src
[2]);
2723 /* dst = (insert & bitmask) | (base & ~bitmask) */
2724 if (dst
.regClass() == s1
) {
2725 aco_ptr
<Instruction
> sop2
;
2726 nir_const_value
* const_bitmask
= nir_src_as_const_value(instr
->src
[0].src
);
2727 nir_const_value
* const_insert
= nir_src_as_const_value(instr
->src
[1].src
);
2729 if (const_insert
&& const_bitmask
) {
2730 lhs
= Operand(const_insert
->u32
& const_bitmask
->u32
);
2732 insert
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), insert
, bitmask
);
2733 lhs
= Operand(insert
);
2737 nir_const_value
* const_base
= nir_src_as_const_value(instr
->src
[2].src
);
2738 if (const_base
&& const_bitmask
) {
2739 rhs
= Operand(const_base
->u32
& ~const_bitmask
->u32
);
2741 base
= bld
.sop2(aco_opcode::s_andn2_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, bitmask
);
2742 rhs
= Operand(base
);
2745 bld
.sop2(aco_opcode::s_or_b32
, Definition(dst
), bld
.def(s1
, scc
), rhs
, lhs
);
2747 } else if (dst
.regClass() == v1
) {
2748 if (base
.type() == RegType::sgpr
&& (bitmask
.type() == RegType::sgpr
|| (insert
.type() == RegType::sgpr
)))
2749 base
= as_vgpr(ctx
, base
);
2750 if (insert
.type() == RegType::sgpr
&& bitmask
.type() == RegType::sgpr
)
2751 insert
= as_vgpr(ctx
, insert
);
2753 bld
.vop3(aco_opcode::v_bfi_b32
, Definition(dst
), bitmask
, insert
, base
);
2756 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2762 if (dst
.bytes() != 4)
2763 unreachable("Unsupported BFE bit size");
2765 if (dst
.type() == RegType::sgpr
) {
2766 Temp base
= get_alu_src(ctx
, instr
->src
[0]);
2768 nir_const_value
* const_offset
= nir_src_as_const_value(instr
->src
[1].src
);
2769 nir_const_value
* const_bits
= nir_src_as_const_value(instr
->src
[2].src
);
2770 if (const_offset
&& const_bits
) {
2771 uint32_t extract
= (const_bits
->u32
<< 16) | (const_offset
->u32
& 0x1f);
2772 aco_opcode opcode
= instr
->op
== nir_op_ubfe
? aco_opcode::s_bfe_u32
: aco_opcode::s_bfe_i32
;
2773 bld
.sop2(opcode
, Definition(dst
), bld
.def(s1
, scc
), base
, Operand(extract
));
2777 Temp offset
= get_alu_src(ctx
, instr
->src
[1]);
2778 Temp bits
= get_alu_src(ctx
, instr
->src
[2]);
2779 if (instr
->op
== nir_op_ubfe
) {
2780 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b32
, bld
.def(s1
), bits
, offset
);
2781 Temp masked
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), base
, mask
);
2782 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(dst
), bld
.def(s1
, scc
), masked
, offset
);
2784 Operand bits_op
= const_bits
? Operand(const_bits
->u32
<< 16) :
2785 bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits
, Operand(16u));
2786 Operand offset_op
= const_offset
? Operand(const_offset
->u32
& 0x1fu
) :
2787 bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(0x1fu
));
2789 Temp extract
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), bits_op
, offset_op
);
2790 bld
.sop2(aco_opcode::s_bfe_i32
, Definition(dst
), bld
.def(s1
, scc
), base
, extract
);
2794 aco_opcode opcode
= instr
->op
== nir_op_ubfe
? aco_opcode::v_bfe_u32
: aco_opcode::v_bfe_i32
;
2795 emit_vop3a_instruction(ctx
, instr
, opcode
, dst
);
2799 case nir_op_bit_count
: {
2800 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2801 if (src
.regClass() == s1
) {
2802 bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, Definition(dst
), bld
.def(s1
, scc
), src
);
2803 } else if (src
.regClass() == v1
) {
2804 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
), src
, Operand(0u));
2805 } else if (src
.regClass() == v2
) {
2806 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, Definition(dst
),
2807 emit_extract_vector(ctx
, src
, 1, v1
),
2808 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
),
2809 emit_extract_vector(ctx
, src
, 0, v1
), Operand(0u)));
2810 } else if (src
.regClass() == s2
) {
2811 bld
.sop1(aco_opcode::s_bcnt1_i32_b64
, Definition(dst
), bld
.def(s1
, scc
), src
);
2813 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
2818 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_f16
, aco_opcode::v_cmp_lt_f32
, aco_opcode::v_cmp_lt_f64
);
2822 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_f16
, aco_opcode::v_cmp_ge_f32
, aco_opcode::v_cmp_ge_f64
);
2826 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_f16
, aco_opcode::v_cmp_eq_f32
, aco_opcode::v_cmp_eq_f64
);
2830 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_neq_f16
, aco_opcode::v_cmp_neq_f32
, aco_opcode::v_cmp_neq_f64
);
2834 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_i16
, aco_opcode::v_cmp_lt_i32
, aco_opcode::v_cmp_lt_i64
, aco_opcode::s_cmp_lt_i32
);
2838 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_i16
, aco_opcode::v_cmp_ge_i32
, aco_opcode::v_cmp_ge_i64
, aco_opcode::s_cmp_ge_i32
);
2842 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2843 emit_boolean_logic(ctx
, instr
, Builder::s_xnor
, dst
);
2845 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_eq_i16
, aco_opcode::v_cmp_eq_i32
, aco_opcode::v_cmp_eq_i64
, aco_opcode::s_cmp_eq_i32
,
2846 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_eq_u64
: aco_opcode::num_opcodes
);
2850 if (instr
->src
[0].src
.ssa
->bit_size
== 1)
2851 emit_boolean_logic(ctx
, instr
, Builder::s_xor
, dst
);
2853 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lg_i16
, aco_opcode::v_cmp_lg_i32
, aco_opcode::v_cmp_lg_i64
, aco_opcode::s_cmp_lg_i32
,
2854 ctx
->program
->chip_class
>= GFX8
? aco_opcode::s_cmp_lg_u64
: aco_opcode::num_opcodes
);
2858 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_lt_u16
, aco_opcode::v_cmp_lt_u32
, aco_opcode::v_cmp_lt_u64
, aco_opcode::s_cmp_lt_u32
);
2862 emit_comparison(ctx
, instr
, dst
, aco_opcode::v_cmp_ge_u16
, aco_opcode::v_cmp_ge_u32
, aco_opcode::v_cmp_ge_u64
, aco_opcode::s_cmp_ge_u32
);
2867 case nir_op_fddx_fine
:
2868 case nir_op_fddy_fine
:
2869 case nir_op_fddx_coarse
:
2870 case nir_op_fddy_coarse
: {
2871 Temp src
= get_alu_src(ctx
, instr
->src
[0]);
2872 uint16_t dpp_ctrl1
, dpp_ctrl2
;
2873 if (instr
->op
== nir_op_fddx_fine
) {
2874 dpp_ctrl1
= dpp_quad_perm(0, 0, 2, 2);
2875 dpp_ctrl2
= dpp_quad_perm(1, 1, 3, 3);
2876 } else if (instr
->op
== nir_op_fddy_fine
) {
2877 dpp_ctrl1
= dpp_quad_perm(0, 1, 0, 1);
2878 dpp_ctrl2
= dpp_quad_perm(2, 3, 2, 3);
2880 dpp_ctrl1
= dpp_quad_perm(0, 0, 0, 0);
2881 if (instr
->op
== nir_op_fddx
|| instr
->op
== nir_op_fddx_coarse
)
2882 dpp_ctrl2
= dpp_quad_perm(1, 1, 1, 1);
2884 dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
2888 if (ctx
->program
->chip_class
>= GFX8
) {
2889 Temp tl
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl1
);
2890 tmp
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), src
, tl
, dpp_ctrl2
);
2892 Temp tl
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl1
);
2893 Temp tr
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl2
);
2894 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), tr
, tl
);
2896 emit_wqm(ctx
, tmp
, dst
, true);
2900 isel_err(&instr
->instr
, "Unknown NIR ALU instr");
2904 void visit_load_const(isel_context
*ctx
, nir_load_const_instr
*instr
)
2906 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
2908 // TODO: we really want to have the resulting type as this would allow for 64bit literals
2909 // which get truncated the lsb if double and msb if int
2910 // for now, we only use s_mov_b64 with 64bit inline constants
2911 assert(instr
->def
.num_components
== 1 && "Vector load_const should be lowered to scalar.");
2912 assert(dst
.type() == RegType::sgpr
);
2914 Builder
bld(ctx
->program
, ctx
->block
);
2916 if (instr
->def
.bit_size
== 1) {
2917 assert(dst
.regClass() == bld
.lm
);
2918 int val
= instr
->value
[0].b
? -1 : 0;
2919 Operand op
= bld
.lm
.size() == 1 ? Operand((uint32_t) val
) : Operand((uint64_t) val
);
2920 bld
.sop1(Builder::s_mov
, Definition(dst
), op
);
2921 } else if (instr
->def
.bit_size
== 8) {
2922 /* ensure that the value is correctly represented in the low byte of the register */
2923 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u8
);
2924 } else if (instr
->def
.bit_size
== 16) {
2925 /* ensure that the value is correctly represented in the low half of the register */
2926 bld
.sopk(aco_opcode::s_movk_i32
, Definition(dst
), instr
->value
[0].u16
);
2927 } else if (dst
.size() == 1) {
2928 bld
.copy(Definition(dst
), Operand(instr
->value
[0].u32
));
2930 assert(dst
.size() != 1);
2931 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
2932 if (instr
->def
.bit_size
== 64)
2933 for (unsigned i
= 0; i
< dst
.size(); i
++)
2934 vec
->operands
[i
] = Operand
{(uint32_t)(instr
->value
[0].u64
>> i
* 32)};
2936 for (unsigned i
= 0; i
< dst
.size(); i
++)
2937 vec
->operands
[i
] = Operand
{instr
->value
[i
].u32
};
2939 vec
->definitions
[0] = Definition(dst
);
2940 ctx
->block
->instructions
.emplace_back(std::move(vec
));
2944 uint32_t widen_mask(uint32_t mask
, unsigned multiplier
)
2946 uint32_t new_mask
= 0;
2947 for(unsigned i
= 0; i
< 32 && (1u << i
) <= mask
; ++i
)
2948 if (mask
& (1u << i
))
2949 new_mask
|= ((1u << multiplier
) - 1u) << (i
* multiplier
);
2953 struct LoadEmitInfo
{
2956 unsigned num_components
;
2957 unsigned component_size
;
2958 Temp resource
= Temp(0, s1
);
2959 unsigned component_stride
= 0;
2960 unsigned const_offset
= 0;
2961 unsigned align_mul
= 0;
2962 unsigned align_offset
= 0;
2965 unsigned swizzle_component_size
= 0;
2966 memory_sync_info sync
;
2967 Temp soffset
= Temp(0, s1
);
2970 using LoadCallback
= Temp(*)(
2971 Builder
& bld
, const LoadEmitInfo
* info
, Temp offset
, unsigned bytes_needed
,
2972 unsigned align
, unsigned const_offset
, Temp dst_hint
);
2974 template <LoadCallback callback
, bool byte_align_loads
, bool supports_8bit_16bit_loads
, unsigned max_const_offset_plus_one
>
2975 void emit_load(isel_context
*ctx
, Builder
& bld
, const LoadEmitInfo
*info
)
2977 unsigned load_size
= info
->num_components
* info
->component_size
;
2978 unsigned component_size
= info
->component_size
;
2980 unsigned num_vals
= 0;
2981 Temp vals
[info
->dst
.bytes()];
2983 unsigned const_offset
= info
->const_offset
;
2985 unsigned align_mul
= info
->align_mul
? info
->align_mul
: component_size
;
2986 unsigned align_offset
= (info
->align_offset
+ const_offset
) % align_mul
;
2988 unsigned bytes_read
= 0;
2989 while (bytes_read
< load_size
) {
2990 unsigned bytes_needed
= load_size
- bytes_read
;
2992 /* add buffer for unaligned loads */
2993 int byte_align
= align_mul
% 4 == 0 ? align_offset
% 4 : -1;
2996 if ((bytes_needed
> 2 ||
2997 (bytes_needed
== 2 && (align_mul
% 2 || align_offset
% 2)) ||
2998 !supports_8bit_16bit_loads
) && byte_align_loads
) {
2999 if (info
->component_stride
) {
3000 assert(supports_8bit_16bit_loads
&& "unimplemented");
3004 bytes_needed
+= byte_align
== -1 ? 4 - info
->align_mul
: byte_align
;
3005 bytes_needed
= align(bytes_needed
, 4);
3012 if (info
->swizzle_component_size
)
3013 bytes_needed
= MIN2(bytes_needed
, info
->swizzle_component_size
);
3014 if (info
->component_stride
)
3015 bytes_needed
= MIN2(bytes_needed
, info
->component_size
);
3017 bool need_to_align_offset
= byte_align
&& (align_mul
% 4 || align_offset
% 4);
3019 /* reduce constant offset */
3020 Operand offset
= info
->offset
;
3021 unsigned reduced_const_offset
= const_offset
;
3022 bool remove_const_offset_completely
= need_to_align_offset
;
3023 if (const_offset
&& (remove_const_offset_completely
|| const_offset
>= max_const_offset_plus_one
)) {
3024 unsigned to_add
= const_offset
;
3025 if (remove_const_offset_completely
) {
3026 reduced_const_offset
= 0;
3028 to_add
= const_offset
/ max_const_offset_plus_one
* max_const_offset_plus_one
;
3029 reduced_const_offset
%= max_const_offset_plus_one
;
3031 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3032 if (offset
.isConstant()) {
3033 offset
= Operand(offset
.constantValue() + to_add
);
3034 } else if (offset_tmp
.regClass() == s1
) {
3035 offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
3036 offset_tmp
, Operand(to_add
));
3037 } else if (offset_tmp
.regClass() == v1
) {
3038 offset
= bld
.vadd32(bld
.def(v1
), offset_tmp
, Operand(to_add
));
3040 Temp lo
= bld
.tmp(offset_tmp
.type(), 1);
3041 Temp hi
= bld
.tmp(offset_tmp
.type(), 1);
3042 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3044 if (offset_tmp
.regClass() == s2
) {
3045 Temp carry
= bld
.tmp(s1
);
3046 lo
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), lo
, Operand(to_add
));
3047 hi
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), hi
, carry
);
3048 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), lo
, hi
);
3050 Temp new_lo
= bld
.tmp(v1
);
3051 Temp carry
= bld
.vadd32(Definition(new_lo
), lo
, Operand(to_add
), true).def(1).getTemp();
3052 hi
= bld
.vadd32(bld
.def(v1
), hi
, Operand(0u), false, carry
);
3053 offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_lo
, hi
);
3058 /* align offset down if needed */
3059 Operand aligned_offset
= offset
;
3060 unsigned align
= align_offset
? 1 << (ffs(align_offset
) - 1) : align_mul
;
3061 if (need_to_align_offset
) {
3063 Temp offset_tmp
= offset
.isTemp() ? offset
.getTemp() : Temp();
3064 if (offset
.isConstant()) {
3065 aligned_offset
= Operand(offset
.constantValue() & 0xfffffffcu
);
3066 } else if (offset_tmp
.regClass() == s1
) {
3067 aligned_offset
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfffffffcu
), offset_tmp
);
3068 } else if (offset_tmp
.regClass() == s2
) {
3069 aligned_offset
= bld
.sop2(aco_opcode::s_and_b64
, bld
.def(s2
), bld
.def(s1
, scc
), Operand((uint64_t)0xfffffffffffffffcllu
), offset_tmp
);
3070 } else if (offset_tmp
.regClass() == v1
) {
3071 aligned_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), offset_tmp
);
3072 } else if (offset_tmp
.regClass() == v2
) {
3073 Temp hi
= bld
.tmp(v1
), lo
= bld
.tmp(v1
);
3074 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), offset_tmp
);
3075 lo
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xfffffffcu
), lo
);
3076 aligned_offset
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), lo
, hi
);
3079 Temp aligned_offset_tmp
= aligned_offset
.isTemp() ? aligned_offset
.getTemp() :
3080 bld
.copy(bld
.def(s1
), aligned_offset
);
3082 Temp val
= callback(bld
, info
, aligned_offset_tmp
, bytes_needed
, align
,
3083 reduced_const_offset
, byte_align
? Temp() : info
->dst
);
3085 /* the callback wrote directly to dst */
3086 if (val
== info
->dst
) {
3087 assert(num_vals
== 0);
3088 emit_split_vector(ctx
, info
->dst
, info
->num_components
);
3092 /* shift result right if needed */
3093 if (info
->component_size
< 4 && byte_align_loads
) {
3094 Operand
align((uint32_t)byte_align
);
3095 if (byte_align
== -1) {
3096 if (offset
.isConstant())
3097 align
= Operand(offset
.constantValue() % 4u);
3098 else if (offset
.size() == 2)
3099 align
= Operand(emit_extract_vector(ctx
, offset
.getTemp(), 0, RegClass(offset
.getTemp().type(), 1)));
3104 assert(val
.bytes() >= load_size
&& "unimplemented");
3105 if (val
.type() == RegType::sgpr
)
3106 byte_align_scalar(ctx
, val
, align
, info
->dst
);
3108 byte_align_vector(ctx
, val
, align
, info
->dst
, component_size
);
3112 /* add result to list and advance */
3113 if (info
->component_stride
) {
3114 assert(val
.bytes() == info
->component_size
&& "unimplemented");
3115 const_offset
+= info
->component_stride
;
3116 align_offset
= (align_offset
+ info
->component_stride
) % align_mul
;
3118 const_offset
+= val
.bytes();
3119 align_offset
= (align_offset
+ val
.bytes()) % align_mul
;
3121 bytes_read
+= val
.bytes();
3122 vals
[num_vals
++] = val
;
3125 /* create array of components */
3126 unsigned components_split
= 0;
3127 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3128 bool has_vgprs
= false;
3129 for (unsigned i
= 0; i
< num_vals
;) {
3131 unsigned num_tmps
= 0;
3132 unsigned tmp_size
= 0;
3133 RegType reg_type
= RegType::sgpr
;
3134 while ((!tmp_size
|| (tmp_size
% component_size
)) && i
< num_vals
) {
3135 if (vals
[i
].type() == RegType::vgpr
)
3136 reg_type
= RegType::vgpr
;
3137 tmp_size
+= vals
[i
].bytes();
3138 tmp
[num_tmps
++] = vals
[i
++];
3141 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3142 aco_opcode::p_create_vector
, Format::PSEUDO
, num_tmps
, 1)};
3143 for (unsigned i
= 0; i
< num_tmps
; i
++)
3144 vec
->operands
[i
] = Operand(tmp
[i
]);
3145 tmp
[0] = bld
.tmp(RegClass::get(reg_type
, tmp_size
));
3146 vec
->definitions
[0] = Definition(tmp
[0]);
3147 bld
.insert(std::move(vec
));
3150 if (tmp
[0].bytes() % component_size
) {
3152 assert(i
== num_vals
);
3153 RegClass new_rc
= RegClass::get(reg_type
, tmp
[0].bytes() / component_size
* component_size
);
3154 tmp
[0] = bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(new_rc
), tmp
[0], Operand(0u));
3157 RegClass elem_rc
= RegClass::get(reg_type
, component_size
);
3159 unsigned start
= components_split
;
3161 if (tmp_size
== elem_rc
.bytes()) {
3162 allocated_vec
[components_split
++] = tmp
[0];
3164 assert(tmp_size
% elem_rc
.bytes() == 0);
3165 aco_ptr
<Pseudo_instruction
> split
{create_instruction
<Pseudo_instruction
>(
3166 aco_opcode::p_split_vector
, Format::PSEUDO
, 1, tmp_size
/ elem_rc
.bytes())};
3167 for (unsigned i
= 0; i
< split
->definitions
.size(); i
++) {
3168 Temp component
= bld
.tmp(elem_rc
);
3169 allocated_vec
[components_split
++] = component
;
3170 split
->definitions
[i
] = Definition(component
);
3172 split
->operands
[0] = Operand(tmp
[0]);
3173 bld
.insert(std::move(split
));
3176 /* try to p_as_uniform early so we can create more optimizable code and
3177 * also update allocated_vec */
3178 for (unsigned j
= start
; j
< components_split
; j
++) {
3179 if (allocated_vec
[j
].bytes() % 4 == 0 && info
->dst
.type() == RegType::sgpr
)
3180 allocated_vec
[j
] = bld
.as_uniform(allocated_vec
[j
]);
3181 has_vgprs
|= allocated_vec
[j
].type() == RegType::vgpr
;
3185 /* concatenate components and p_as_uniform() result if needed */
3186 if (info
->dst
.type() == RegType::vgpr
|| !has_vgprs
)
3187 ctx
->allocated_vec
.emplace(info
->dst
.id(), allocated_vec
);
3189 int padding_bytes
= MAX2((int)info
->dst
.bytes() - int(allocated_vec
[0].bytes() * info
->num_components
), 0);
3191 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(
3192 aco_opcode::p_create_vector
, Format::PSEUDO
, info
->num_components
+ !!padding_bytes
, 1)};
3193 for (unsigned i
= 0; i
< info
->num_components
; i
++)
3194 vec
->operands
[i
] = Operand(allocated_vec
[i
]);
3196 vec
->operands
[info
->num_components
] = Operand(RegClass::get(RegType::vgpr
, padding_bytes
));
3197 if (info
->dst
.type() == RegType::sgpr
&& has_vgprs
) {
3198 Temp tmp
= bld
.tmp(RegType::vgpr
, info
->dst
.size());
3199 vec
->definitions
[0] = Definition(tmp
);
3200 bld
.insert(std::move(vec
));
3201 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(info
->dst
), tmp
);
3203 vec
->definitions
[0] = Definition(info
->dst
);
3204 bld
.insert(std::move(vec
));
3208 Operand
load_lds_size_m0(Builder
& bld
)
3210 /* TODO: m0 does not need to be initialized on GFX9+ */
3211 return bld
.m0((Temp
)bld
.sopk(aco_opcode::s_movk_i32
, bld
.def(s1
, m0
), 0xffff));
3214 Temp
lds_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3215 Temp offset
, unsigned bytes_needed
,
3216 unsigned align
, unsigned const_offset
,
3219 offset
= offset
.regClass() == s1
? bld
.copy(bld
.def(v1
), offset
) : offset
;
3221 Operand m
= load_lds_size_m0(bld
);
3223 bool large_ds_read
= bld
.program
->chip_class
>= GFX7
;
3224 bool usable_read2
= bld
.program
->chip_class
>= GFX7
;
3229 //TODO: use ds_read_u8_d16_hi/ds_read_u16_d16_hi if beneficial
3230 if (bytes_needed
>= 16 && align
% 16 == 0 && large_ds_read
) {
3232 op
= aco_opcode::ds_read_b128
;
3233 } else if (bytes_needed
>= 16 && align
% 8 == 0 && const_offset
% 8 == 0 && usable_read2
) {
3236 op
= aco_opcode::ds_read2_b64
;
3237 } else if (bytes_needed
>= 12 && align
% 16 == 0 && large_ds_read
) {
3239 op
= aco_opcode::ds_read_b96
;
3240 } else if (bytes_needed
>= 8 && align
% 8 == 0) {
3242 op
= aco_opcode::ds_read_b64
;
3243 } else if (bytes_needed
>= 8 && align
% 4 == 0 && const_offset
% 4 == 0) {
3246 op
= aco_opcode::ds_read2_b32
;
3247 } else if (bytes_needed
>= 4 && align
% 4 == 0) {
3249 op
= aco_opcode::ds_read_b32
;
3250 } else if (bytes_needed
>= 2 && align
% 2 == 0) {
3252 op
= aco_opcode::ds_read_u16
;
3255 op
= aco_opcode::ds_read_u8
;
3258 unsigned max_offset_plus_one
= read2
? 254 * (size
/ 2u) + 1 : 65536;
3259 if (const_offset
>= max_offset_plus_one
) {
3260 offset
= bld
.vadd32(bld
.def(v1
), offset
, Operand(const_offset
/ max_offset_plus_one
));
3261 const_offset
%= max_offset_plus_one
;
3265 const_offset
/= (size
/ 2u);
3267 RegClass rc
= RegClass(RegType::vgpr
, DIV_ROUND_UP(size
, 4));
3268 Temp val
= rc
== info
->dst
.regClass() && dst_hint
.id() ? dst_hint
: bld
.tmp(rc
);
3271 instr
= bld
.ds(op
, Definition(val
), offset
, m
, const_offset
, const_offset
+ 1);
3273 instr
= bld
.ds(op
, Definition(val
), offset
, m
, const_offset
);
3274 static_cast<DS_instruction
*>(instr
)->sync
= info
->sync
;
3277 val
= bld
.pseudo(aco_opcode::p_extract_vector
, bld
.def(RegClass::get(RegType::vgpr
, size
)), val
, Operand(0u));
3282 static auto emit_lds_load
= emit_load
<lds_load_callback
, false, true, UINT32_MAX
>;
3284 Temp
smem_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3285 Temp offset
, unsigned bytes_needed
,
3286 unsigned align
, unsigned const_offset
,
3291 if (bytes_needed
<= 4) {
3293 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dword
: aco_opcode::s_load_dword
;
3294 } else if (bytes_needed
<= 8) {
3296 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx2
: aco_opcode::s_load_dwordx2
;
3297 } else if (bytes_needed
<= 16) {
3299 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx4
: aco_opcode::s_load_dwordx4
;
3300 } else if (bytes_needed
<= 32) {
3302 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx8
: aco_opcode::s_load_dwordx8
;
3305 op
= info
->resource
.id() ? aco_opcode::s_buffer_load_dwordx16
: aco_opcode::s_load_dwordx16
;
3307 aco_ptr
<SMEM_instruction
> load
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 2, 1)};
3308 if (info
->resource
.id()) {
3309 load
->operands
[0] = Operand(info
->resource
);
3310 load
->operands
[1] = Operand(offset
);
3312 load
->operands
[0] = Operand(offset
);
3313 load
->operands
[1] = Operand(0u);
3315 RegClass
rc(RegType::sgpr
, size
);
3316 Temp val
= dst_hint
.id() && dst_hint
.regClass() == rc
? dst_hint
: bld
.tmp(rc
);
3317 load
->definitions
[0] = Definition(val
);
3318 load
->glc
= info
->glc
;
3319 load
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3320 load
->sync
= info
->sync
;
3321 bld
.insert(std::move(load
));
3325 static auto emit_smem_load
= emit_load
<smem_load_callback
, true, false, 1024>;
3327 Temp
mubuf_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3328 Temp offset
, unsigned bytes_needed
,
3329 unsigned align_
, unsigned const_offset
,
3332 Operand vaddr
= offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3333 Operand soffset
= offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
3335 if (info
->soffset
.id()) {
3336 if (soffset
.isTemp())
3337 vaddr
= bld
.copy(bld
.def(v1
), soffset
);
3338 soffset
= Operand(info
->soffset
);
3341 unsigned bytes_size
= 0;
3343 if (bytes_needed
== 1 || align_
% 2) {
3345 op
= aco_opcode::buffer_load_ubyte
;
3346 } else if (bytes_needed
== 2 || align_
% 4) {
3348 op
= aco_opcode::buffer_load_ushort
;
3349 } else if (bytes_needed
<= 4) {
3351 op
= aco_opcode::buffer_load_dword
;
3352 } else if (bytes_needed
<= 8) {
3354 op
= aco_opcode::buffer_load_dwordx2
;
3355 } else if (bytes_needed
<= 12 && bld
.program
->chip_class
> GFX6
) {
3357 op
= aco_opcode::buffer_load_dwordx3
;
3360 op
= aco_opcode::buffer_load_dwordx4
;
3362 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3363 mubuf
->operands
[0] = Operand(info
->resource
);
3364 mubuf
->operands
[1] = vaddr
;
3365 mubuf
->operands
[2] = soffset
;
3366 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
3367 mubuf
->glc
= info
->glc
;
3368 mubuf
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3369 mubuf
->sync
= info
->sync
;
3370 mubuf
->offset
= const_offset
;
3371 mubuf
->swizzled
= info
->swizzle_component_size
!= 0;
3372 RegClass rc
= RegClass::get(RegType::vgpr
, bytes_size
);
3373 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3374 mubuf
->definitions
[0] = Definition(val
);
3375 bld
.insert(std::move(mubuf
));
3380 static auto emit_mubuf_load
= emit_load
<mubuf_load_callback
, true, true, 4096>;
3381 static auto emit_scratch_load
= emit_load
<mubuf_load_callback
, false, true, 4096>;
3383 Temp
get_gfx6_global_rsrc(Builder
& bld
, Temp addr
)
3385 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3386 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3388 if (addr
.type() == RegType::vgpr
)
3389 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), Operand(0u), Operand(0u), Operand(-1u), Operand(rsrc_conf
));
3390 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), addr
, Operand(-1u), Operand(rsrc_conf
));
3393 Temp
global_load_callback(Builder
& bld
, const LoadEmitInfo
*info
,
3394 Temp offset
, unsigned bytes_needed
,
3395 unsigned align_
, unsigned const_offset
,
3398 unsigned bytes_size
= 0;
3399 bool mubuf
= bld
.program
->chip_class
== GFX6
;
3400 bool global
= bld
.program
->chip_class
>= GFX9
;
3402 if (bytes_needed
== 1) {
3404 op
= mubuf
? aco_opcode::buffer_load_ubyte
: global
? aco_opcode::global_load_ubyte
: aco_opcode::flat_load_ubyte
;
3405 } else if (bytes_needed
== 2) {
3407 op
= mubuf
? aco_opcode::buffer_load_ushort
: global
? aco_opcode::global_load_ushort
: aco_opcode::flat_load_ushort
;
3408 } else if (bytes_needed
<= 4) {
3410 op
= mubuf
? aco_opcode::buffer_load_dword
: global
? aco_opcode::global_load_dword
: aco_opcode::flat_load_dword
;
3411 } else if (bytes_needed
<= 8) {
3413 op
= mubuf
? aco_opcode::buffer_load_dwordx2
: global
? aco_opcode::global_load_dwordx2
: aco_opcode::flat_load_dwordx2
;
3414 } else if (bytes_needed
<= 12 && !mubuf
) {
3416 op
= global
? aco_opcode::global_load_dwordx3
: aco_opcode::flat_load_dwordx3
;
3419 op
= mubuf
? aco_opcode::buffer_load_dwordx4
: global
? aco_opcode::global_load_dwordx4
: aco_opcode::flat_load_dwordx4
;
3421 RegClass rc
= RegClass::get(RegType::vgpr
, align(bytes_size
, 4));
3422 Temp val
= dst_hint
.id() && rc
== dst_hint
.regClass() ? dst_hint
: bld
.tmp(rc
);
3424 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
3425 mubuf
->operands
[0] = Operand(get_gfx6_global_rsrc(bld
, offset
));
3426 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
3427 mubuf
->operands
[2] = Operand(0u);
3428 mubuf
->glc
= info
->glc
;
3431 mubuf
->addr64
= offset
.type() == RegType::vgpr
;
3432 mubuf
->disable_wqm
= false;
3433 mubuf
->sync
= info
->sync
;
3434 mubuf
->definitions
[0] = Definition(val
);
3435 bld
.insert(std::move(mubuf
));
3437 offset
= offset
.regClass() == s2
? bld
.copy(bld
.def(v2
), offset
) : offset
;
3439 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 2, 1)};
3440 flat
->operands
[0] = Operand(offset
);
3441 flat
->operands
[1] = Operand(s1
);
3442 flat
->glc
= info
->glc
;
3443 flat
->dlc
= info
->glc
&& bld
.program
->chip_class
>= GFX10
;
3444 flat
->sync
= info
->sync
;
3446 flat
->definitions
[0] = Definition(val
);
3447 bld
.insert(std::move(flat
));
3453 static auto emit_global_load
= emit_load
<global_load_callback
, true, true, 1>;
3455 Temp
load_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp dst
,
3456 Temp address
, unsigned base_offset
, unsigned align
)
3458 assert(util_is_power_of_two_nonzero(align
));
3460 Builder
bld(ctx
->program
, ctx
->block
);
3462 unsigned num_components
= dst
.bytes() / elem_size_bytes
;
3463 LoadEmitInfo info
= {Operand(as_vgpr(ctx
, address
)), dst
, num_components
, elem_size_bytes
};
3464 info
.align_mul
= align
;
3465 info
.align_offset
= 0;
3466 info
.sync
= memory_sync_info(storage_shared
);
3467 info
.const_offset
= base_offset
;
3468 emit_lds_load(ctx
, bld
, &info
);
3473 void split_store_data(isel_context
*ctx
, RegType dst_type
, unsigned count
, Temp
*dst
, unsigned *offsets
, Temp src
)
3478 Builder
bld(ctx
->program
, ctx
->block
);
3480 ASSERTED
bool is_subdword
= false;
3481 for (unsigned i
= 0; i
< count
; i
++)
3482 is_subdword
|= offsets
[i
] % 4;
3483 is_subdword
|= (src
.bytes() - offsets
[count
- 1]) % 4;
3484 assert(!is_subdword
|| dst_type
== RegType::vgpr
);
3486 /* count == 1 fast path */
3488 if (dst_type
== RegType::sgpr
)
3489 dst
[0] = bld
.as_uniform(src
);
3491 dst
[0] = as_vgpr(ctx
, src
);
3495 for (unsigned i
= 0; i
< count
- 1; i
++)
3496 dst
[i
] = bld
.tmp(RegClass::get(dst_type
, offsets
[i
+ 1] - offsets
[i
]));
3497 dst
[count
- 1] = bld
.tmp(RegClass::get(dst_type
, src
.bytes() - offsets
[count
- 1]));
3499 if (is_subdword
&& src
.type() == RegType::sgpr
) {
3500 src
= as_vgpr(ctx
, src
);
3502 /* use allocated_vec if possible */
3503 auto it
= ctx
->allocated_vec
.find(src
.id());
3504 if (it
!= ctx
->allocated_vec
.end()) {
3505 if (!it
->second
[0].id())
3507 unsigned elem_size
= it
->second
[0].bytes();
3508 assert(src
.bytes() % elem_size
== 0);
3510 for (unsigned i
= 0; i
< src
.bytes() / elem_size
; i
++) {
3511 if (!it
->second
[i
].id())
3515 for (unsigned i
= 0; i
< count
; i
++) {
3516 if (offsets
[i
] % elem_size
|| dst
[i
].bytes() % elem_size
)
3520 for (unsigned i
= 0; i
< count
; i
++) {
3521 unsigned start_idx
= offsets
[i
] / elem_size
;
3522 unsigned op_count
= dst
[i
].bytes() / elem_size
;
3523 if (op_count
== 1) {
3524 if (dst_type
== RegType::sgpr
)
3525 dst
[i
] = bld
.as_uniform(it
->second
[start_idx
]);
3527 dst
[i
] = as_vgpr(ctx
, it
->second
[start_idx
]);
3531 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, op_count
, 1)};
3532 for (unsigned j
= 0; j
< op_count
; j
++) {
3533 Temp tmp
= it
->second
[start_idx
+ j
];
3534 if (dst_type
== RegType::sgpr
)
3535 tmp
= bld
.as_uniform(tmp
);
3536 vec
->operands
[j
] = Operand(tmp
);
3538 vec
->definitions
[0] = Definition(dst
[i
]);
3539 bld
.insert(std::move(vec
));
3547 if (dst_type
== RegType::sgpr
)
3548 src
= bld
.as_uniform(src
);
3551 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
, Format::PSEUDO
, 1, count
)};
3552 split
->operands
[0] = Operand(src
);
3553 for (unsigned i
= 0; i
< count
; i
++)
3554 split
->definitions
[i
] = Definition(dst
[i
]);
3555 bld
.insert(std::move(split
));
3558 bool scan_write_mask(uint32_t mask
, uint32_t todo_mask
,
3559 int *start
, int *count
)
3561 unsigned start_elem
= ffs(todo_mask
) - 1;
3562 bool skip
= !(mask
& (1 << start_elem
));
3564 mask
= ~mask
& todo_mask
;
3568 u_bit_scan_consecutive_range(&mask
, start
, count
);
3573 void advance_write_mask(uint32_t *todo_mask
, int start
, int count
)
3575 *todo_mask
&= ~u_bit_consecutive(0, count
) << start
;
3578 void store_lds(isel_context
*ctx
, unsigned elem_size_bytes
, Temp data
, uint32_t wrmask
,
3579 Temp address
, unsigned base_offset
, unsigned align
)
3581 assert(util_is_power_of_two_nonzero(align
));
3582 assert(util_is_power_of_two_nonzero(elem_size_bytes
) && elem_size_bytes
<= 8);
3584 Builder
bld(ctx
->program
, ctx
->block
);
3585 bool large_ds_write
= ctx
->options
->chip_class
>= GFX7
;
3586 bool usable_write2
= ctx
->options
->chip_class
>= GFX7
;
3588 unsigned write_count
= 0;
3589 Temp write_datas
[32];
3590 unsigned offsets
[32];
3591 aco_opcode opcodes
[32];
3593 wrmask
= widen_mask(wrmask
, elem_size_bytes
);
3595 uint32_t todo
= u_bit_consecutive(0, data
.bytes());
3598 if (!scan_write_mask(wrmask
, todo
, &offset
, &bytes
)) {
3599 offsets
[write_count
] = offset
;
3600 opcodes
[write_count
] = aco_opcode::num_opcodes
;
3602 advance_write_mask(&todo
, offset
, bytes
);
3606 bool aligned2
= offset
% 2 == 0 && align
% 2 == 0;
3607 bool aligned4
= offset
% 4 == 0 && align
% 4 == 0;
3608 bool aligned8
= offset
% 8 == 0 && align
% 8 == 0;
3609 bool aligned16
= offset
% 16 == 0 && align
% 16 == 0;
3611 //TODO: use ds_write_b8_d16_hi/ds_write_b16_d16_hi if beneficial
3612 aco_opcode op
= aco_opcode::num_opcodes
;
3613 if (bytes
>= 16 && aligned16
&& large_ds_write
) {
3614 op
= aco_opcode::ds_write_b128
;
3616 } else if (bytes
>= 12 && aligned16
&& large_ds_write
) {
3617 op
= aco_opcode::ds_write_b96
;
3619 } else if (bytes
>= 8 && aligned8
) {
3620 op
= aco_opcode::ds_write_b64
;
3622 } else if (bytes
>= 4 && aligned4
) {
3623 op
= aco_opcode::ds_write_b32
;
3625 } else if (bytes
>= 2 && aligned2
) {
3626 op
= aco_opcode::ds_write_b16
;
3628 } else if (bytes
>= 1) {
3629 op
= aco_opcode::ds_write_b8
;
3635 offsets
[write_count
] = offset
;
3636 opcodes
[write_count
] = op
;
3638 advance_write_mask(&todo
, offset
, bytes
);
3641 Operand m
= load_lds_size_m0(bld
);
3643 split_store_data(ctx
, RegType::vgpr
, write_count
, write_datas
, offsets
, data
);
3645 for (unsigned i
= 0; i
< write_count
; i
++) {
3646 aco_opcode op
= opcodes
[i
];
3647 if (op
== aco_opcode::num_opcodes
)
3650 Temp data
= write_datas
[i
];
3652 unsigned second
= write_count
;
3653 if (usable_write2
&& (op
== aco_opcode::ds_write_b32
|| op
== aco_opcode::ds_write_b64
)) {
3654 for (second
= i
+ 1; second
< write_count
; second
++) {
3655 if (opcodes
[second
] == op
&& (offsets
[second
] - offsets
[i
]) % data
.bytes() == 0) {
3656 op
= data
.bytes() == 4 ? aco_opcode::ds_write2_b32
: aco_opcode::ds_write2_b64
;
3657 opcodes
[second
] = aco_opcode::num_opcodes
;
3663 bool write2
= op
== aco_opcode::ds_write2_b32
|| op
== aco_opcode::ds_write2_b64
;
3664 unsigned write2_off
= (offsets
[second
] - offsets
[i
]) / data
.bytes();
3666 unsigned inline_offset
= base_offset
+ offsets
[i
];
3667 unsigned max_offset
= write2
? (255 - write2_off
) * data
.bytes() : 65535;
3668 Temp address_offset
= address
;
3669 if (inline_offset
> max_offset
) {
3670 address_offset
= bld
.vadd32(bld
.def(v1
), Operand(base_offset
), address_offset
);
3671 inline_offset
= offsets
[i
];
3673 assert(inline_offset
<= max_offset
); /* offsets[i] shouldn't be large enough for this to happen */
3677 Temp second_data
= write_datas
[second
];
3678 inline_offset
/= data
.bytes();
3679 instr
= bld
.ds(op
, address_offset
, data
, second_data
, m
, inline_offset
, inline_offset
+ write2_off
);
3681 instr
= bld
.ds(op
, address_offset
, data
, m
, inline_offset
);
3683 static_cast<DS_instruction
*>(instr
)->sync
=
3684 memory_sync_info(storage_shared
);
3688 unsigned calculate_lds_alignment(isel_context
*ctx
, unsigned const_offset
)
3690 unsigned align
= 16;
3692 align
= std::min(align
, 1u << (ffs(const_offset
) - 1));
3698 aco_opcode
get_buffer_store_op(bool smem
, unsigned bytes
)
3703 return aco_opcode::buffer_store_byte
;
3706 return aco_opcode::buffer_store_short
;
3708 return smem
? aco_opcode::s_buffer_store_dword
: aco_opcode::buffer_store_dword
;
3710 return smem
? aco_opcode::s_buffer_store_dwordx2
: aco_opcode::buffer_store_dwordx2
;
3713 return aco_opcode::buffer_store_dwordx3
;
3715 return smem
? aco_opcode::s_buffer_store_dwordx4
: aco_opcode::buffer_store_dwordx4
;
3717 unreachable("Unexpected store size");
3718 return aco_opcode::num_opcodes
;
3721 void split_buffer_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool smem
, RegType dst_type
,
3722 Temp data
, unsigned writemask
, int swizzle_element_size
,
3723 unsigned *write_count
, Temp
*write_datas
, unsigned *offsets
)
3725 unsigned write_count_with_skips
= 0;
3728 /* determine how to split the data */
3729 unsigned todo
= u_bit_consecutive(0, data
.bytes());
3732 skips
[write_count_with_skips
] = !scan_write_mask(writemask
, todo
, &offset
, &bytes
);
3733 offsets
[write_count_with_skips
] = offset
;
3734 if (skips
[write_count_with_skips
]) {
3735 advance_write_mask(&todo
, offset
, bytes
);
3736 write_count_with_skips
++;
3740 /* only supported sizes are 1, 2, 4, 8, 12 and 16 bytes and can't be
3741 * larger than swizzle_element_size */
3742 bytes
= MIN2(bytes
, swizzle_element_size
);
3744 bytes
= bytes
> 4 ? bytes
& ~0x3 : MIN2(bytes
, 2);
3746 /* SMEM and GFX6 VMEM can't emit 12-byte stores */
3747 if ((ctx
->program
->chip_class
== GFX6
|| smem
) && bytes
== 12)
3750 /* dword or larger stores have to be dword-aligned */
3751 unsigned align_mul
= instr
? nir_intrinsic_align_mul(instr
) : 4;
3752 unsigned align_offset
= (instr
? nir_intrinsic_align_offset(instr
) : 0) + offset
;
3753 bool dword_aligned
= align_offset
% 4 == 0 && align_mul
% 4 == 0;
3755 bytes
= MIN2(bytes
, (align_offset
% 2 == 0 && align_mul
% 2 == 0) ? 2 : 1);
3757 advance_write_mask(&todo
, offset
, bytes
);
3758 write_count_with_skips
++;
3761 /* actually split data */
3762 split_store_data(ctx
, dst_type
, write_count_with_skips
, write_datas
, offsets
, data
);
3765 for (unsigned i
= 0; i
< write_count_with_skips
; i
++) {
3768 write_datas
[*write_count
] = write_datas
[i
];
3769 offsets
[*write_count
] = offsets
[i
];
3774 Temp
create_vec_from_array(isel_context
*ctx
, Temp arr
[], unsigned cnt
, RegType reg_type
, unsigned elem_size_bytes
,
3775 unsigned split_cnt
= 0u, Temp dst
= Temp())
3777 Builder
bld(ctx
->program
, ctx
->block
);
3778 unsigned dword_size
= elem_size_bytes
/ 4;
3781 dst
= bld
.tmp(RegClass(reg_type
, cnt
* dword_size
));
3783 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> allocated_vec
;
3784 aco_ptr
<Pseudo_instruction
> instr
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, cnt
, 1)};
3785 instr
->definitions
[0] = Definition(dst
);
3787 for (unsigned i
= 0; i
< cnt
; ++i
) {
3789 assert(arr
[i
].size() == dword_size
);
3790 allocated_vec
[i
] = arr
[i
];
3791 instr
->operands
[i
] = Operand(arr
[i
]);
3793 Temp zero
= bld
.copy(bld
.def(RegClass(reg_type
, dword_size
)), Operand(0u, dword_size
== 2));
3794 allocated_vec
[i
] = zero
;
3795 instr
->operands
[i
] = Operand(zero
);
3799 bld
.insert(std::move(instr
));
3802 emit_split_vector(ctx
, dst
, split_cnt
);
3804 ctx
->allocated_vec
.emplace(dst
.id(), allocated_vec
); /* emit_split_vector already does this */
3809 inline unsigned resolve_excess_vmem_const_offset(Builder
&bld
, Temp
&voffset
, unsigned const_offset
)
3811 if (const_offset
>= 4096) {
3812 unsigned excess_const_offset
= const_offset
/ 4096u * 4096u;
3813 const_offset
%= 4096u;
3816 voffset
= bld
.copy(bld
.def(v1
), Operand(excess_const_offset
));
3817 else if (unlikely(voffset
.regClass() == s1
))
3818 voffset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(excess_const_offset
), Operand(voffset
));
3819 else if (likely(voffset
.regClass() == v1
))
3820 voffset
= bld
.vadd32(bld
.def(v1
), Operand(voffset
), Operand(excess_const_offset
));
3822 unreachable("Unsupported register class of voffset");
3825 return const_offset
;
3828 void emit_single_mubuf_store(isel_context
*ctx
, Temp descriptor
, Temp voffset
, Temp soffset
, Temp vdata
,
3829 unsigned const_offset
= 0u, memory_sync_info sync
=memory_sync_info(),
3830 bool slc
= false, bool swizzled
= false)
3833 assert(vdata
.size() != 3 || ctx
->program
->chip_class
!= GFX6
);
3834 assert(vdata
.size() >= 1 && vdata
.size() <= 4);
3836 Builder
bld(ctx
->program
, ctx
->block
);
3837 aco_opcode op
= get_buffer_store_op(false, vdata
.bytes());
3838 const_offset
= resolve_excess_vmem_const_offset(bld
, voffset
, const_offset
);
3840 Operand voffset_op
= voffset
.id() ? Operand(as_vgpr(ctx
, voffset
)) : Operand(v1
);
3841 Operand soffset_op
= soffset
.id() ? Operand(soffset
) : Operand(0u);
3842 Builder::Result r
= bld
.mubuf(op
, Operand(descriptor
), voffset_op
, soffset_op
, Operand(vdata
), const_offset
,
3843 /* offen */ !voffset_op
.isUndefined(), /* swizzled */ swizzled
,
3844 /* idxen*/ false, /* addr64 */ false, /* disable_wqm */ false, /* glc */ true,
3845 /* dlc*/ false, /* slc */ slc
);
3847 static_cast<MUBUF_instruction
*>(r
.instr
)->sync
= sync
;
3850 void store_vmem_mubuf(isel_context
*ctx
, Temp src
, Temp descriptor
, Temp voffset
, Temp soffset
,
3851 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned write_mask
,
3852 bool allow_combining
= true, memory_sync_info sync
=memory_sync_info(), bool slc
= false)
3854 Builder
bld(ctx
->program
, ctx
->block
);
3855 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3857 write_mask
= widen_mask(write_mask
, elem_size_bytes
);
3859 unsigned write_count
= 0;
3860 Temp write_datas
[32];
3861 unsigned offsets
[32];
3862 split_buffer_store(ctx
, NULL
, false, RegType::vgpr
, src
, write_mask
,
3863 allow_combining
? 16 : 4, &write_count
, write_datas
, offsets
);
3865 for (unsigned i
= 0; i
< write_count
; i
++) {
3866 unsigned const_offset
= offsets
[i
] + base_const_offset
;
3867 emit_single_mubuf_store(ctx
, descriptor
, voffset
, soffset
, write_datas
[i
], const_offset
, sync
, slc
, !allow_combining
);
3871 void load_vmem_mubuf(isel_context
*ctx
, Temp dst
, Temp descriptor
, Temp voffset
, Temp soffset
,
3872 unsigned base_const_offset
, unsigned elem_size_bytes
, unsigned num_components
,
3873 unsigned stride
= 0u, bool allow_combining
= true, bool allow_reorder
= true)
3875 assert(elem_size_bytes
== 2 || elem_size_bytes
== 4 || elem_size_bytes
== 8);
3876 assert((num_components
* elem_size_bytes
) == dst
.bytes());
3877 assert(!!stride
!= allow_combining
);
3879 Builder
bld(ctx
->program
, ctx
->block
);
3881 LoadEmitInfo info
= {Operand(voffset
), dst
, num_components
, elem_size_bytes
, descriptor
};
3882 info
.component_stride
= allow_combining
? 0 : stride
;
3884 info
.swizzle_component_size
= allow_combining
? 0 : 4;
3885 info
.align_mul
= MIN2(elem_size_bytes
, 4);
3886 info
.align_offset
= 0;
3887 info
.soffset
= soffset
;
3888 info
.const_offset
= base_const_offset
;
3889 emit_mubuf_load(ctx
, bld
, &info
);
3892 std::pair
<Temp
, unsigned> offset_add_from_nir(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &base_offset
, nir_src
*off_src
, unsigned stride
= 1u)
3894 Builder
bld(ctx
->program
, ctx
->block
);
3895 Temp offset
= base_offset
.first
;
3896 unsigned const_offset
= base_offset
.second
;
3898 if (!nir_src_is_const(*off_src
)) {
3899 Temp indirect_offset_arg
= get_ssa_temp(ctx
, off_src
->ssa
);
3902 /* Calculate indirect offset with stride */
3903 if (likely(indirect_offset_arg
.regClass() == v1
))
3904 with_stride
= bld
.v_mul24_imm(bld
.def(v1
), indirect_offset_arg
, stride
);
3905 else if (indirect_offset_arg
.regClass() == s1
)
3906 with_stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), indirect_offset_arg
);
3908 unreachable("Unsupported register class of indirect offset");
3910 /* Add to the supplied base offset */
3911 if (offset
.id() == 0)
3912 offset
= with_stride
;
3913 else if (unlikely(offset
.regClass() == s1
&& with_stride
.regClass() == s1
))
3914 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), with_stride
, offset
);
3915 else if (offset
.size() == 1 && with_stride
.size() == 1)
3916 offset
= bld
.vadd32(bld
.def(v1
), with_stride
, offset
);
3918 unreachable("Unsupported register class of indirect offset");
3920 unsigned const_offset_arg
= nir_src_as_uint(*off_src
);
3921 const_offset
+= const_offset_arg
* stride
;
3924 return std::make_pair(offset
, const_offset
);
3927 std::pair
<Temp
, unsigned> offset_add(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &off1
, const std::pair
<Temp
, unsigned> &off2
)
3929 Builder
bld(ctx
->program
, ctx
->block
);
3932 if (off1
.first
.id() && off2
.first
.id()) {
3933 if (unlikely(off1
.first
.regClass() == s1
&& off2
.first
.regClass() == s1
))
3934 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), off1
.first
, off2
.first
);
3935 else if (off1
.first
.size() == 1 && off2
.first
.size() == 1)
3936 offset
= bld
.vadd32(bld
.def(v1
), off1
.first
, off2
.first
);
3938 unreachable("Unsupported register class of indirect offset");
3940 offset
= off1
.first
.id() ? off1
.first
: off2
.first
;
3943 return std::make_pair(offset
, off1
.second
+ off2
.second
);
3946 std::pair
<Temp
, unsigned> offset_mul(isel_context
*ctx
, const std::pair
<Temp
, unsigned> &offs
, unsigned multiplier
)
3948 Builder
bld(ctx
->program
, ctx
->block
);
3949 unsigned const_offset
= offs
.second
* multiplier
;
3951 if (!offs
.first
.id())
3952 return std::make_pair(offs
.first
, const_offset
);
3954 Temp offset
= unlikely(offs
.first
.regClass() == s1
)
3955 ? bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(multiplier
), offs
.first
)
3956 : bld
.v_mul24_imm(bld
.def(v1
), offs
.first
, multiplier
);
3958 return std::make_pair(offset
, const_offset
);
3961 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
, unsigned component_stride
)
3963 Builder
bld(ctx
->program
, ctx
->block
);
3965 /* base is the driver_location, which is already multiplied by 4, so is in dwords */
3966 unsigned const_offset
= nir_intrinsic_base(instr
) * base_stride
;
3967 /* component is in bytes */
3968 const_offset
+= nir_intrinsic_component(instr
) * component_stride
;
3970 /* offset should be interpreted in relation to the base, so the instruction effectively reads/writes another input/output when it has an offset */
3971 nir_src
*off_src
= nir_get_io_offset_src(instr
);
3972 return offset_add_from_nir(ctx
, std::make_pair(Temp(), const_offset
), off_src
, 4u * base_stride
);
3975 std::pair
<Temp
, unsigned> get_intrinsic_io_basic_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned stride
= 1u)
3977 return get_intrinsic_io_basic_offset(ctx
, instr
, stride
, stride
);
3980 Temp
get_tess_rel_patch_id(isel_context
*ctx
)
3982 Builder
bld(ctx
->program
, ctx
->block
);
3984 switch (ctx
->shader
->info
.stage
) {
3985 case MESA_SHADER_TESS_CTRL
:
3986 return bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffu
),
3987 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
));
3988 case MESA_SHADER_TESS_EVAL
:
3989 return get_arg(ctx
, ctx
->args
->tes_rel_patch_id
);
3991 unreachable("Unsupported stage in get_tess_rel_patch_id");
3995 std::pair
<Temp
, unsigned> get_tcs_per_vertex_input_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
3997 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
3998 Builder
bld(ctx
->program
, ctx
->block
);
4000 uint32_t tcs_in_patch_stride
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 4;
4001 uint32_t tcs_in_vertex_stride
= ctx
->tcs_num_inputs
* 4;
4003 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
);
4005 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4006 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, tcs_in_vertex_stride
);
4008 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4009 Temp tcs_in_current_patch_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, tcs_in_patch_stride
);
4010 offs
= offset_add(ctx
, offs
, std::make_pair(tcs_in_current_patch_offset
, 0));
4012 return offset_mul(ctx
, offs
, 4u);
4015 std::pair
<Temp
, unsigned> get_tcs_output_lds_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, bool per_vertex
= false)
4017 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4018 Builder
bld(ctx
->program
, ctx
->block
);
4020 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* ctx
->tcs_num_inputs
* 16;
4021 uint32_t output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4022 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4023 uint32_t output_patch_stride
= pervertex_output_patch_size
+ ctx
->tcs_num_patch_outputs
* 16;
4025 std::pair
<Temp
, unsigned> offs
= instr
4026 ? get_intrinsic_io_basic_offset(ctx
, instr
, 4u)
4027 : std::make_pair(Temp(), 0u);
4029 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4030 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, output_patch_stride
);
4035 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4036 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, output_vertex_size
);
4038 uint32_t output_patch0_offset
= (input_patch_size
* ctx
->tcs_num_patches
);
4039 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_offset
));
4041 uint32_t output_patch0_patch_data_offset
= (input_patch_size
* ctx
->tcs_num_patches
+ pervertex_output_patch_size
);
4042 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, output_patch0_patch_data_offset
));
4048 std::pair
<Temp
, unsigned> get_tcs_per_vertex_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4050 Builder
bld(ctx
->program
, ctx
->block
);
4052 unsigned vertices_per_patch
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
4053 unsigned attr_stride
= vertices_per_patch
* ctx
->tcs_num_patches
;
4055 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u);
4057 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4058 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, vertices_per_patch
* 16u);
4059 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, 0u));
4061 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4062 offs
= offset_add_from_nir(ctx
, offs
, vertex_index_src
, 16u);
4067 std::pair
<Temp
, unsigned> get_tcs_per_patch_output_vmem_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
= nullptr, unsigned const_base_offset
= 0u)
4069 Builder
bld(ctx
->program
, ctx
->block
);
4071 unsigned output_vertex_size
= ctx
->tcs_num_outputs
* 16;
4072 unsigned per_vertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
4073 unsigned per_patch_data_offset
= per_vertex_output_patch_size
* ctx
->tcs_num_patches
;
4074 unsigned attr_stride
= ctx
->tcs_num_patches
;
4076 std::pair
<Temp
, unsigned> offs
= instr
4077 ? get_intrinsic_io_basic_offset(ctx
, instr
, attr_stride
* 4u, 4u)
4078 : std::make_pair(Temp(), 0u);
4080 if (const_base_offset
)
4081 offs
.second
+= const_base_offset
* attr_stride
;
4083 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
4084 Temp patch_off
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, 16u);
4085 offs
= offset_add(ctx
, offs
, std::make_pair(patch_off
, per_patch_data_offset
));
4090 bool tcs_driver_location_matches_api_mask(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
, uint64_t mask
, bool *indirect
)
4092 assert(per_vertex
|| ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4097 unsigned drv_loc
= nir_intrinsic_base(instr
);
4098 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4100 if (!nir_src_is_const(*off_src
)) {
4106 uint64_t slot
= per_vertex
4107 ? ctx
->output_drv_loc_to_var_slot
[ctx
->shader
->info
.stage
][drv_loc
/ 4]
4108 : (ctx
->output_tcs_patch_drv_loc_to_var_slot
[drv_loc
/ 4] - VARYING_SLOT_PATCH0
);
4109 return (((uint64_t) 1) << slot
) & mask
;
4112 bool store_output_to_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4114 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4115 unsigned component
= nir_intrinsic_component(instr
);
4116 unsigned idx
= nir_intrinsic_base(instr
) + component
;
4118 nir_instr
*off_instr
= instr
->src
[1].ssa
->parent_instr
;
4119 if (off_instr
->type
!= nir_instr_type_load_const
)
4122 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4123 idx
+= nir_src_as_uint(instr
->src
[1]) * 4u;
4125 if (instr
->src
[0].ssa
->bit_size
== 64)
4126 write_mask
= widen_mask(write_mask
, 2);
4128 RegClass rc
= instr
->src
[0].ssa
->bit_size
== 16 ? v2b
: v1
;
4130 for (unsigned i
= 0; i
< 8; ++i
) {
4131 if (write_mask
& (1 << i
)) {
4132 ctx
->outputs
.mask
[idx
/ 4u] |= 1 << (idx
% 4u);
4133 ctx
->outputs
.temps
[idx
] = emit_extract_vector(ctx
, src
, i
, rc
);
4141 bool load_input_from_temps(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp dst
)
4143 /* Only TCS per-vertex inputs are supported by this function.
4144 * Per-vertex inputs only match between the VS/TCS invocation id when the number of invocations is the same.
4146 if (ctx
->shader
->info
.stage
!= MESA_SHADER_TESS_CTRL
|| !ctx
->tcs_in_out_eq
)
4149 nir_src
*off_src
= nir_get_io_offset_src(instr
);
4150 nir_src
*vertex_index_src
= nir_get_io_vertex_index_src(instr
);
4151 nir_instr
*vertex_index_instr
= vertex_index_src
->ssa
->parent_instr
;
4152 bool can_use_temps
= nir_src_is_const(*off_src
) &&
4153 vertex_index_instr
->type
== nir_instr_type_intrinsic
&&
4154 nir_instr_as_intrinsic(vertex_index_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
;
4159 unsigned idx
= nir_intrinsic_base(instr
) + nir_intrinsic_component(instr
) + 4 * nir_src_as_uint(*off_src
);
4160 Temp
*src
= &ctx
->inputs
.temps
[idx
];
4161 create_vec_from_array(ctx
, src
, dst
.size(), dst
.regClass().type(), 4u, 0, dst
);
4166 void visit_store_ls_or_es_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4168 Builder
bld(ctx
->program
, ctx
->block
);
4170 if (ctx
->tcs_in_out_eq
&& store_output_to_temps(ctx
, instr
)) {
4171 /* When the TCS only reads this output directly and for the same vertices as its invocation id, it is unnecessary to store the VS output to LDS. */
4172 bool indirect_write
;
4173 bool temp_only_input
= tcs_driver_location_matches_api_mask(ctx
, instr
, true, ctx
->tcs_temp_only_inputs
, &indirect_write
);
4174 if (temp_only_input
&& !indirect_write
)
4178 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, 4u);
4179 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4180 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4181 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8u;
4183 if (ctx
->stage
== vertex_es
|| ctx
->stage
== tess_eval_es
) {
4184 /* GFX6-8: ES stage is not merged into GS, data is passed from ES to GS in VMEM. */
4185 Temp esgs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_VS
* 16u));
4186 Temp es2gs_offset
= get_arg(ctx
, ctx
->args
->es2gs_offset
);
4187 store_vmem_mubuf(ctx
, src
, esgs_ring
, offs
.first
, es2gs_offset
, offs
.second
, elem_size_bytes
, write_mask
, false, memory_sync_info(), true);
4191 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4192 /* GFX9+: ES stage is merged into GS, data is passed between them using LDS. */
4193 unsigned itemsize
= ctx
->stage
== vertex_geometry_gs
4194 ? ctx
->program
->info
->vs
.es_info
.esgs_itemsize
4195 : ctx
->program
->info
->tes
.es_info
.esgs_itemsize
;
4196 Temp thread_id
= emit_mbcnt(ctx
, bld
.def(v1
));
4197 Temp wave_idx
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(4u << 16 | 24));
4198 Temp vertex_idx
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), thread_id
,
4199 bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_idx
), ctx
->program
->wave_size
));
4200 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, itemsize
);
4201 } else if (ctx
->stage
== vertex_ls
|| ctx
->stage
== vertex_tess_control_hs
) {
4202 /* GFX6-8: VS runs on LS stage when tessellation is used, but LS shares LDS space with HS.
4203 * GFX9+: LS is merged into HS, but still uses the same LDS layout.
4205 Temp vertex_idx
= get_arg(ctx
, ctx
->args
->rel_auto_id
);
4206 lds_base
= bld
.v_mul24_imm(bld
.def(v1
), vertex_idx
, ctx
->tcs_num_inputs
* 16u);
4208 unreachable("Invalid LS or ES stage");
4211 offs
= offset_add(ctx
, offs
, std::make_pair(lds_base
, 0u));
4212 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4213 store_lds(ctx
, elem_size_bytes
, src
, write_mask
, offs
.first
, offs
.second
, lds_align
);
4217 bool tcs_output_is_tess_factor(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4222 unsigned off
= nir_intrinsic_base(instr
) * 4u;
4223 return off
== ctx
->tcs_tess_lvl_out_loc
||
4224 off
== ctx
->tcs_tess_lvl_in_loc
;
4228 bool tcs_output_is_read_by_tes(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4230 uint64_t mask
= per_vertex
4231 ? ctx
->program
->info
->tcs
.tes_inputs_read
4232 : ctx
->program
->info
->tcs
.tes_patch_inputs_read
;
4234 bool indirect_write
= false;
4235 bool output_read_by_tes
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4236 return indirect_write
|| output_read_by_tes
;
4239 bool tcs_output_is_read_by_tcs(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4241 uint64_t mask
= per_vertex
4242 ? ctx
->shader
->info
.outputs_read
4243 : ctx
->shader
->info
.patch_outputs_read
;
4245 bool indirect_write
= false;
4246 bool output_read
= tcs_driver_location_matches_api_mask(ctx
, instr
, per_vertex
, mask
, &indirect_write
);
4247 return indirect_write
|| output_read
;
4250 void visit_store_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4252 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4253 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4255 Builder
bld(ctx
->program
, ctx
->block
);
4257 Temp store_val
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4258 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4259 unsigned write_mask
= nir_intrinsic_write_mask(instr
);
4261 bool is_tess_factor
= tcs_output_is_tess_factor(ctx
, instr
, per_vertex
);
4262 bool write_to_vmem
= !is_tess_factor
&& tcs_output_is_read_by_tes(ctx
, instr
, per_vertex
);
4263 bool write_to_lds
= is_tess_factor
|| tcs_output_is_read_by_tcs(ctx
, instr
, per_vertex
);
4265 if (write_to_vmem
) {
4266 std::pair
<Temp
, unsigned> vmem_offs
= per_vertex
4267 ? get_tcs_per_vertex_output_vmem_offset(ctx
, instr
)
4268 : get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4270 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4271 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4272 store_vmem_mubuf(ctx
, store_val
, hs_ring_tess_offchip
, vmem_offs
.first
, oc_lds
, vmem_offs
.second
, elem_size_bytes
, write_mask
, true, memory_sync_info(storage_vmem_output
));
4276 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4277 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4278 store_lds(ctx
, elem_size_bytes
, store_val
, write_mask
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4282 void visit_load_tcs_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
, bool per_vertex
)
4284 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4285 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4287 Builder
bld(ctx
->program
, ctx
->block
);
4289 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4290 std::pair
<Temp
, unsigned> lds_offs
= get_tcs_output_lds_offset(ctx
, instr
, per_vertex
);
4291 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_offs
.second
);
4292 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
4294 load_lds(ctx
, elem_size_bytes
, dst
, lds_offs
.first
, lds_offs
.second
, lds_align
);
4297 void visit_store_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4299 if (ctx
->stage
== vertex_vs
||
4300 ctx
->stage
== tess_eval_vs
||
4301 ctx
->stage
== fragment_fs
||
4302 ctx
->stage
== ngg_vertex_gs
||
4303 ctx
->stage
== ngg_tess_eval_gs
||
4304 ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
4305 bool stored_to_temps
= store_output_to_temps(ctx
, instr
);
4306 if (!stored_to_temps
) {
4307 isel_err(instr
->src
[1].ssa
->parent_instr
, "Unimplemented output offset instruction");
4310 } else if (ctx
->stage
== vertex_es
||
4311 ctx
->stage
== vertex_ls
||
4312 ctx
->stage
== tess_eval_es
||
4313 (ctx
->stage
== vertex_tess_control_hs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4314 (ctx
->stage
== vertex_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) ||
4315 (ctx
->stage
== tess_eval_geometry_gs
&& ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
)) {
4316 visit_store_ls_or_es_output(ctx
, instr
);
4317 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4318 visit_store_tcs_output(ctx
, instr
, false);
4320 unreachable("Shader stage not implemented");
4324 void visit_load_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4326 visit_load_tcs_output(ctx
, instr
, false);
4329 void emit_interp_instr(isel_context
*ctx
, unsigned idx
, unsigned component
, Temp src
, Temp dst
, Temp prim_mask
)
4331 Temp coord1
= emit_extract_vector(ctx
, src
, 0, v1
);
4332 Temp coord2
= emit_extract_vector(ctx
, src
, 1, v1
);
4334 Builder
bld(ctx
->program
, ctx
->block
);
4336 if (dst
.regClass() == v2b
) {
4337 if (ctx
->program
->has_16bank_lds
) {
4338 assert(ctx
->options
->chip_class
<= GFX8
);
4339 Builder::Result interp_p1
=
4340 bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
),
4341 Operand(2u) /* P0 */, bld
.m0(prim_mask
), idx
, component
);
4342 interp_p1
= bld
.vintrp(aco_opcode::v_interp_p1lv_f16
, bld
.def(v2b
),
4343 coord1
, bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4344 bld
.vintrp(aco_opcode::v_interp_p2_legacy_f16
, Definition(dst
), coord2
,
4345 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4347 aco_opcode interp_p2_op
= aco_opcode::v_interp_p2_f16
;
4349 if (ctx
->options
->chip_class
== GFX8
)
4350 interp_p2_op
= aco_opcode::v_interp_p2_legacy_f16
;
4352 Builder::Result interp_p1
=
4353 bld
.vintrp(aco_opcode::v_interp_p1ll_f16
, bld
.def(v1
),
4354 coord1
, bld
.m0(prim_mask
), idx
, component
);
4355 bld
.vintrp(interp_p2_op
, Definition(dst
), coord2
, bld
.m0(prim_mask
),
4356 interp_p1
, idx
, component
);
4359 Builder::Result interp_p1
=
4360 bld
.vintrp(aco_opcode::v_interp_p1_f32
, bld
.def(v1
), coord1
,
4361 bld
.m0(prim_mask
), idx
, component
);
4363 if (ctx
->program
->has_16bank_lds
)
4364 interp_p1
.instr
->operands
[0].setLateKill(true);
4366 bld
.vintrp(aco_opcode::v_interp_p2_f32
, Definition(dst
), coord2
,
4367 bld
.m0(prim_mask
), interp_p1
, idx
, component
);
4371 void emit_load_frag_coord(isel_context
*ctx
, Temp dst
, unsigned num_components
)
4373 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1));
4374 for (unsigned i
= 0; i
< num_components
; i
++)
4375 vec
->operands
[i
] = Operand(get_arg(ctx
, ctx
->args
->ac
.frag_pos
[i
]));
4376 if (G_0286CC_POS_W_FLOAT_ENA(ctx
->program
->config
->spi_ps_input_ena
)) {
4377 assert(num_components
== 4);
4378 Builder
bld(ctx
->program
, ctx
->block
);
4379 vec
->operands
[3] = bld
.vop1(aco_opcode::v_rcp_f32
, bld
.def(v1
), get_arg(ctx
, ctx
->args
->ac
.frag_pos
[3]));
4382 for (Operand
& op
: vec
->operands
)
4383 op
= op
.isUndefined() ? Operand(0u) : op
;
4385 vec
->definitions
[0] = Definition(dst
);
4386 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4387 emit_split_vector(ctx
, dst
, num_components
);
4391 void visit_load_interpolated_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4393 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4394 Temp coords
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4395 unsigned idx
= nir_intrinsic_base(instr
);
4396 unsigned component
= nir_intrinsic_component(instr
);
4397 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4399 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[1]);
4401 assert(offset
->u32
== 0);
4403 /* the lower 15bit of the prim_mask contain the offset into LDS
4404 * while the upper bits contain the number of prims */
4405 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
4406 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4407 Builder
bld(ctx
->program
, ctx
->block
);
4408 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4409 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4410 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4411 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4412 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4415 if (instr
->dest
.ssa
.num_components
== 1) {
4416 emit_interp_instr(ctx
, idx
, component
, coords
, dst
, prim_mask
);
4418 aco_ptr
<Pseudo_instruction
> vec(create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, instr
->dest
.ssa
.num_components
, 1));
4419 for (unsigned i
= 0; i
< instr
->dest
.ssa
.num_components
; i
++)
4421 Temp tmp
= {ctx
->program
->allocateId(), v1
};
4422 emit_interp_instr(ctx
, idx
, component
+i
, coords
, tmp
, prim_mask
);
4423 vec
->operands
[i
] = Operand(tmp
);
4425 vec
->definitions
[0] = Definition(dst
);
4426 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4430 bool check_vertex_fetch_size(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4431 unsigned offset
, unsigned stride
, unsigned channels
)
4433 unsigned vertex_byte_size
= vtx_info
->chan_byte_size
* channels
;
4434 if (vtx_info
->chan_byte_size
!= 4 && channels
== 3)
4436 return (ctx
->options
->chip_class
!= GFX6
&& ctx
->options
->chip_class
!= GFX10
) ||
4437 (offset
% vertex_byte_size
== 0 && stride
% vertex_byte_size
== 0);
4440 uint8_t get_fetch_data_format(isel_context
*ctx
, const ac_data_format_info
*vtx_info
,
4441 unsigned offset
, unsigned stride
, unsigned *channels
)
4443 if (!vtx_info
->chan_byte_size
) {
4444 *channels
= vtx_info
->num_channels
;
4445 return vtx_info
->chan_format
;
4448 unsigned num_channels
= *channels
;
4449 if (!check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, *channels
)) {
4450 unsigned new_channels
= num_channels
+ 1;
4451 /* first, assume more loads is worse and try using a larger data format */
4452 while (new_channels
<= 4 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
)) {
4454 /* don't make the attribute potentially out-of-bounds */
4455 if (offset
+ new_channels
* vtx_info
->chan_byte_size
> stride
)
4459 if (new_channels
== 5) {
4460 /* then try decreasing load size (at the cost of more loads) */
4461 new_channels
= *channels
;
4462 while (new_channels
> 1 && !check_vertex_fetch_size(ctx
, vtx_info
, offset
, stride
, new_channels
))
4466 if (new_channels
< *channels
)
4467 *channels
= new_channels
;
4468 num_channels
= new_channels
;
4471 switch (vtx_info
->chan_format
) {
4472 case V_008F0C_BUF_DATA_FORMAT_8
:
4473 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_8
, V_008F0C_BUF_DATA_FORMAT_8_8
,
4474 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_8_8_8_8
}[num_channels
- 1];
4475 case V_008F0C_BUF_DATA_FORMAT_16
:
4476 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_16
, V_008F0C_BUF_DATA_FORMAT_16_16
,
4477 V_008F0C_BUF_DATA_FORMAT_INVALID
, V_008F0C_BUF_DATA_FORMAT_16_16_16_16
}[num_channels
- 1];
4478 case V_008F0C_BUF_DATA_FORMAT_32
:
4479 return (uint8_t[]){V_008F0C_BUF_DATA_FORMAT_32
, V_008F0C_BUF_DATA_FORMAT_32_32
,
4480 V_008F0C_BUF_DATA_FORMAT_32_32_32
, V_008F0C_BUF_DATA_FORMAT_32_32_32_32
}[num_channels
- 1];
4482 unreachable("shouldn't reach here");
4483 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
4486 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
4487 * so we may need to fix it up. */
4488 Temp
adjust_vertex_fetch_alpha(isel_context
*ctx
, unsigned adjustment
, Temp alpha
)
4490 Builder
bld(ctx
->program
, ctx
->block
);
4492 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
4493 alpha
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), alpha
);
4495 /* For the integer-like cases, do a natural sign extension.
4497 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
4498 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
4501 alpha
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(adjustment
== RADV_ALPHA_ADJUST_SNORM
? 7u : 30u), alpha
);
4502 alpha
= bld
.vop2(aco_opcode::v_ashrrev_i32
, bld
.def(v1
), Operand(30u), alpha
);
4504 /* Convert back to the right type. */
4505 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
4506 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4507 Temp clamp
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0xbf800000u
), alpha
);
4508 alpha
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0xbf800000u
), alpha
, clamp
);
4509 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
4510 alpha
= bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), alpha
);
4516 void visit_load_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4518 Builder
bld(ctx
->program
, ctx
->block
);
4519 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4520 if (ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
) {
4522 nir_instr
*off_instr
= instr
->src
[0].ssa
->parent_instr
;
4523 if (off_instr
->type
!= nir_instr_type_load_const
) {
4524 isel_err(off_instr
, "Unimplemented nir_intrinsic_load_input offset");
4526 uint32_t offset
= nir_instr_as_load_const(off_instr
)->value
[0].u32
;
4528 Temp vertex_buffers
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->vertex_buffers
));
4530 unsigned location
= nir_intrinsic_base(instr
) / 4 - VERT_ATTRIB_GENERIC0
+ offset
;
4531 unsigned component
= nir_intrinsic_component(instr
);
4532 unsigned bitsize
= instr
->dest
.ssa
.bit_size
;
4533 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[location
];
4534 uint32_t attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[location
];
4535 uint32_t attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[location
];
4536 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[location
];
4538 unsigned dfmt
= attrib_format
& 0xf;
4539 unsigned nfmt
= (attrib_format
>> 4) & 0x7;
4540 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(dfmt
);
4542 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
) << component
;
4543 unsigned num_channels
= MIN2(util_last_bit(mask
), vtx_info
->num_channels
);
4544 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (location
* 2)) & 3;
4545 bool post_shuffle
= ctx
->options
->key
.vs
.post_shuffle
& (1 << location
);
4547 num_channels
= MAX2(num_channels
, 3);
4549 Operand off
= bld
.copy(bld
.def(s1
), Operand(attrib_binding
* 16u));
4550 Temp list
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), vertex_buffers
, off
);
4553 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << location
)) {
4554 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[location
];
4555 Temp start_instance
= get_arg(ctx
, ctx
->args
->ac
.start_instance
);
4557 Temp instance_id
= get_arg(ctx
, ctx
->args
->ac
.instance_id
);
4559 Temp divided
= bld
.tmp(v1
);
4560 emit_v_div_u32(ctx
, divided
, as_vgpr(ctx
, instance_id
), divisor
);
4561 index
= bld
.vadd32(bld
.def(v1
), start_instance
, divided
);
4563 index
= bld
.vadd32(bld
.def(v1
), start_instance
, instance_id
);
4566 index
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), start_instance
);
4569 index
= bld
.vadd32(bld
.def(v1
),
4570 get_arg(ctx
, ctx
->args
->ac
.base_vertex
),
4571 get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
4574 Temp channels
[num_channels
];
4575 unsigned channel_start
= 0;
4576 bool direct_fetch
= false;
4578 /* skip unused channels at the start */
4579 if (vtx_info
->chan_byte_size
&& !post_shuffle
) {
4580 channel_start
= ffs(mask
) - 1;
4581 for (unsigned i
= 0; i
< channel_start
; i
++)
4582 channels
[i
] = Temp(0, s1
);
4583 } else if (vtx_info
->chan_byte_size
&& post_shuffle
&& !(mask
& 0x8)) {
4584 num_channels
= 3 - (ffs(mask
) - 1);
4588 while (channel_start
< num_channels
) {
4589 unsigned fetch_component
= num_channels
- channel_start
;
4590 unsigned fetch_offset
= attrib_offset
+ channel_start
* vtx_info
->chan_byte_size
;
4591 bool expanded
= false;
4593 /* use MUBUF when possible to avoid possible alignment issues */
4594 /* TODO: we could use SDWA to unpack 8/16-bit attributes without extra instructions */
4595 bool use_mubuf
= (nfmt
== V_008F0C_BUF_NUM_FORMAT_FLOAT
||
4596 nfmt
== V_008F0C_BUF_NUM_FORMAT_UINT
||
4597 nfmt
== V_008F0C_BUF_NUM_FORMAT_SINT
) &&
4598 vtx_info
->chan_byte_size
== 4;
4599 unsigned fetch_dfmt
= V_008F0C_BUF_DATA_FORMAT_INVALID
;
4601 fetch_dfmt
= get_fetch_data_format(ctx
, vtx_info
, fetch_offset
, attrib_stride
, &fetch_component
);
4603 if (fetch_component
== 3 && ctx
->options
->chip_class
== GFX6
) {
4604 /* GFX6 only supports loading vec3 with MTBUF, expand to vec4. */
4605 fetch_component
= 4;
4610 unsigned fetch_bytes
= fetch_component
* bitsize
/ 8;
4612 Temp fetch_index
= index
;
4613 if (attrib_stride
!= 0 && fetch_offset
> attrib_stride
) {
4614 fetch_index
= bld
.vadd32(bld
.def(v1
), Operand(fetch_offset
/ attrib_stride
), fetch_index
);
4615 fetch_offset
= fetch_offset
% attrib_stride
;
4618 Operand
soffset(0u);
4619 if (fetch_offset
>= 4096) {
4620 soffset
= bld
.copy(bld
.def(s1
), Operand(fetch_offset
/ 4096 * 4096));
4621 fetch_offset
%= 4096;
4625 switch (fetch_bytes
) {
4627 assert(!use_mubuf
&& bitsize
== 16);
4628 opcode
= aco_opcode::tbuffer_load_format_d16_x
;
4631 if (bitsize
== 16) {
4633 opcode
= aco_opcode::tbuffer_load_format_d16_xy
;
4635 opcode
= use_mubuf
? aco_opcode::buffer_load_dword
: aco_opcode::tbuffer_load_format_x
;
4639 assert(!use_mubuf
&& bitsize
== 16);
4640 opcode
= aco_opcode::tbuffer_load_format_d16_xyz
;
4643 if (bitsize
== 16) {
4645 opcode
= aco_opcode::tbuffer_load_format_d16_xyzw
;
4647 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx2
: aco_opcode::tbuffer_load_format_xy
;
4651 assert(ctx
->options
->chip_class
>= GFX7
||
4652 (!use_mubuf
&& ctx
->options
->chip_class
== GFX6
));
4653 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx3
: aco_opcode::tbuffer_load_format_xyz
;
4656 opcode
= use_mubuf
? aco_opcode::buffer_load_dwordx4
: aco_opcode::tbuffer_load_format_xyzw
;
4659 unreachable("Unimplemented load_input vector size");
4663 if (channel_start
== 0 && fetch_bytes
== dst
.bytes() && !post_shuffle
&&
4664 !expanded
&& (alpha_adjust
== RADV_ALPHA_ADJUST_NONE
||
4665 num_channels
<= 3)) {
4666 direct_fetch
= true;
4669 fetch_dst
= bld
.tmp(RegClass::get(RegType::vgpr
, fetch_bytes
));
4674 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4675 fetch_offset
, false, false, true).instr
;
4678 Definition(fetch_dst
), list
, fetch_index
, soffset
,
4679 fetch_dfmt
, nfmt
, fetch_offset
, false, true).instr
;
4682 emit_split_vector(ctx
, fetch_dst
, fetch_dst
.size());
4684 if (fetch_component
== 1) {
4685 channels
[channel_start
] = fetch_dst
;
4687 for (unsigned i
= 0; i
< MIN2(fetch_component
, num_channels
- channel_start
); i
++)
4688 channels
[channel_start
+ i
] = emit_extract_vector(ctx
, fetch_dst
, i
,
4689 bitsize
== 16 ? v2b
: v1
);
4692 channel_start
+= fetch_component
;
4695 if (!direct_fetch
) {
4696 bool is_float
= nfmt
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
4697 nfmt
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
4699 static const unsigned swizzle_normal
[4] = {0, 1, 2, 3};
4700 static const unsigned swizzle_post_shuffle
[4] = {2, 1, 0, 3};
4701 const unsigned *swizzle
= post_shuffle
? swizzle_post_shuffle
: swizzle_normal
;
4703 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4704 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
4705 unsigned num_temp
= 0;
4706 for (unsigned i
= 0; i
< dst
.size(); i
++) {
4707 unsigned idx
= i
+ component
;
4708 if (swizzle
[idx
] < num_channels
&& channels
[swizzle
[idx
]].id()) {
4709 Temp channel
= channels
[swizzle
[idx
]];
4710 if (idx
== 3 && alpha_adjust
!= RADV_ALPHA_ADJUST_NONE
)
4711 channel
= adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, channel
);
4712 vec
->operands
[i
] = Operand(channel
);
4716 } else if (is_float
&& idx
== 3) {
4717 vec
->operands
[i
] = Operand(0x3f800000u
);
4718 } else if (!is_float
&& idx
== 3) {
4719 vec
->operands
[i
] = Operand(1u);
4721 vec
->operands
[i
] = Operand(0u);
4724 vec
->definitions
[0] = Definition(dst
);
4725 ctx
->block
->instructions
.emplace_back(std::move(vec
));
4726 emit_split_vector(ctx
, dst
, dst
.size());
4728 if (num_temp
== dst
.size())
4729 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
4731 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_FRAGMENT
) {
4732 unsigned offset_idx
= instr
->intrinsic
== nir_intrinsic_load_input
? 0 : 1;
4733 nir_instr
*off_instr
= instr
->src
[offset_idx
].ssa
->parent_instr
;
4734 if (off_instr
->type
!= nir_instr_type_load_const
||
4735 nir_instr_as_load_const(off_instr
)->value
[0].u32
!= 0) {
4736 isel_err(off_instr
, "Unimplemented nir_intrinsic_load_input offset");
4739 Temp prim_mask
= get_arg(ctx
, ctx
->args
->ac
.prim_mask
);
4740 nir_const_value
* offset
= nir_src_as_const_value(instr
->src
[offset_idx
]);
4742 assert(offset
->u32
== 0);
4744 /* the lower 15bit of the prim_mask contain the offset into LDS
4745 * while the upper bits contain the number of prims */
4746 Temp offset_src
= get_ssa_temp(ctx
, instr
->src
[offset_idx
].ssa
);
4747 assert(offset_src
.regClass() == s1
&& "TODO: divergent offsets...");
4748 Builder
bld(ctx
->program
, ctx
->block
);
4749 Temp stride
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prim_mask
, Operand(16u));
4750 stride
= bld
.sop1(aco_opcode::s_bcnt1_i32_b32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
);
4751 stride
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, Operand(48u));
4752 offset_src
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), stride
, offset_src
);
4753 prim_mask
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), offset_src
, prim_mask
);
4756 unsigned idx
= nir_intrinsic_base(instr
);
4757 unsigned component
= nir_intrinsic_component(instr
);
4758 unsigned vertex_id
= 2; /* P0 */
4760 if (instr
->intrinsic
== nir_intrinsic_load_input_vertex
) {
4761 nir_const_value
* src0
= nir_src_as_const_value(instr
->src
[0]);
4762 switch (src0
->u32
) {
4764 vertex_id
= 2; /* P0 */
4767 vertex_id
= 0; /* P10 */
4770 vertex_id
= 1; /* P20 */
4773 unreachable("invalid vertex index");
4777 if (dst
.size() == 1) {
4778 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(dst
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
);
4780 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
4781 for (unsigned i
= 0; i
< dst
.size(); i
++)
4782 vec
->operands
[i
] = bld
.vintrp(aco_opcode::v_interp_mov_f32
, bld
.def(v1
), Operand(vertex_id
), bld
.m0(prim_mask
), idx
, component
+ i
);
4783 vec
->definitions
[0] = Definition(dst
);
4784 bld
.insert(std::move(vec
));
4787 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4788 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4789 Temp soffset
= get_arg(ctx
, ctx
->args
->oc_lds
);
4790 std::pair
<Temp
, unsigned> offs
= get_tcs_per_patch_output_vmem_offset(ctx
, instr
);
4791 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8u;
4793 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, soffset
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
);
4795 unreachable("Shader stage not implemented");
4799 std::pair
<Temp
, unsigned> get_gs_per_vertex_input_offset(isel_context
*ctx
, nir_intrinsic_instr
*instr
, unsigned base_stride
= 1u)
4801 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4803 Builder
bld(ctx
->program
, ctx
->block
);
4804 nir_src
*vertex_src
= nir_get_io_vertex_index_src(instr
);
4807 if (!nir_src_is_const(*vertex_src
)) {
4808 /* better code could be created, but this case probably doesn't happen
4809 * much in practice */
4810 Temp indirect_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, vertex_src
->ssa
));
4811 for (unsigned i
= 0; i
< ctx
->shader
->info
.gs
.vertices_in
; i
++) {
4814 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4815 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
/ 2u * 2u]);
4817 elem
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(16u), elem
);
4819 elem
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[i
]);
4822 if (vertex_offset
.id()) {
4823 Temp cond
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
4824 Operand(i
), indirect_vertex
);
4825 vertex_offset
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), vertex_offset
, elem
, cond
);
4827 vertex_offset
= elem
;
4831 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4832 vertex_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
), vertex_offset
);
4834 unsigned vertex
= nir_src_as_uint(*vertex_src
);
4835 if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
)
4836 vertex_offset
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
4837 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
/ 2u * 2u]),
4838 Operand((vertex
% 2u) * 16u), Operand(16u));
4840 vertex_offset
= get_arg(ctx
, ctx
->args
->gs_vtx_offset
[vertex
]);
4843 std::pair
<Temp
, unsigned> offs
= get_intrinsic_io_basic_offset(ctx
, instr
, base_stride
);
4844 offs
= offset_add(ctx
, offs
, std::make_pair(vertex_offset
, 0u));
4845 return offset_mul(ctx
, offs
, 4u);
4848 void visit_load_gs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4850 assert(ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
);
4852 Builder
bld(ctx
->program
, ctx
->block
);
4853 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4854 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4856 if (ctx
->stage
== geometry_gs
) {
4857 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
, ctx
->program
->wave_size
);
4858 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_ESGS_GS
* 16u));
4859 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, Temp(), offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 4u * ctx
->program
->wave_size
, false, true);
4860 } else if (ctx
->stage
== vertex_geometry_gs
|| ctx
->stage
== tess_eval_geometry_gs
) {
4861 std::pair
<Temp
, unsigned> offs
= get_gs_per_vertex_input_offset(ctx
, instr
);
4862 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4863 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4865 unreachable("Unsupported GS stage.");
4869 void visit_load_tcs_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4871 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4873 Builder
bld(ctx
->program
, ctx
->block
);
4874 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4876 if (load_input_from_temps(ctx
, instr
, dst
))
4879 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_input_lds_offset(ctx
, instr
);
4880 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4881 unsigned lds_align
= calculate_lds_alignment(ctx
, offs
.second
);
4883 load_lds(ctx
, elem_size_bytes
, dst
, offs
.first
, offs
.second
, lds_align
);
4886 void visit_load_tes_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4888 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4890 Builder
bld(ctx
->program
, ctx
->block
);
4892 Temp ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
4893 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
4894 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4896 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
4897 std::pair
<Temp
, unsigned> offs
= get_tcs_per_vertex_output_vmem_offset(ctx
, instr
);
4899 load_vmem_mubuf(ctx
, dst
, ring
, offs
.first
, oc_lds
, offs
.second
, elem_size_bytes
, instr
->dest
.ssa
.num_components
, 0u, true, true);
4902 void visit_load_per_vertex_input(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4904 switch (ctx
->shader
->info
.stage
) {
4905 case MESA_SHADER_GEOMETRY
:
4906 visit_load_gs_per_vertex_input(ctx
, instr
);
4908 case MESA_SHADER_TESS_CTRL
:
4909 visit_load_tcs_per_vertex_input(ctx
, instr
);
4911 case MESA_SHADER_TESS_EVAL
:
4912 visit_load_tes_per_vertex_input(ctx
, instr
);
4915 unreachable("Unimplemented shader stage");
4919 void visit_load_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4921 visit_load_tcs_output(ctx
, instr
, true);
4924 void visit_store_per_vertex_output(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4926 assert(ctx
->stage
== tess_control_hs
|| ctx
->stage
== vertex_tess_control_hs
);
4927 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
);
4929 visit_store_tcs_output(ctx
, instr
, true);
4932 void visit_load_tess_coord(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4934 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
4936 Builder
bld(ctx
->program
, ctx
->block
);
4937 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
4939 Operand
tes_u(get_arg(ctx
, ctx
->args
->tes_u
));
4940 Operand
tes_v(get_arg(ctx
, ctx
->args
->tes_v
));
4943 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
) {
4944 Temp tmp
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), tes_u
, tes_v
);
4945 tmp
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0x3f800000u
/* 1.0f */), tmp
);
4946 tes_w
= Operand(tmp
);
4949 Temp tess_coord
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), tes_u
, tes_v
, tes_w
);
4950 emit_split_vector(ctx
, tess_coord
, 3);
4953 Temp
load_desc_ptr(isel_context
*ctx
, unsigned desc_set
)
4955 if (ctx
->program
->info
->need_indirect_descriptor_sets
) {
4956 Builder
bld(ctx
->program
, ctx
->block
);
4957 Temp ptr64
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->descriptor_sets
[0]));
4958 Operand off
= bld
.copy(bld
.def(s1
), Operand(desc_set
<< 2));
4959 return bld
.smem(aco_opcode::s_load_dword
, bld
.def(s1
), ptr64
, off
);//, false, false, false);
4962 return get_arg(ctx
, ctx
->args
->descriptor_sets
[desc_set
]);
4966 void visit_load_resource(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
4968 Builder
bld(ctx
->program
, ctx
->block
);
4969 Temp index
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
4970 if (!nir_dest_is_divergent(instr
->dest
))
4971 index
= bld
.as_uniform(index
);
4972 unsigned desc_set
= nir_intrinsic_desc_set(instr
);
4973 unsigned binding
= nir_intrinsic_binding(instr
);
4976 radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
4977 radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
4978 unsigned offset
= layout
->binding
[binding
].offset
;
4980 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
4981 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
4982 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+ layout
->binding
[binding
].dynamic_offset_offset
;
4983 desc_ptr
= get_arg(ctx
, ctx
->args
->ac
.push_constants
);
4984 offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
4987 desc_ptr
= load_desc_ptr(ctx
, desc_set
);
4988 stride
= layout
->binding
[binding
].size
;
4991 nir_const_value
* nir_const_index
= nir_src_as_const_value(instr
->src
[0]);
4992 unsigned const_index
= nir_const_index
? nir_const_index
->u32
: 0;
4994 if (nir_const_index
) {
4995 const_index
= const_index
* stride
;
4996 } else if (index
.type() == RegType::vgpr
) {
4997 bool index24bit
= layout
->binding
[binding
].array_size
<= 0x1000000;
4998 index
= bld
.v_mul_imm(bld
.def(v1
), index
, stride
, index24bit
);
5000 index
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), Operand(index
));
5004 if (nir_const_index
) {
5005 const_index
= const_index
+ offset
;
5006 } else if (index
.type() == RegType::vgpr
) {
5007 index
= bld
.vadd32(bld
.def(v1
), Operand(offset
), index
);
5009 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), Operand(index
));
5013 if (nir_const_index
&& const_index
== 0) {
5015 } else if (index
.type() == RegType::vgpr
) {
5016 index
= bld
.vadd32(bld
.def(v1
),
5017 nir_const_index
? Operand(const_index
) : Operand(index
),
5020 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
5021 nir_const_index
? Operand(const_index
) : Operand(index
),
5025 bld
.copy(Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), index
);
5028 void load_buffer(isel_context
*ctx
, unsigned num_components
, unsigned component_size
,
5029 Temp dst
, Temp rsrc
, Temp offset
, unsigned align_mul
, unsigned align_offset
,
5030 bool glc
=false, bool allow_smem
=true, memory_sync_info sync
=memory_sync_info())
5032 Builder
bld(ctx
->program
, ctx
->block
);
5034 bool use_smem
= dst
.type() != RegType::vgpr
&& (!glc
|| ctx
->options
->chip_class
>= GFX8
) && allow_smem
;
5036 offset
= bld
.as_uniform(offset
);
5038 LoadEmitInfo info
= {Operand(offset
), dst
, num_components
, component_size
, rsrc
};
5041 info
.align_mul
= align_mul
;
5042 info
.align_offset
= align_offset
;
5044 emit_smem_load(ctx
, bld
, &info
);
5046 emit_mubuf_load(ctx
, bld
, &info
);
5049 void visit_load_ubo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5051 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5052 Temp rsrc
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5054 Builder
bld(ctx
->program
, ctx
->block
);
5056 nir_intrinsic_instr
* idx_instr
= nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
5057 unsigned desc_set
= nir_intrinsic_desc_set(idx_instr
);
5058 unsigned binding
= nir_intrinsic_binding(idx_instr
);
5059 radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[desc_set
].layout
;
5061 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
5062 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5063 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5064 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5065 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5066 if (ctx
->options
->chip_class
>= GFX10
) {
5067 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5068 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5069 S_008F0C_RESOURCE_LEVEL(1);
5071 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5072 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5074 Temp upper_dwords
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s3
),
5075 Operand(S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
)),
5076 Operand(0xFFFFFFFFu
),
5077 Operand(desc_type
));
5078 rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5079 rsrc
, upper_dwords
);
5081 rsrc
= convert_pointer_to_64_bit(ctx
, rsrc
);
5082 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
5084 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5085 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
5086 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
));
5089 void visit_load_push_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5091 Builder
bld(ctx
->program
, ctx
->block
);
5092 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5093 unsigned offset
= nir_intrinsic_base(instr
);
5094 unsigned count
= instr
->dest
.ssa
.num_components
;
5095 nir_const_value
*index_cv
= nir_src_as_const_value(instr
->src
[0]);
5097 if (index_cv
&& instr
->dest
.ssa
.bit_size
== 32) {
5098 unsigned start
= (offset
+ index_cv
->u32
) / 4u;
5099 start
-= ctx
->args
->ac
.base_inline_push_consts
;
5100 if (start
+ count
<= ctx
->args
->ac
.num_inline_push_consts
) {
5101 std::array
<Temp
,NIR_MAX_VEC_COMPONENTS
> elems
;
5102 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
5103 for (unsigned i
= 0; i
< count
; ++i
) {
5104 elems
[i
] = get_arg(ctx
, ctx
->args
->ac
.inline_push_consts
[start
+ i
]);
5105 vec
->operands
[i
] = Operand
{elems
[i
]};
5107 vec
->definitions
[0] = Definition(dst
);
5108 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5109 ctx
->allocated_vec
.emplace(dst
.id(), elems
);
5114 Temp index
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[0].ssa
));
5115 if (offset
!= 0) // TODO check if index != 0 as well
5116 index
= bld
.nuw().sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
), index
);
5117 Temp ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->ac
.push_constants
));
5120 bool aligned
= true;
5122 if (instr
->dest
.ssa
.bit_size
== 8) {
5123 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5124 bool fits_in_dword
= count
== 1 || (index_cv
&& ((offset
+ index_cv
->u32
) % 4 + count
) <= 4);
5126 vec
= fits_in_dword
? bld
.tmp(s1
) : bld
.tmp(s2
);
5127 } else if (instr
->dest
.ssa
.bit_size
== 16) {
5128 aligned
= index_cv
&& (offset
+ index_cv
->u32
) % 4 == 0;
5130 vec
= count
== 4 ? bld
.tmp(s4
) : count
> 1 ? bld
.tmp(s2
) : bld
.tmp(s1
);
5135 switch (vec
.size()) {
5137 op
= aco_opcode::s_load_dword
;
5140 op
= aco_opcode::s_load_dwordx2
;
5146 op
= aco_opcode::s_load_dwordx4
;
5152 op
= aco_opcode::s_load_dwordx8
;
5155 unreachable("unimplemented or forbidden load_push_constant.");
5158 static_cast<SMEM_instruction
*>(bld
.smem(op
, Definition(vec
), ptr
, index
).instr
)->prevent_overflow
= true;
5161 Operand byte_offset
= index_cv
? Operand((offset
+ index_cv
->u32
) % 4) : Operand(index
);
5162 byte_align_scalar(ctx
, vec
, byte_offset
, dst
);
5167 emit_split_vector(ctx
, vec
, 4);
5168 RegClass rc
= dst
.size() == 3 ? s1
: s2
;
5169 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
5170 emit_extract_vector(ctx
, vec
, 0, rc
),
5171 emit_extract_vector(ctx
, vec
, 1, rc
),
5172 emit_extract_vector(ctx
, vec
, 2, rc
));
5175 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
5178 void visit_load_constant(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5180 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5182 Builder
bld(ctx
->program
, ctx
->block
);
5184 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
5185 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
5186 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
5187 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
5188 if (ctx
->options
->chip_class
>= GFX10
) {
5189 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
5190 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
5191 S_008F0C_RESOURCE_LEVEL(1);
5193 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
5194 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
5197 unsigned base
= nir_intrinsic_base(instr
);
5198 unsigned range
= nir_intrinsic_range(instr
);
5200 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5201 if (base
&& offset
.type() == RegType::sgpr
)
5202 offset
= bld
.nuw().sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), offset
, Operand(base
));
5203 else if (base
&& offset
.type() == RegType::vgpr
)
5204 offset
= bld
.vadd32(bld
.def(v1
), Operand(base
), offset
);
5206 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5207 bld
.sop1(aco_opcode::p_constaddr
, bld
.def(s2
), bld
.def(s1
, scc
), Operand(ctx
->constant_data_offset
)),
5208 Operand(MIN2(base
+ range
, ctx
->shader
->constant_data_size
)),
5209 Operand(desc_type
));
5210 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
5211 // TODO: get alignment information for subdword constants
5212 load_buffer(ctx
, instr
->num_components
, size
, dst
, rsrc
, offset
, size
, 0);
5215 void visit_discard_if(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5217 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5218 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5220 ctx
->program
->needs_exact
= true;
5222 // TODO: optimize uniform conditions
5223 Builder
bld(ctx
->program
, ctx
->block
);
5224 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
5225 assert(src
.regClass() == bld
.lm
);
5226 src
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
5227 bld
.pseudo(aco_opcode::p_discard_if
, src
);
5228 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5232 void visit_discard(isel_context
* ctx
, nir_intrinsic_instr
*instr
)
5234 Builder
bld(ctx
->program
, ctx
->block
);
5236 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
5237 ctx
->cf_info
.exec_potentially_empty_discard
= true;
5239 bool divergent
= ctx
->cf_info
.parent_if
.is_divergent
||
5240 ctx
->cf_info
.parent_loop
.has_divergent_continue
;
5242 if (ctx
->block
->loop_nest_depth
&&
5243 ((nir_instr_is_last(&instr
->instr
) && !divergent
) || divergent
)) {
5244 /* we handle discards the same way as jump instructions */
5245 append_logical_end(ctx
->block
);
5247 /* in loops, discard behaves like break */
5248 Block
*linear_target
= ctx
->cf_info
.parent_loop
.exit
;
5249 ctx
->block
->kind
|= block_kind_discard
;
5252 /* uniform discard - loop ends here */
5253 assert(nir_instr_is_last(&instr
->instr
));
5254 ctx
->block
->kind
|= block_kind_uniform
;
5255 ctx
->cf_info
.has_branch
= true;
5256 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
5257 add_linear_edge(ctx
->block
->index
, linear_target
);
5261 /* we add a break right behind the discard() instructions */
5262 ctx
->block
->kind
|= block_kind_break
;
5263 unsigned idx
= ctx
->block
->index
;
5265 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
5266 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = idx
;
5268 /* remove critical edges from linear CFG */
5269 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
5270 Block
* break_block
= ctx
->program
->create_and_insert_block();
5271 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5272 break_block
->kind
|= block_kind_uniform
;
5273 add_linear_edge(idx
, break_block
);
5274 add_linear_edge(break_block
->index
, linear_target
);
5275 bld
.reset(break_block
);
5276 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
5278 Block
* continue_block
= ctx
->program
->create_and_insert_block();
5279 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
5280 add_linear_edge(idx
, continue_block
);
5281 append_logical_start(continue_block
);
5282 ctx
->block
= continue_block
;
5287 /* it can currently happen that NIR doesn't remove the unreachable code */
5288 if (!nir_instr_is_last(&instr
->instr
)) {
5289 ctx
->program
->needs_exact
= true;
5290 /* save exec somewhere temporarily so that it doesn't get
5291 * overwritten before the discard from outer exec masks */
5292 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(0xFFFFFFFF), Operand(exec
, bld
.lm
));
5293 bld
.pseudo(aco_opcode::p_discard_if
, cond
);
5294 ctx
->block
->kind
|= block_kind_uses_discard_if
;
5298 /* This condition is incorrect for uniformly branched discards in a loop
5299 * predicated by a divergent condition, but the above code catches that case
5300 * and the discard would end up turning into a discard_if.
5310 if (!ctx
->cf_info
.parent_if
.is_divergent
) {
5311 /* program just ends here */
5312 ctx
->block
->kind
|= block_kind_uniform
;
5313 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
5314 0 /* enabled mask */, 9 /* dest */,
5315 false /* compressed */, true/* done */, true /* valid mask */);
5316 bld
.sopp(aco_opcode::s_endpgm
);
5317 // TODO: it will potentially be followed by a branch which is dead code to sanitize NIR phis
5319 ctx
->block
->kind
|= block_kind_discard
;
5320 /* branch and linear edge is added by visit_if() */
5324 enum aco_descriptor_type
{
5335 should_declare_array(isel_context
*ctx
, enum glsl_sampler_dim sampler_dim
, bool is_array
) {
5336 if (sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
5338 ac_image_dim dim
= ac_get_sampler_dim(ctx
->options
->chip_class
, sampler_dim
, is_array
);
5339 return dim
== ac_image_cube
||
5340 dim
== ac_image_1darray
||
5341 dim
== ac_image_2darray
||
5342 dim
== ac_image_2darraymsaa
;
5345 Temp
get_sampler_desc(isel_context
*ctx
, nir_deref_instr
*deref_instr
,
5346 enum aco_descriptor_type desc_type
,
5347 const nir_tex_instr
*tex_instr
, bool image
, bool write
)
5349 /* FIXME: we should lower the deref with some new nir_intrinsic_load_desc
5350 std::unordered_map<uint64_t, Temp>::iterator it = ctx->tex_desc.find((uint64_t) desc_type << 32 | deref_instr->dest.ssa.index);
5351 if (it != ctx->tex_desc.end())
5354 Temp index
= Temp();
5355 bool index_set
= false;
5356 unsigned constant_index
= 0;
5357 unsigned descriptor_set
;
5358 unsigned base_index
;
5359 Builder
bld(ctx
->program
, ctx
->block
);
5362 assert(tex_instr
&& !image
);
5364 base_index
= tex_instr
->sampler_index
;
5366 while(deref_instr
->deref_type
!= nir_deref_type_var
) {
5367 unsigned array_size
= glsl_get_aoa_size(deref_instr
->type
);
5371 assert(deref_instr
->deref_type
== nir_deref_type_array
);
5372 nir_const_value
*const_value
= nir_src_as_const_value(deref_instr
->arr
.index
);
5374 constant_index
+= array_size
* const_value
->u32
;
5376 Temp indirect
= get_ssa_temp(ctx
, deref_instr
->arr
.index
.ssa
);
5377 if (indirect
.type() == RegType::vgpr
)
5378 indirect
= bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), indirect
);
5380 if (array_size
!= 1)
5381 indirect
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(array_size
), indirect
);
5387 index
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), index
, indirect
);
5391 deref_instr
= nir_src_as_deref(deref_instr
->parent
);
5393 descriptor_set
= deref_instr
->var
->data
.descriptor_set
;
5394 base_index
= deref_instr
->var
->data
.binding
;
5397 Temp list
= load_desc_ptr(ctx
, descriptor_set
);
5398 list
= convert_pointer_to_64_bit(ctx
, list
);
5400 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
5401 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
5402 unsigned offset
= binding
->offset
;
5403 unsigned stride
= binding
->size
;
5407 assert(base_index
< layout
->binding_count
);
5409 switch (desc_type
) {
5410 case ACO_DESC_IMAGE
:
5412 opcode
= aco_opcode::s_load_dwordx8
;
5414 case ACO_DESC_FMASK
:
5416 opcode
= aco_opcode::s_load_dwordx8
;
5419 case ACO_DESC_SAMPLER
:
5421 opcode
= aco_opcode::s_load_dwordx4
;
5422 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
5423 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
5425 case ACO_DESC_BUFFER
:
5427 opcode
= aco_opcode::s_load_dwordx4
;
5429 case ACO_DESC_PLANE_0
:
5430 case ACO_DESC_PLANE_1
:
5432 opcode
= aco_opcode::s_load_dwordx8
;
5433 offset
+= 32 * (desc_type
- ACO_DESC_PLANE_0
);
5435 case ACO_DESC_PLANE_2
:
5437 opcode
= aco_opcode::s_load_dwordx4
;
5441 unreachable("invalid desc_type\n");
5444 offset
+= constant_index
* stride
;
5446 if (desc_type
== ACO_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
5447 (!index_set
|| binding
->immutable_samplers_equal
)) {
5448 if (binding
->immutable_samplers_equal
)
5451 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
5452 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
5453 Operand(samplers
[constant_index
* 4 + 0]),
5454 Operand(samplers
[constant_index
* 4 + 1]),
5455 Operand(samplers
[constant_index
* 4 + 2]),
5456 Operand(samplers
[constant_index
* 4 + 3]));
5461 off
= bld
.copy(bld
.def(s1
), Operand(offset
));
5463 off
= Operand((Temp
)bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(offset
),
5464 bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(stride
), index
)));
5467 Temp res
= bld
.smem(opcode
, bld
.def(type
), list
, off
);
5469 if (desc_type
== ACO_DESC_PLANE_2
) {
5471 for (unsigned i
= 0; i
< 8; i
++)
5472 components
[i
] = bld
.tmp(s1
);
5473 bld
.pseudo(aco_opcode::p_split_vector
,
5474 Definition(components
[0]),
5475 Definition(components
[1]),
5476 Definition(components
[2]),
5477 Definition(components
[3]),
5480 Temp desc2
= get_sampler_desc(ctx
, deref_instr
, ACO_DESC_PLANE_1
, tex_instr
, image
, write
);
5481 bld
.pseudo(aco_opcode::p_split_vector
,
5482 bld
.def(s1
), bld
.def(s1
), bld
.def(s1
), bld
.def(s1
),
5483 Definition(components
[4]),
5484 Definition(components
[5]),
5485 Definition(components
[6]),
5486 Definition(components
[7]),
5489 res
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
5490 components
[0], components
[1], components
[2], components
[3],
5491 components
[4], components
[5], components
[6], components
[7]);
5497 static int image_type_to_components_count(enum glsl_sampler_dim dim
, bool array
)
5500 case GLSL_SAMPLER_DIM_BUF
:
5502 case GLSL_SAMPLER_DIM_1D
:
5503 return array
? 2 : 1;
5504 case GLSL_SAMPLER_DIM_2D
:
5505 return array
? 3 : 2;
5506 case GLSL_SAMPLER_DIM_MS
:
5507 return array
? 4 : 3;
5508 case GLSL_SAMPLER_DIM_3D
:
5509 case GLSL_SAMPLER_DIM_CUBE
:
5511 case GLSL_SAMPLER_DIM_RECT
:
5512 case GLSL_SAMPLER_DIM_SUBPASS
:
5514 case GLSL_SAMPLER_DIM_SUBPASS_MS
:
5523 /* Adjust the sample index according to FMASK.
5525 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
5526 * which is the identity mapping. Each nibble says which physical sample
5527 * should be fetched to get that sample.
5529 * For example, 0x11111100 means there are only 2 samples stored and
5530 * the second sample covers 3/4 of the pixel. When reading samples 0
5531 * and 1, return physical sample 0 (determined by the first two 0s
5532 * in FMASK), otherwise return physical sample 1.
5534 * The sample index should be adjusted as follows:
5535 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
5537 static Temp
adjust_sample_index_using_fmask(isel_context
*ctx
, bool da
, std::vector
<Temp
>& coords
, Operand sample_index
, Temp fmask_desc_ptr
)
5539 Builder
bld(ctx
->program
, ctx
->block
);
5540 Temp fmask
= bld
.tmp(v1
);
5541 unsigned dim
= ctx
->options
->chip_class
>= GFX10
5542 ? ac_get_sampler_dim(ctx
->options
->chip_class
, GLSL_SAMPLER_DIM_2D
, da
)
5545 Temp coord
= da
? bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v3
), coords
[0], coords
[1], coords
[2]) :
5546 bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), coords
[0], coords
[1]);
5547 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(aco_opcode::image_load
, Format::MIMG
, 3, 1)};
5548 load
->operands
[0] = Operand(fmask_desc_ptr
);
5549 load
->operands
[1] = Operand(s4
); /* no sampler */
5550 load
->operands
[2] = Operand(coord
);
5551 load
->definitions
[0] = Definition(fmask
);
5558 ctx
->block
->instructions
.emplace_back(std::move(load
));
5560 Operand sample_index4
;
5561 if (sample_index
.isConstant()) {
5562 if (sample_index
.constantValue() < 16) {
5563 sample_index4
= Operand(sample_index
.constantValue() << 2);
5565 sample_index4
= Operand(0u);
5567 } else if (sample_index
.regClass() == s1
) {
5568 sample_index4
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), sample_index
, Operand(2u));
5570 assert(sample_index
.regClass() == v1
);
5571 sample_index4
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), sample_index
);
5575 if (sample_index4
.isConstant() && sample_index4
.constantValue() == 0)
5576 final_sample
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(15u), fmask
);
5577 else if (sample_index4
.isConstant() && sample_index4
.constantValue() == 28)
5578 final_sample
= bld
.vop2(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), Operand(28u), fmask
);
5580 final_sample
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), fmask
, sample_index4
, Operand(4u));
5582 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
5583 * resource descriptor is 0 (invalid),
5585 Temp compare
= bld
.tmp(bld
.lm
);
5586 bld
.vopc_e64(aco_opcode::v_cmp_lg_u32
, Definition(compare
),
5587 Operand(0u), emit_extract_vector(ctx
, fmask_desc_ptr
, 1, s1
)).def(0).setHint(vcc
);
5589 Temp sample_index_v
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), sample_index
);
5591 /* Replace the MSAA sample index. */
5592 return bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), sample_index_v
, final_sample
, compare
);
5595 static Temp
get_image_coords(isel_context
*ctx
, const nir_intrinsic_instr
*instr
, const struct glsl_type
*type
)
5598 Temp src0
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
5599 enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5600 bool is_array
= glsl_sampler_type_is_array(type
);
5601 ASSERTED
bool add_frag_pos
= (dim
== GLSL_SAMPLER_DIM_SUBPASS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5602 assert(!add_frag_pos
&& "Input attachments should be lowered.");
5603 bool is_ms
= (dim
== GLSL_SAMPLER_DIM_MS
|| dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
);
5604 bool gfx9_1d
= ctx
->options
->chip_class
== GFX9
&& dim
== GLSL_SAMPLER_DIM_1D
;
5605 int count
= image_type_to_components_count(dim
, is_array
);
5606 std::vector
<Temp
> coords(count
);
5607 Builder
bld(ctx
->program
, ctx
->block
);
5611 Temp src2
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
5612 /* get sample index */
5613 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
) {
5614 nir_const_value
*sample_cv
= nir_src_as_const_value(instr
->src
[2]);
5615 Operand sample_index
= sample_cv
? Operand(sample_cv
->u32
) : Operand(emit_extract_vector(ctx
, src2
, 0, v1
));
5616 std::vector
<Temp
> fmask_load_address
;
5617 for (unsigned i
= 0; i
< (is_array
? 3 : 2); i
++)
5618 fmask_load_address
.emplace_back(emit_extract_vector(ctx
, src0
, i
, v1
));
5620 Temp fmask_desc_ptr
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_FMASK
, nullptr, false, false);
5621 coords
[count
] = adjust_sample_index_using_fmask(ctx
, is_array
, fmask_load_address
, sample_index
, fmask_desc_ptr
);
5623 coords
[count
] = emit_extract_vector(ctx
, src2
, 0, v1
);
5628 coords
[0] = emit_extract_vector(ctx
, src0
, 0, v1
);
5629 coords
.resize(coords
.size() + 1);
5630 coords
[1] = bld
.copy(bld
.def(v1
), Operand(0u));
5632 coords
[2] = emit_extract_vector(ctx
, src0
, 1, v1
);
5634 for (int i
= 0; i
< count
; i
++)
5635 coords
[i
] = emit_extract_vector(ctx
, src0
, i
, v1
);
5638 if (instr
->intrinsic
== nir_intrinsic_image_deref_load
||
5639 instr
->intrinsic
== nir_intrinsic_image_deref_store
) {
5640 int lod_index
= instr
->intrinsic
== nir_intrinsic_image_deref_load
? 3 : 4;
5641 bool level_zero
= nir_src_is_const(instr
->src
[lod_index
]) && nir_src_as_uint(instr
->src
[lod_index
]) == 0;
5644 coords
.emplace_back(get_ssa_temp(ctx
, instr
->src
[lod_index
].ssa
));
5647 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, coords
.size(), 1)};
5648 for (unsigned i
= 0; i
< coords
.size(); i
++)
5649 vec
->operands
[i
] = Operand(coords
[i
]);
5650 Temp res
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, coords
.size())};
5651 vec
->definitions
[0] = Definition(res
);
5652 ctx
->block
->instructions
.emplace_back(std::move(vec
));
5657 memory_sync_info
get_memory_sync_info(nir_intrinsic_instr
*instr
, storage_class storage
, unsigned semantics
)
5659 /* atomicrmw might not have NIR_INTRINSIC_ACCESS and there's nothing interesting there anyway */
5660 if (semantics
& semantic_atomicrmw
)
5661 return memory_sync_info(storage
, semantics
);
5663 unsigned access
= nir_intrinsic_access(instr
);
5665 if (access
& ACCESS_VOLATILE
)
5666 semantics
|= semantic_volatile
;
5667 if (access
& ACCESS_CAN_REORDER
)
5668 semantics
|= semantic_can_reorder
| semantic_private
;
5670 return memory_sync_info(storage
, semantics
);
5673 void visit_image_load(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5675 Builder
bld(ctx
->program
, ctx
->block
);
5676 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5677 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5678 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5679 bool is_array
= glsl_sampler_type_is_array(type
);
5680 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5682 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, 0);
5683 unsigned access
= var
->data
.access
| nir_intrinsic_access(instr
);
5685 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5686 unsigned mask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5687 unsigned num_channels
= util_last_bit(mask
);
5688 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5689 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5692 switch (num_channels
) {
5694 opcode
= aco_opcode::buffer_load_format_x
;
5697 opcode
= aco_opcode::buffer_load_format_xy
;
5700 opcode
= aco_opcode::buffer_load_format_xyz
;
5703 opcode
= aco_opcode::buffer_load_format_xyzw
;
5706 unreachable(">4 channel buffer image load");
5708 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 3, 1)};
5709 load
->operands
[0] = Operand(rsrc
);
5710 load
->operands
[1] = Operand(vindex
);
5711 load
->operands
[2] = Operand((uint32_t) 0);
5713 if (num_channels
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5716 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_channels
)};
5717 load
->definitions
[0] = Definition(tmp
);
5719 load
->glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
5720 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5722 ctx
->block
->instructions
.emplace_back(std::move(load
));
5724 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, (1 << num_channels
) - 1);
5728 Temp coords
= get_image_coords(ctx
, instr
, type
);
5729 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5731 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
5732 unsigned num_components
= util_bitcount(dmask
);
5734 if (num_components
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
5737 tmp
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, num_components
)};
5739 bool level_zero
= nir_src_is_const(instr
->src
[3]) && nir_src_as_uint(instr
->src
[3]) == 0;
5740 aco_opcode opcode
= level_zero
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
5742 aco_ptr
<MIMG_instruction
> load
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1)};
5743 load
->operands
[0] = Operand(resource
);
5744 load
->operands
[1] = Operand(s4
); /* no sampler */
5745 load
->operands
[2] = Operand(coords
);
5746 load
->definitions
[0] = Definition(tmp
);
5747 load
->glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
) ? 1 : 0;
5748 load
->dlc
= load
->glc
&& ctx
->options
->chip_class
>= GFX10
;
5749 load
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5750 load
->dmask
= dmask
;
5752 load
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5754 ctx
->block
->instructions
.emplace_back(std::move(load
));
5756 expand_vector(ctx
, tmp
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
5760 void visit_image_store(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5762 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5763 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5764 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5765 bool is_array
= glsl_sampler_type_is_array(type
);
5766 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5768 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, 0);
5769 unsigned access
= var
->data
.access
| nir_intrinsic_access(instr
);
5770 bool glc
= ctx
->options
->chip_class
== GFX6
|| access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
) ? 1 : 0;
5772 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5773 Temp rsrc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5774 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5776 switch (data
.size()) {
5778 opcode
= aco_opcode::buffer_store_format_x
;
5781 opcode
= aco_opcode::buffer_store_format_xy
;
5784 opcode
= aco_opcode::buffer_store_format_xyz
;
5787 opcode
= aco_opcode::buffer_store_format_xyzw
;
5790 unreachable(">4 channel buffer image store");
5792 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
5793 store
->operands
[0] = Operand(rsrc
);
5794 store
->operands
[1] = Operand(vindex
);
5795 store
->operands
[2] = Operand((uint32_t) 0);
5796 store
->operands
[3] = Operand(data
);
5797 store
->idxen
= true;
5800 store
->disable_wqm
= true;
5802 ctx
->program
->needs_exact
= true;
5803 ctx
->block
->instructions
.emplace_back(std::move(store
));
5807 assert(data
.type() == RegType::vgpr
);
5808 Temp coords
= get_image_coords(ctx
, instr
, type
);
5809 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5811 bool level_zero
= nir_src_is_const(instr
->src
[4]) && nir_src_as_uint(instr
->src
[4]) == 0;
5812 aco_opcode opcode
= level_zero
? aco_opcode::image_store
: aco_opcode::image_store_mip
;
5814 aco_ptr
<MIMG_instruction
> store
{create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 0)};
5815 store
->operands
[0] = Operand(resource
);
5816 store
->operands
[1] = Operand(data
);
5817 store
->operands
[2] = Operand(coords
);
5820 store
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5821 store
->dmask
= (1 << data
.size()) - 1;
5823 store
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5824 store
->disable_wqm
= true;
5826 ctx
->program
->needs_exact
= true;
5827 ctx
->block
->instructions
.emplace_back(std::move(store
));
5831 void visit_image_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5833 /* return the previous value if dest is ever used */
5834 bool return_previous
= false;
5835 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
5836 return_previous
= true;
5839 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
5840 return_previous
= true;
5844 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5845 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5846 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5847 bool is_array
= glsl_sampler_type_is_array(type
);
5848 Builder
bld(ctx
->program
, ctx
->block
);
5850 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[3].ssa
));
5851 assert(data
.size() == 1 && "64bit ssbo atomics not yet implemented.");
5853 if (instr
->intrinsic
== nir_intrinsic_image_deref_atomic_comp_swap
)
5854 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), get_ssa_temp(ctx
, instr
->src
[4].ssa
), data
);
5856 aco_opcode buf_op
, image_op
;
5857 switch (instr
->intrinsic
) {
5858 case nir_intrinsic_image_deref_atomic_add
:
5859 buf_op
= aco_opcode::buffer_atomic_add
;
5860 image_op
= aco_opcode::image_atomic_add
;
5862 case nir_intrinsic_image_deref_atomic_umin
:
5863 buf_op
= aco_opcode::buffer_atomic_umin
;
5864 image_op
= aco_opcode::image_atomic_umin
;
5866 case nir_intrinsic_image_deref_atomic_imin
:
5867 buf_op
= aco_opcode::buffer_atomic_smin
;
5868 image_op
= aco_opcode::image_atomic_smin
;
5870 case nir_intrinsic_image_deref_atomic_umax
:
5871 buf_op
= aco_opcode::buffer_atomic_umax
;
5872 image_op
= aco_opcode::image_atomic_umax
;
5874 case nir_intrinsic_image_deref_atomic_imax
:
5875 buf_op
= aco_opcode::buffer_atomic_smax
;
5876 image_op
= aco_opcode::image_atomic_smax
;
5878 case nir_intrinsic_image_deref_atomic_and
:
5879 buf_op
= aco_opcode::buffer_atomic_and
;
5880 image_op
= aco_opcode::image_atomic_and
;
5882 case nir_intrinsic_image_deref_atomic_or
:
5883 buf_op
= aco_opcode::buffer_atomic_or
;
5884 image_op
= aco_opcode::image_atomic_or
;
5886 case nir_intrinsic_image_deref_atomic_xor
:
5887 buf_op
= aco_opcode::buffer_atomic_xor
;
5888 image_op
= aco_opcode::image_atomic_xor
;
5890 case nir_intrinsic_image_deref_atomic_exchange
:
5891 buf_op
= aco_opcode::buffer_atomic_swap
;
5892 image_op
= aco_opcode::image_atomic_swap
;
5894 case nir_intrinsic_image_deref_atomic_comp_swap
:
5895 buf_op
= aco_opcode::buffer_atomic_cmpswap
;
5896 image_op
= aco_opcode::image_atomic_cmpswap
;
5899 unreachable("visit_image_atomic should only be called with nir_intrinsic_image_deref_atomic_* instructions.");
5902 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5903 memory_sync_info sync
= get_memory_sync_info(instr
, storage_image
, semantic_atomicrmw
);
5905 if (dim
== GLSL_SAMPLER_DIM_BUF
) {
5906 Temp vindex
= emit_extract_vector(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
), 0, v1
);
5907 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, nullptr, true, true);
5908 //assert(ctx->options->chip_class < GFX9 && "GFX9 stride size workaround not yet implemented.");
5909 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(buf_op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
5910 mubuf
->operands
[0] = Operand(resource
);
5911 mubuf
->operands
[1] = Operand(vindex
);
5912 mubuf
->operands
[2] = Operand((uint32_t)0);
5913 mubuf
->operands
[3] = Operand(data
);
5914 if (return_previous
)
5915 mubuf
->definitions
[0] = Definition(dst
);
5917 mubuf
->idxen
= true;
5918 mubuf
->glc
= return_previous
;
5919 mubuf
->dlc
= false; /* Not needed for atomics */
5920 mubuf
->disable_wqm
= true;
5922 ctx
->program
->needs_exact
= true;
5923 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
5927 Temp coords
= get_image_coords(ctx
, instr
, type
);
5928 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, nullptr, true, true);
5929 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(image_op
, Format::MIMG
, 3, return_previous
? 1 : 0)};
5930 mimg
->operands
[0] = Operand(resource
);
5931 mimg
->operands
[1] = Operand(data
);
5932 mimg
->operands
[2] = Operand(coords
);
5933 if (return_previous
)
5934 mimg
->definitions
[0] = Definition(dst
);
5935 mimg
->glc
= return_previous
;
5936 mimg
->dlc
= false; /* Not needed for atomics */
5937 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
5938 mimg
->dmask
= (1 << data
.size()) - 1;
5940 mimg
->da
= should_declare_array(ctx
, dim
, glsl_sampler_type_is_array(type
));
5941 mimg
->disable_wqm
= true;
5943 ctx
->program
->needs_exact
= true;
5944 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
5948 void get_buffer_size(isel_context
*ctx
, Temp desc
, Temp dst
, bool in_elements
)
5950 if (in_elements
&& ctx
->options
->chip_class
== GFX8
) {
5951 /* we only have to divide by 1, 2, 4, 8, 12 or 16 */
5952 Builder
bld(ctx
->program
, ctx
->block
);
5954 Temp size
= emit_extract_vector(ctx
, desc
, 2, s1
);
5956 Temp size_div3
= bld
.vop3(aco_opcode::v_mul_hi_u32
, bld
.def(v1
), bld
.copy(bld
.def(v1
), Operand(0xaaaaaaabu
)), size
);
5957 size_div3
= bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.as_uniform(size_div3
), Operand(1u));
5959 Temp stride
= emit_extract_vector(ctx
, desc
, 1, s1
);
5960 stride
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), stride
, Operand((5u << 16) | 16u));
5962 Temp is12
= bld
.sopc(aco_opcode::s_cmp_eq_i32
, bld
.def(s1
, scc
), stride
, Operand(12u));
5963 size
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
), size_div3
, size
, bld
.scc(is12
));
5965 Temp shr_dst
= dst
.type() == RegType::vgpr
? bld
.tmp(s1
) : dst
;
5966 bld
.sop2(aco_opcode::s_lshr_b32
, Definition(shr_dst
), bld
.def(s1
, scc
),
5967 size
, bld
.sop1(aco_opcode::s_ff1_i32_b32
, bld
.def(s1
), stride
));
5968 if (dst
.type() == RegType::vgpr
)
5969 bld
.copy(Definition(dst
), shr_dst
);
5971 /* TODO: we can probably calculate this faster with v_skip when stride != 12 */
5973 emit_extract_vector(ctx
, desc
, 2, dst
);
5977 void visit_image_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
5979 const nir_variable
*var
= nir_deref_instr_get_variable(nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
));
5980 const struct glsl_type
*type
= glsl_without_array(var
->type
);
5981 const enum glsl_sampler_dim dim
= glsl_get_sampler_dim(type
);
5982 bool is_array
= glsl_sampler_type_is_array(type
);
5983 Builder
bld(ctx
->program
, ctx
->block
);
5985 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_BUF
) {
5986 Temp desc
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_BUFFER
, NULL
, true, false);
5987 return get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
5991 assert(nir_src_as_uint(instr
->src
[1]) == 0);
5992 Temp lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
5995 Temp resource
= get_sampler_desc(ctx
, nir_instr_as_deref(instr
->src
[0].ssa
->parent_instr
), ACO_DESC_IMAGE
, NULL
, true, false);
5997 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
5999 aco_ptr
<MIMG_instruction
> mimg
{create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1)};
6000 mimg
->operands
[0] = Operand(resource
);
6001 mimg
->operands
[1] = Operand(s4
); /* no sampler */
6002 mimg
->operands
[2] = Operand(lod
);
6003 uint8_t& dmask
= mimg
->dmask
;
6004 mimg
->dim
= ac_get_image_dim(ctx
->options
->chip_class
, dim
, is_array
);
6005 mimg
->dmask
= (1 << instr
->dest
.ssa
.num_components
) - 1;
6006 mimg
->da
= glsl_sampler_type_is_array(type
);
6007 Definition
& def
= mimg
->definitions
[0];
6008 ctx
->block
->instructions
.emplace_back(std::move(mimg
));
6010 if (glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_CUBE
&&
6011 glsl_sampler_type_is_array(type
)) {
6013 assert(instr
->dest
.ssa
.num_components
== 3);
6014 Temp tmp
= {ctx
->program
->allocateId(), v3
};
6015 def
= Definition(tmp
);
6016 emit_split_vector(ctx
, tmp
, 3);
6018 /* divide 3rd value by 6 by multiplying with magic number */
6019 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
6020 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp
, 2, v1
), c
);
6022 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
6023 emit_extract_vector(ctx
, tmp
, 0, v1
),
6024 emit_extract_vector(ctx
, tmp
, 1, v1
),
6027 } else if (ctx
->options
->chip_class
== GFX9
&&
6028 glsl_get_sampler_dim(type
) == GLSL_SAMPLER_DIM_1D
&&
6029 glsl_sampler_type_is_array(type
)) {
6030 assert(instr
->dest
.ssa
.num_components
== 2);
6031 def
= Definition(dst
);
6034 def
= Definition(dst
);
6037 emit_split_vector(ctx
, dst
, instr
->dest
.ssa
.num_components
);
6040 void visit_load_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6042 Builder
bld(ctx
->program
, ctx
->block
);
6043 unsigned num_components
= instr
->num_components
;
6045 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6046 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6047 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6049 unsigned access
= nir_intrinsic_access(instr
);
6050 bool glc
= access
& (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6051 unsigned size
= instr
->dest
.ssa
.bit_size
/ 8;
6053 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[0].ssa
, access
);
6054 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6055 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6057 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_store
: has_vmem_store
));
6058 allow_smem
|= ((access
& ACCESS_RESTRICT
) && (access
& ACCESS_NON_WRITEABLE
)) || (access
& ACCESS_CAN_REORDER
);
6060 load_buffer(ctx
, num_components
, size
, dst
, rsrc
, get_ssa_temp(ctx
, instr
->src
[1].ssa
),
6061 nir_intrinsic_align_mul(instr
), nir_intrinsic_align_offset(instr
), glc
, allow_smem
,
6062 get_memory_sync_info(instr
, storage_buffer
, 0));
6065 void visit_store_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6067 Builder
bld(ctx
->program
, ctx
->block
);
6068 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6069 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6070 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6071 Temp offset
= get_ssa_temp(ctx
, instr
->src
[2].ssa
);
6073 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6074 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6076 memory_sync_info sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6077 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6078 uint32_t flags
= get_all_buffer_resource_flags(ctx
, instr
->src
[1].ssa
, nir_intrinsic_access(instr
));
6079 /* GLC bypasses VMEM/SMEM caches, so GLC SMEM loads/stores are coherent with GLC VMEM loads/stores
6080 * TODO: this optimization is disabled for now because we still need to ensure correct ordering
6082 bool allow_smem
= !(flags
& (0 && glc
? has_nonglc_vmem_loadstore
: has_vmem_loadstore
));
6084 bool smem
= !nir_src_is_divergent(instr
->src
[2]) &&
6085 ctx
->options
->chip_class
>= GFX8
&&
6086 ctx
->options
->chip_class
< GFX10_3
&&
6087 (elem_size_bytes
>= 4 || can_subdword_ssbo_store_use_smem(instr
)) &&
6090 offset
= bld
.as_uniform(offset
);
6091 bool smem_nonfs
= smem
&& ctx
->stage
!= fragment_fs
;
6093 unsigned write_count
= 0;
6094 Temp write_datas
[32];
6095 unsigned offsets
[32];
6096 split_buffer_store(ctx
, instr
, smem
, smem_nonfs
? RegType::sgpr
: (smem
? data
.type() : RegType::vgpr
),
6097 data
, writemask
, 16, &write_count
, write_datas
, offsets
);
6099 for (unsigned i
= 0; i
< write_count
; i
++) {
6100 aco_opcode op
= get_buffer_store_op(smem
, write_datas
[i
].bytes());
6101 if (smem
&& ctx
->stage
== fragment_fs
)
6102 op
= aco_opcode::p_fs_buffer_store_smem
;
6105 aco_ptr
<SMEM_instruction
> store
{create_instruction
<SMEM_instruction
>(op
, Format::SMEM
, 3, 0)};
6106 store
->operands
[0] = Operand(rsrc
);
6108 Temp off
= bld
.nuw().sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
6109 offset
, Operand(offsets
[i
]));
6110 store
->operands
[1] = Operand(off
);
6112 store
->operands
[1] = Operand(offset
);
6114 if (op
!= aco_opcode::p_fs_buffer_store_smem
)
6115 store
->operands
[1].setFixed(m0
);
6116 store
->operands
[2] = Operand(write_datas
[i
]);
6119 store
->disable_wqm
= true;
6121 ctx
->block
->instructions
.emplace_back(std::move(store
));
6122 ctx
->program
->wb_smem_l1_on_end
= true;
6123 if (op
== aco_opcode::p_fs_buffer_store_smem
) {
6124 ctx
->block
->kind
|= block_kind_needs_lowering
;
6125 ctx
->program
->needs_exact
= true;
6128 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6129 store
->operands
[0] = Operand(rsrc
);
6130 store
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6131 store
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6132 store
->operands
[3] = Operand(write_datas
[i
]);
6133 store
->offset
= offsets
[i
];
6134 store
->offen
= (offset
.type() == RegType::vgpr
);
6137 store
->disable_wqm
= true;
6139 ctx
->program
->needs_exact
= true;
6140 ctx
->block
->instructions
.emplace_back(std::move(store
));
6145 void visit_atomic_ssbo(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6147 /* return the previous value if dest is ever used */
6148 bool return_previous
= false;
6149 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6150 return_previous
= true;
6153 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6154 return_previous
= true;
6158 Builder
bld(ctx
->program
, ctx
->block
);
6159 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6161 if (instr
->intrinsic
== nir_intrinsic_ssbo_atomic_comp_swap
)
6162 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6163 get_ssa_temp(ctx
, instr
->src
[3].ssa
), data
);
6165 Temp offset
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6166 Temp rsrc
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6167 rsrc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), rsrc
, Operand(0u));
6169 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6171 aco_opcode op32
, op64
;
6172 switch (instr
->intrinsic
) {
6173 case nir_intrinsic_ssbo_atomic_add
:
6174 op32
= aco_opcode::buffer_atomic_add
;
6175 op64
= aco_opcode::buffer_atomic_add_x2
;
6177 case nir_intrinsic_ssbo_atomic_imin
:
6178 op32
= aco_opcode::buffer_atomic_smin
;
6179 op64
= aco_opcode::buffer_atomic_smin_x2
;
6181 case nir_intrinsic_ssbo_atomic_umin
:
6182 op32
= aco_opcode::buffer_atomic_umin
;
6183 op64
= aco_opcode::buffer_atomic_umin_x2
;
6185 case nir_intrinsic_ssbo_atomic_imax
:
6186 op32
= aco_opcode::buffer_atomic_smax
;
6187 op64
= aco_opcode::buffer_atomic_smax_x2
;
6189 case nir_intrinsic_ssbo_atomic_umax
:
6190 op32
= aco_opcode::buffer_atomic_umax
;
6191 op64
= aco_opcode::buffer_atomic_umax_x2
;
6193 case nir_intrinsic_ssbo_atomic_and
:
6194 op32
= aco_opcode::buffer_atomic_and
;
6195 op64
= aco_opcode::buffer_atomic_and_x2
;
6197 case nir_intrinsic_ssbo_atomic_or
:
6198 op32
= aco_opcode::buffer_atomic_or
;
6199 op64
= aco_opcode::buffer_atomic_or_x2
;
6201 case nir_intrinsic_ssbo_atomic_xor
:
6202 op32
= aco_opcode::buffer_atomic_xor
;
6203 op64
= aco_opcode::buffer_atomic_xor_x2
;
6205 case nir_intrinsic_ssbo_atomic_exchange
:
6206 op32
= aco_opcode::buffer_atomic_swap
;
6207 op64
= aco_opcode::buffer_atomic_swap_x2
;
6209 case nir_intrinsic_ssbo_atomic_comp_swap
:
6210 op32
= aco_opcode::buffer_atomic_cmpswap
;
6211 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6214 unreachable("visit_atomic_ssbo should only be called with nir_intrinsic_ssbo_atomic_* instructions.");
6216 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6217 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6218 mubuf
->operands
[0] = Operand(rsrc
);
6219 mubuf
->operands
[1] = offset
.type() == RegType::vgpr
? Operand(offset
) : Operand(v1
);
6220 mubuf
->operands
[2] = offset
.type() == RegType::sgpr
? Operand(offset
) : Operand((uint32_t) 0);
6221 mubuf
->operands
[3] = Operand(data
);
6222 if (return_previous
)
6223 mubuf
->definitions
[0] = Definition(dst
);
6225 mubuf
->offen
= (offset
.type() == RegType::vgpr
);
6226 mubuf
->glc
= return_previous
;
6227 mubuf
->dlc
= false; /* Not needed for atomics */
6228 mubuf
->disable_wqm
= true;
6229 mubuf
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6230 ctx
->program
->needs_exact
= true;
6231 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6234 void visit_get_buffer_size(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6236 Temp index
= convert_pointer_to_64_bit(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6237 Builder
bld(ctx
->program
, ctx
->block
);
6238 Temp desc
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), index
, Operand(0u));
6239 get_buffer_size(ctx
, desc
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), false);
6242 void visit_load_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6244 Builder
bld(ctx
->program
, ctx
->block
);
6245 unsigned num_components
= instr
->num_components
;
6246 unsigned component_size
= instr
->dest
.ssa
.bit_size
/ 8;
6248 LoadEmitInfo info
= {Operand(get_ssa_temp(ctx
, instr
->src
[0].ssa
)),
6249 get_ssa_temp(ctx
, &instr
->dest
.ssa
),
6250 num_components
, component_size
};
6251 info
.glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
);
6252 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6253 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6254 info
.sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6255 /* VMEM stores don't update the SMEM cache and it's difficult to prove that
6256 * it's safe to use SMEM */
6257 bool can_use_smem
= nir_intrinsic_access(instr
) & ACCESS_NON_WRITEABLE
;
6258 if (info
.dst
.type() == RegType::vgpr
|| (info
.glc
&& ctx
->options
->chip_class
< GFX8
) || !can_use_smem
) {
6259 emit_global_load(ctx
, bld
, &info
);
6261 info
.offset
= Operand(bld
.as_uniform(info
.offset
));
6262 emit_smem_load(ctx
, bld
, &info
);
6266 void visit_store_global(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6268 Builder
bld(ctx
->program
, ctx
->block
);
6269 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6270 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6272 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6273 Temp addr
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
6274 memory_sync_info sync
= get_memory_sync_info(instr
, storage_buffer
, 0);
6275 bool glc
= nir_intrinsic_access(instr
) & (ACCESS_VOLATILE
| ACCESS_COHERENT
| ACCESS_NON_READABLE
);
6277 if (ctx
->options
->chip_class
>= GFX7
)
6278 addr
= as_vgpr(ctx
, addr
);
6280 unsigned write_count
= 0;
6281 Temp write_datas
[32];
6282 unsigned offsets
[32];
6283 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6284 16, &write_count
, write_datas
, offsets
);
6286 for (unsigned i
= 0; i
< write_count
; i
++) {
6287 if (ctx
->options
->chip_class
>= GFX7
) {
6288 unsigned offset
= offsets
[i
];
6289 Temp store_addr
= addr
;
6290 if (offset
> 0 && ctx
->options
->chip_class
< GFX9
) {
6291 Temp addr0
= bld
.tmp(v1
), addr1
= bld
.tmp(v1
);
6292 Temp new_addr0
= bld
.tmp(v1
), new_addr1
= bld
.tmp(v1
);
6293 Temp carry
= bld
.tmp(bld
.lm
);
6294 bld
.pseudo(aco_opcode::p_split_vector
, Definition(addr0
), Definition(addr1
), addr
);
6296 bld
.vop2(aco_opcode::v_add_co_u32
, Definition(new_addr0
), bld
.hint_vcc(Definition(carry
)),
6297 Operand(offset
), addr0
);
6298 bld
.vop2(aco_opcode::v_addc_co_u32
, Definition(new_addr1
), bld
.def(bld
.lm
),
6300 carry
).def(1).setHint(vcc
);
6302 store_addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), new_addr0
, new_addr1
);
6307 bool global
= ctx
->options
->chip_class
>= GFX9
;
6309 switch (write_datas
[i
].bytes()) {
6311 op
= global
? aco_opcode::global_store_byte
: aco_opcode::flat_store_byte
;
6314 op
= global
? aco_opcode::global_store_short
: aco_opcode::flat_store_short
;
6317 op
= global
? aco_opcode::global_store_dword
: aco_opcode::flat_store_dword
;
6320 op
= global
? aco_opcode::global_store_dwordx2
: aco_opcode::flat_store_dwordx2
;
6323 op
= global
? aco_opcode::global_store_dwordx3
: aco_opcode::flat_store_dwordx3
;
6326 op
= global
? aco_opcode::global_store_dwordx4
: aco_opcode::flat_store_dwordx4
;
6329 unreachable("store_global not implemented for this size.");
6332 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, 0)};
6333 flat
->operands
[0] = Operand(store_addr
);
6334 flat
->operands
[1] = Operand(s1
);
6335 flat
->operands
[2] = Operand(write_datas
[i
]);
6338 flat
->offset
= offset
;
6339 flat
->disable_wqm
= true;
6341 ctx
->program
->needs_exact
= true;
6342 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6344 assert(ctx
->options
->chip_class
== GFX6
);
6346 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6348 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6350 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, 0)};
6351 mubuf
->operands
[0] = Operand(rsrc
);
6352 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6353 mubuf
->operands
[2] = Operand(0u);
6354 mubuf
->operands
[3] = Operand(write_datas
[i
]);
6357 mubuf
->offset
= offsets
[i
];
6358 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6359 mubuf
->disable_wqm
= true;
6361 ctx
->program
->needs_exact
= true;
6362 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6367 void visit_global_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6369 /* return the previous value if dest is ever used */
6370 bool return_previous
= false;
6371 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6372 return_previous
= true;
6375 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6376 return_previous
= true;
6380 Builder
bld(ctx
->program
, ctx
->block
);
6381 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6382 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6384 if (ctx
->options
->chip_class
>= GFX7
)
6385 addr
= as_vgpr(ctx
, addr
);
6387 if (instr
->intrinsic
== nir_intrinsic_global_atomic_comp_swap
)
6388 data
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(RegType::vgpr
, data
.size() * 2),
6389 get_ssa_temp(ctx
, instr
->src
[2].ssa
), data
);
6391 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6393 aco_opcode op32
, op64
;
6395 if (ctx
->options
->chip_class
>= GFX7
) {
6396 bool global
= ctx
->options
->chip_class
>= GFX9
;
6397 switch (instr
->intrinsic
) {
6398 case nir_intrinsic_global_atomic_add
:
6399 op32
= global
? aco_opcode::global_atomic_add
: aco_opcode::flat_atomic_add
;
6400 op64
= global
? aco_opcode::global_atomic_add_x2
: aco_opcode::flat_atomic_add_x2
;
6402 case nir_intrinsic_global_atomic_imin
:
6403 op32
= global
? aco_opcode::global_atomic_smin
: aco_opcode::flat_atomic_smin
;
6404 op64
= global
? aco_opcode::global_atomic_smin_x2
: aco_opcode::flat_atomic_smin_x2
;
6406 case nir_intrinsic_global_atomic_umin
:
6407 op32
= global
? aco_opcode::global_atomic_umin
: aco_opcode::flat_atomic_umin
;
6408 op64
= global
? aco_opcode::global_atomic_umin_x2
: aco_opcode::flat_atomic_umin_x2
;
6410 case nir_intrinsic_global_atomic_imax
:
6411 op32
= global
? aco_opcode::global_atomic_smax
: aco_opcode::flat_atomic_smax
;
6412 op64
= global
? aco_opcode::global_atomic_smax_x2
: aco_opcode::flat_atomic_smax_x2
;
6414 case nir_intrinsic_global_atomic_umax
:
6415 op32
= global
? aco_opcode::global_atomic_umax
: aco_opcode::flat_atomic_umax
;
6416 op64
= global
? aco_opcode::global_atomic_umax_x2
: aco_opcode::flat_atomic_umax_x2
;
6418 case nir_intrinsic_global_atomic_and
:
6419 op32
= global
? aco_opcode::global_atomic_and
: aco_opcode::flat_atomic_and
;
6420 op64
= global
? aco_opcode::global_atomic_and_x2
: aco_opcode::flat_atomic_and_x2
;
6422 case nir_intrinsic_global_atomic_or
:
6423 op32
= global
? aco_opcode::global_atomic_or
: aco_opcode::flat_atomic_or
;
6424 op64
= global
? aco_opcode::global_atomic_or_x2
: aco_opcode::flat_atomic_or_x2
;
6426 case nir_intrinsic_global_atomic_xor
:
6427 op32
= global
? aco_opcode::global_atomic_xor
: aco_opcode::flat_atomic_xor
;
6428 op64
= global
? aco_opcode::global_atomic_xor_x2
: aco_opcode::flat_atomic_xor_x2
;
6430 case nir_intrinsic_global_atomic_exchange
:
6431 op32
= global
? aco_opcode::global_atomic_swap
: aco_opcode::flat_atomic_swap
;
6432 op64
= global
? aco_opcode::global_atomic_swap_x2
: aco_opcode::flat_atomic_swap_x2
;
6434 case nir_intrinsic_global_atomic_comp_swap
:
6435 op32
= global
? aco_opcode::global_atomic_cmpswap
: aco_opcode::flat_atomic_cmpswap
;
6436 op64
= global
? aco_opcode::global_atomic_cmpswap_x2
: aco_opcode::flat_atomic_cmpswap_x2
;
6439 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6442 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6443 aco_ptr
<FLAT_instruction
> flat
{create_instruction
<FLAT_instruction
>(op
, global
? Format::GLOBAL
: Format::FLAT
, 3, return_previous
? 1 : 0)};
6444 flat
->operands
[0] = Operand(addr
);
6445 flat
->operands
[1] = Operand(s1
);
6446 flat
->operands
[2] = Operand(data
);
6447 if (return_previous
)
6448 flat
->definitions
[0] = Definition(dst
);
6449 flat
->glc
= return_previous
;
6450 flat
->dlc
= false; /* Not needed for atomics */
6452 flat
->disable_wqm
= true;
6453 flat
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6454 ctx
->program
->needs_exact
= true;
6455 ctx
->block
->instructions
.emplace_back(std::move(flat
));
6457 assert(ctx
->options
->chip_class
== GFX6
);
6459 switch (instr
->intrinsic
) {
6460 case nir_intrinsic_global_atomic_add
:
6461 op32
= aco_opcode::buffer_atomic_add
;
6462 op64
= aco_opcode::buffer_atomic_add_x2
;
6464 case nir_intrinsic_global_atomic_imin
:
6465 op32
= aco_opcode::buffer_atomic_smin
;
6466 op64
= aco_opcode::buffer_atomic_smin_x2
;
6468 case nir_intrinsic_global_atomic_umin
:
6469 op32
= aco_opcode::buffer_atomic_umin
;
6470 op64
= aco_opcode::buffer_atomic_umin_x2
;
6472 case nir_intrinsic_global_atomic_imax
:
6473 op32
= aco_opcode::buffer_atomic_smax
;
6474 op64
= aco_opcode::buffer_atomic_smax_x2
;
6476 case nir_intrinsic_global_atomic_umax
:
6477 op32
= aco_opcode::buffer_atomic_umax
;
6478 op64
= aco_opcode::buffer_atomic_umax_x2
;
6480 case nir_intrinsic_global_atomic_and
:
6481 op32
= aco_opcode::buffer_atomic_and
;
6482 op64
= aco_opcode::buffer_atomic_and_x2
;
6484 case nir_intrinsic_global_atomic_or
:
6485 op32
= aco_opcode::buffer_atomic_or
;
6486 op64
= aco_opcode::buffer_atomic_or_x2
;
6488 case nir_intrinsic_global_atomic_xor
:
6489 op32
= aco_opcode::buffer_atomic_xor
;
6490 op64
= aco_opcode::buffer_atomic_xor_x2
;
6492 case nir_intrinsic_global_atomic_exchange
:
6493 op32
= aco_opcode::buffer_atomic_swap
;
6494 op64
= aco_opcode::buffer_atomic_swap_x2
;
6496 case nir_intrinsic_global_atomic_comp_swap
:
6497 op32
= aco_opcode::buffer_atomic_cmpswap
;
6498 op64
= aco_opcode::buffer_atomic_cmpswap_x2
;
6501 unreachable("visit_atomic_global should only be called with nir_intrinsic_global_atomic_* instructions.");
6504 Temp rsrc
= get_gfx6_global_rsrc(bld
, addr
);
6506 aco_opcode op
= instr
->dest
.ssa
.bit_size
== 32 ? op32
: op64
;
6508 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 4, return_previous
? 1 : 0)};
6509 mubuf
->operands
[0] = Operand(rsrc
);
6510 mubuf
->operands
[1] = addr
.type() == RegType::vgpr
? Operand(addr
) : Operand(v1
);
6511 mubuf
->operands
[2] = Operand(0u);
6512 mubuf
->operands
[3] = Operand(data
);
6513 if (return_previous
)
6514 mubuf
->definitions
[0] = Definition(dst
);
6515 mubuf
->glc
= return_previous
;
6518 mubuf
->addr64
= addr
.type() == RegType::vgpr
;
6519 mubuf
->disable_wqm
= true;
6520 mubuf
->sync
= get_memory_sync_info(instr
, storage_buffer
, semantic_atomicrmw
);
6521 ctx
->program
->needs_exact
= true;
6522 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
6526 sync_scope
translate_nir_scope(nir_scope scope
)
6529 case NIR_SCOPE_NONE
:
6530 case NIR_SCOPE_INVOCATION
:
6531 return scope_invocation
;
6532 case NIR_SCOPE_SUBGROUP
:
6533 return scope_subgroup
;
6534 case NIR_SCOPE_WORKGROUP
:
6535 return scope_workgroup
;
6536 case NIR_SCOPE_QUEUE_FAMILY
:
6537 return scope_queuefamily
;
6538 case NIR_SCOPE_DEVICE
:
6539 return scope_device
;
6541 unreachable("invalid scope");
6544 void emit_scoped_barrier(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6545 Builder
bld(ctx
->program
, ctx
->block
);
6547 unsigned semantics
= 0;
6548 unsigned storage
= 0;
6549 sync_scope mem_scope
= translate_nir_scope(nir_intrinsic_memory_scope(instr
));
6550 sync_scope exec_scope
= translate_nir_scope(nir_intrinsic_execution_scope(instr
));
6552 unsigned nir_storage
= nir_intrinsic_memory_modes(instr
);
6553 if (nir_storage
& (nir_var_mem_ssbo
| nir_var_mem_global
))
6554 storage
|= storage_buffer
| storage_image
; //TODO: split this when NIR gets nir_var_mem_image
6555 if (ctx
->shader
->info
.stage
== MESA_SHADER_COMPUTE
&& (nir_storage
& nir_var_mem_shared
))
6556 storage
|= storage_shared
;
6557 if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
&& (nir_storage
& nir_var_shader_out
))
6558 storage
|= storage_shared
;
6560 unsigned nir_semantics
= nir_intrinsic_memory_semantics(instr
);
6561 if (nir_semantics
& NIR_MEMORY_ACQUIRE
)
6562 semantics
|= semantic_acquire
| semantic_release
;
6563 if (nir_semantics
& NIR_MEMORY_RELEASE
)
6564 semantics
|= semantic_acquire
| semantic_release
;
6566 assert(!(nir_semantics
& (NIR_MEMORY_MAKE_AVAILABLE
| NIR_MEMORY_MAKE_VISIBLE
)));
6568 bld
.barrier(aco_opcode::p_barrier
,
6569 memory_sync_info((storage_class
)storage
, (memory_semantics
)semantics
, mem_scope
),
6573 void visit_load_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6575 // TODO: implement sparse reads using ds_read2_b32 and nir_ssa_def_components_read()
6576 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6577 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6578 Builder
bld(ctx
->program
, ctx
->block
);
6580 unsigned elem_size_bytes
= instr
->dest
.ssa
.bit_size
/ 8;
6581 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6582 load_lds(ctx
, elem_size_bytes
, dst
, address
, nir_intrinsic_base(instr
), align
);
6585 void visit_store_shared(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6587 unsigned writemask
= nir_intrinsic_write_mask(instr
);
6588 Temp data
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
6589 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6590 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6592 unsigned align
= nir_intrinsic_align_mul(instr
) ? nir_intrinsic_align(instr
) : elem_size_bytes
;
6593 store_lds(ctx
, elem_size_bytes
, data
, writemask
, address
, nir_intrinsic_base(instr
), align
);
6596 void visit_shared_atomic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
6598 unsigned offset
= nir_intrinsic_base(instr
);
6599 Builder
bld(ctx
->program
, ctx
->block
);
6600 Operand m
= load_lds_size_m0(bld
);
6601 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6602 Temp address
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6604 unsigned num_operands
= 3;
6605 aco_opcode op32
, op64
, op32_rtn
, op64_rtn
;
6606 switch(instr
->intrinsic
) {
6607 case nir_intrinsic_shared_atomic_add
:
6608 op32
= aco_opcode::ds_add_u32
;
6609 op64
= aco_opcode::ds_add_u64
;
6610 op32_rtn
= aco_opcode::ds_add_rtn_u32
;
6611 op64_rtn
= aco_opcode::ds_add_rtn_u64
;
6613 case nir_intrinsic_shared_atomic_imin
:
6614 op32
= aco_opcode::ds_min_i32
;
6615 op64
= aco_opcode::ds_min_i64
;
6616 op32_rtn
= aco_opcode::ds_min_rtn_i32
;
6617 op64_rtn
= aco_opcode::ds_min_rtn_i64
;
6619 case nir_intrinsic_shared_atomic_umin
:
6620 op32
= aco_opcode::ds_min_u32
;
6621 op64
= aco_opcode::ds_min_u64
;
6622 op32_rtn
= aco_opcode::ds_min_rtn_u32
;
6623 op64_rtn
= aco_opcode::ds_min_rtn_u64
;
6625 case nir_intrinsic_shared_atomic_imax
:
6626 op32
= aco_opcode::ds_max_i32
;
6627 op64
= aco_opcode::ds_max_i64
;
6628 op32_rtn
= aco_opcode::ds_max_rtn_i32
;
6629 op64_rtn
= aco_opcode::ds_max_rtn_i64
;
6631 case nir_intrinsic_shared_atomic_umax
:
6632 op32
= aco_opcode::ds_max_u32
;
6633 op64
= aco_opcode::ds_max_u64
;
6634 op32_rtn
= aco_opcode::ds_max_rtn_u32
;
6635 op64_rtn
= aco_opcode::ds_max_rtn_u64
;
6637 case nir_intrinsic_shared_atomic_and
:
6638 op32
= aco_opcode::ds_and_b32
;
6639 op64
= aco_opcode::ds_and_b64
;
6640 op32_rtn
= aco_opcode::ds_and_rtn_b32
;
6641 op64_rtn
= aco_opcode::ds_and_rtn_b64
;
6643 case nir_intrinsic_shared_atomic_or
:
6644 op32
= aco_opcode::ds_or_b32
;
6645 op64
= aco_opcode::ds_or_b64
;
6646 op32_rtn
= aco_opcode::ds_or_rtn_b32
;
6647 op64_rtn
= aco_opcode::ds_or_rtn_b64
;
6649 case nir_intrinsic_shared_atomic_xor
:
6650 op32
= aco_opcode::ds_xor_b32
;
6651 op64
= aco_opcode::ds_xor_b64
;
6652 op32_rtn
= aco_opcode::ds_xor_rtn_b32
;
6653 op64_rtn
= aco_opcode::ds_xor_rtn_b64
;
6655 case nir_intrinsic_shared_atomic_exchange
:
6656 op32
= aco_opcode::ds_write_b32
;
6657 op64
= aco_opcode::ds_write_b64
;
6658 op32_rtn
= aco_opcode::ds_wrxchg_rtn_b32
;
6659 op64_rtn
= aco_opcode::ds_wrxchg_rtn_b64
;
6661 case nir_intrinsic_shared_atomic_comp_swap
:
6662 op32
= aco_opcode::ds_cmpst_b32
;
6663 op64
= aco_opcode::ds_cmpst_b64
;
6664 op32_rtn
= aco_opcode::ds_cmpst_rtn_b32
;
6665 op64_rtn
= aco_opcode::ds_cmpst_rtn_b64
;
6668 case nir_intrinsic_shared_atomic_fadd
:
6669 op32
= aco_opcode::ds_add_f32
;
6670 op32_rtn
= aco_opcode::ds_add_rtn_f32
;
6671 op64
= aco_opcode::num_opcodes
;
6672 op64_rtn
= aco_opcode::num_opcodes
;
6675 unreachable("Unhandled shared atomic intrinsic");
6678 /* return the previous value if dest is ever used */
6679 bool return_previous
= false;
6680 nir_foreach_use_safe(use_src
, &instr
->dest
.ssa
) {
6681 return_previous
= true;
6684 nir_foreach_if_use_safe(use_src
, &instr
->dest
.ssa
) {
6685 return_previous
= true;
6690 if (data
.size() == 1) {
6691 assert(instr
->dest
.ssa
.bit_size
== 32);
6692 op
= return_previous
? op32_rtn
: op32
;
6694 assert(instr
->dest
.ssa
.bit_size
== 64);
6695 op
= return_previous
? op64_rtn
: op64
;
6698 if (offset
> 65535) {
6699 address
= bld
.vadd32(bld
.def(v1
), Operand(offset
), address
);
6703 aco_ptr
<DS_instruction
> ds
;
6704 ds
.reset(create_instruction
<DS_instruction
>(op
, Format::DS
, num_operands
, return_previous
? 1 : 0));
6705 ds
->operands
[0] = Operand(address
);
6706 ds
->operands
[1] = Operand(data
);
6707 if (num_operands
== 4)
6708 ds
->operands
[2] = Operand(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
6709 ds
->operands
[num_operands
- 1] = m
;
6710 ds
->offset0
= offset
;
6711 if (return_previous
)
6712 ds
->definitions
[0] = Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
6713 ds
->sync
= memory_sync_info(storage_shared
, semantic_atomicrmw
);
6714 ctx
->block
->instructions
.emplace_back(std::move(ds
));
6717 Temp
get_scratch_resource(isel_context
*ctx
)
6719 Builder
bld(ctx
->program
, ctx
->block
);
6720 Temp scratch_addr
= ctx
->program
->private_segment_buffer
;
6721 if (ctx
->stage
!= compute_cs
)
6722 scratch_addr
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), scratch_addr
, Operand(0u));
6724 uint32_t rsrc_conf
= S_008F0C_ADD_TID_ENABLE(1) |
6725 S_008F0C_INDEX_STRIDE(ctx
->program
->wave_size
== 64 ? 3 : 2);
6727 if (ctx
->program
->chip_class
>= GFX10
) {
6728 rsrc_conf
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
6729 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
6730 S_008F0C_RESOURCE_LEVEL(1);
6731 } else if (ctx
->program
->chip_class
<= GFX7
) { /* dfmt modifies stride on GFX8/GFX9 when ADD_TID_EN=1 */
6732 rsrc_conf
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
6733 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
6736 /* older generations need element size = 4 bytes. element size removed in GFX9 */
6737 if (ctx
->program
->chip_class
<= GFX8
)
6738 rsrc_conf
|= S_008F0C_ELEMENT_SIZE(1);
6740 return bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), scratch_addr
, Operand(-1u), Operand(rsrc_conf
));
6743 void visit_load_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6744 Builder
bld(ctx
->program
, ctx
->block
);
6745 Temp rsrc
= get_scratch_resource(ctx
);
6746 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6747 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6749 LoadEmitInfo info
= {Operand(offset
), dst
, instr
->dest
.ssa
.num_components
,
6750 instr
->dest
.ssa
.bit_size
/ 8u, rsrc
};
6751 info
.align_mul
= nir_intrinsic_align_mul(instr
);
6752 info
.align_offset
= nir_intrinsic_align_offset(instr
);
6753 info
.swizzle_component_size
= ctx
->program
->chip_class
<= GFX8
? 4 : 0;
6754 info
.sync
= memory_sync_info(storage_scratch
, semantic_private
);
6755 info
.soffset
= ctx
->program
->scratch_offset
;
6756 emit_scratch_load(ctx
, bld
, &info
);
6759 void visit_store_scratch(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6760 Builder
bld(ctx
->program
, ctx
->block
);
6761 Temp rsrc
= get_scratch_resource(ctx
);
6762 Temp data
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6763 Temp offset
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[1].ssa
));
6765 unsigned elem_size_bytes
= instr
->src
[0].ssa
->bit_size
/ 8;
6766 unsigned writemask
= widen_mask(nir_intrinsic_write_mask(instr
), elem_size_bytes
);
6768 unsigned write_count
= 0;
6769 Temp write_datas
[32];
6770 unsigned offsets
[32];
6771 unsigned swizzle_component_size
= ctx
->program
->chip_class
<= GFX8
? 4 : 16;
6772 split_buffer_store(ctx
, instr
, false, RegType::vgpr
, data
, writemask
,
6773 swizzle_component_size
, &write_count
, write_datas
, offsets
);
6775 for (unsigned i
= 0; i
< write_count
; i
++) {
6776 aco_opcode op
= get_buffer_store_op(false, write_datas
[i
].bytes());
6777 Instruction
*instr
= bld
.mubuf(op
, rsrc
, offset
, ctx
->program
->scratch_offset
, write_datas
[i
], offsets
[i
], true, true);
6778 static_cast<MUBUF_instruction
*>(instr
)->sync
= memory_sync_info(storage_scratch
, semantic_private
);
6782 void visit_load_sample_mask_in(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6783 uint8_t log2_ps_iter_samples
;
6784 if (ctx
->program
->info
->ps
.force_persample
) {
6785 log2_ps_iter_samples
=
6786 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
6788 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
6791 /* The bit pattern matches that used by fixed function fragment
6793 static const unsigned ps_iter_masks
[] = {
6794 0xffff, /* not used */
6800 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
6802 Builder
bld(ctx
->program
, ctx
->block
);
6804 Temp sample_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
6805 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
6806 Temp ps_iter_mask
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(ps_iter_masks
[log2_ps_iter_samples
]));
6807 Temp mask
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), sample_id
, ps_iter_mask
);
6808 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
6809 bld
.vop2(aco_opcode::v_and_b32
, Definition(dst
), mask
, get_arg(ctx
, ctx
->args
->ac
.sample_coverage
));
6812 void visit_emit_vertex_with_counter(isel_context
*ctx
, nir_intrinsic_instr
*instr
) {
6813 Builder
bld(ctx
->program
, ctx
->block
);
6815 unsigned stream
= nir_intrinsic_stream_id(instr
);
6816 Temp next_vertex
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
6817 next_vertex
= bld
.v_mul_imm(bld
.def(v1
), next_vertex
, 4u);
6818 nir_const_value
*next_vertex_cv
= nir_src_as_const_value(instr
->src
[0]);
6821 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_GSVS_GS
* 16u));
6823 unsigned num_components
=
6824 ctx
->program
->info
->gs
.num_stream_output_components
[stream
];
6825 assert(num_components
);
6827 unsigned stride
= 4u * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
6828 unsigned stream_offset
= 0;
6829 for (unsigned i
= 0; i
< stream
; i
++) {
6830 unsigned prev_stride
= 4u * ctx
->program
->info
->gs
.num_stream_output_components
[i
] * ctx
->shader
->info
.gs
.vertices_out
;
6831 stream_offset
+= prev_stride
* ctx
->program
->wave_size
;
6834 /* Limit on the stride field for <= GFX7. */
6835 assert(stride
< (1 << 14));
6837 Temp gsvs_dwords
[4];
6838 for (unsigned i
= 0; i
< 4; i
++)
6839 gsvs_dwords
[i
] = bld
.tmp(s1
);
6840 bld
.pseudo(aco_opcode::p_split_vector
,
6841 Definition(gsvs_dwords
[0]),
6842 Definition(gsvs_dwords
[1]),
6843 Definition(gsvs_dwords
[2]),
6844 Definition(gsvs_dwords
[3]),
6847 if (stream_offset
) {
6848 Temp stream_offset_tmp
= bld
.copy(bld
.def(s1
), Operand(stream_offset
));
6850 Temp carry
= bld
.tmp(s1
);
6851 gsvs_dwords
[0] = bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.scc(Definition(carry
)), gsvs_dwords
[0], stream_offset_tmp
);
6852 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(0u), bld
.scc(carry
));
6855 gsvs_dwords
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), gsvs_dwords
[1], Operand(S_008F04_STRIDE(stride
)));
6856 gsvs_dwords
[2] = bld
.copy(bld
.def(s1
), Operand((uint32_t)ctx
->program
->wave_size
));
6858 gsvs_ring
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
6859 gsvs_dwords
[0], gsvs_dwords
[1], gsvs_dwords
[2], gsvs_dwords
[3]);
6861 unsigned offset
= 0;
6862 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; i
++) {
6863 if (ctx
->program
->info
->gs
.output_streams
[i
] != stream
)
6866 for (unsigned j
= 0; j
< 4; j
++) {
6867 if (!(ctx
->program
->info
->gs
.output_usage_mask
[i
] & (1 << j
)))
6870 if (ctx
->outputs
.mask
[i
] & (1 << j
)) {
6871 Operand vaddr_offset
= next_vertex_cv
? Operand(v1
) : Operand(next_vertex
);
6872 unsigned const_offset
= (offset
+ (next_vertex_cv
? next_vertex_cv
->u32
: 0u)) * 4u;
6873 if (const_offset
>= 4096u) {
6874 if (vaddr_offset
.isUndefined())
6875 vaddr_offset
= bld
.copy(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u));
6877 vaddr_offset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), vaddr_offset
);
6878 const_offset
%= 4096u;
6881 aco_ptr
<MTBUF_instruction
> mtbuf
{create_instruction
<MTBUF_instruction
>(aco_opcode::tbuffer_store_format_x
, Format::MTBUF
, 4, 0)};
6882 mtbuf
->operands
[0] = Operand(gsvs_ring
);
6883 mtbuf
->operands
[1] = vaddr_offset
;
6884 mtbuf
->operands
[2] = Operand(get_arg(ctx
, ctx
->args
->gs2vs_offset
));
6885 mtbuf
->operands
[3] = Operand(ctx
->outputs
.temps
[i
* 4u + j
]);
6886 mtbuf
->offen
= !vaddr_offset
.isUndefined();
6887 mtbuf
->dfmt
= V_008F0C_BUF_DATA_FORMAT_32
;
6888 mtbuf
->nfmt
= V_008F0C_BUF_NUM_FORMAT_UINT
;
6889 mtbuf
->offset
= const_offset
;
6892 mtbuf
->sync
= memory_sync_info(storage_vmem_output
, semantic_can_reorder
);
6893 bld
.insert(std::move(mtbuf
));
6896 offset
+= ctx
->shader
->info
.gs
.vertices_out
;
6899 /* outputs for the next vertex are undefined and keeping them around can
6900 * create invalid IR with control flow */
6901 ctx
->outputs
.mask
[i
] = 0;
6904 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(false, true, stream
));
6907 Temp
emit_boolean_reduce(isel_context
*ctx
, nir_op op
, unsigned cluster_size
, Temp src
)
6909 Builder
bld(ctx
->program
, ctx
->block
);
6911 if (cluster_size
== 1) {
6913 } if (op
== nir_op_iand
&& cluster_size
== 4) {
6914 //subgroupClusteredAnd(val, 4) -> ~wqm(exec & ~val)
6915 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6916 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6917 bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
));
6918 } else if (op
== nir_op_ior
&& cluster_size
== 4) {
6919 //subgroupClusteredOr(val, 4) -> wqm(val & exec)
6920 return bld
.sop1(Builder::s_wqm
, bld
.def(bld
.lm
), bld
.def(s1
, scc
),
6921 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)));
6922 } else if (op
== nir_op_iand
&& cluster_size
== ctx
->program
->wave_size
) {
6923 //subgroupAnd(val) -> (exec & ~val) == 0
6924 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
6925 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
6926 return bld
.sop1(Builder::s_not
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), cond
);
6927 } else if (op
== nir_op_ior
&& cluster_size
== ctx
->program
->wave_size
) {
6928 //subgroupOr(val) -> (val & exec) != 0
6929 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
)).def(1).getTemp();
6930 return bool_to_vector_condition(ctx
, tmp
);
6931 } else if (op
== nir_op_ixor
&& cluster_size
== ctx
->program
->wave_size
) {
6932 //subgroupXor(val) -> s_bcnt1_i32_b64(val & exec) & 1
6933 Temp tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6934 tmp
= bld
.sop1(Builder::s_bcnt1_i32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
);
6935 tmp
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp
, Operand(1u)).def(1).getTemp();
6936 return bool_to_vector_condition(ctx
, tmp
);
6938 //subgroupClustered{And,Or,Xor}(val, n) ->
6939 //lane_id = v_mbcnt_hi_u32_b32(-1, v_mbcnt_lo_u32_b32(-1, 0)) ; just v_mbcnt_lo_u32_b32 on wave32
6940 //cluster_offset = ~(n - 1) & lane_id
6941 //cluster_mask = ((1 << n) - 1)
6942 //subgroupClusteredAnd():
6943 // return ((val | ~exec) >> cluster_offset) & cluster_mask == cluster_mask
6944 //subgroupClusteredOr():
6945 // return ((val & exec) >> cluster_offset) & cluster_mask != 0
6946 //subgroupClusteredXor():
6947 // return v_bnt_u32_b32(((val & exec) >> cluster_offset) & cluster_mask, 0) & 1 != 0
6948 Temp lane_id
= emit_mbcnt(ctx
, bld
.def(v1
));
6949 Temp cluster_offset
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(~uint32_t(cluster_size
- 1)), lane_id
);
6952 if (op
== nir_op_iand
)
6953 tmp
= bld
.sop2(Builder::s_orn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6955 tmp
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6957 uint32_t cluster_mask
= cluster_size
== 32 ? -1 : (1u << cluster_size
) - 1u;
6959 if (ctx
->program
->chip_class
<= GFX7
)
6960 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), tmp
, cluster_offset
);
6961 else if (ctx
->program
->wave_size
== 64)
6962 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), cluster_offset
, tmp
);
6964 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), cluster_offset
, tmp
);
6965 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
6966 if (cluster_mask
!= 0xffffffff)
6967 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(cluster_mask
), tmp
);
6969 Definition cmp_def
= Definition();
6970 if (op
== nir_op_iand
) {
6971 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(cluster_mask
), tmp
).def(0);
6972 } else if (op
== nir_op_ior
) {
6973 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6974 } else if (op
== nir_op_ixor
) {
6975 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u),
6976 bld
.vop3(aco_opcode::v_bcnt_u32_b32
, bld
.def(v1
), tmp
, Operand(0u)));
6977 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
).def(0);
6979 cmp_def
.setHint(vcc
);
6980 return cmp_def
.getTemp();
6984 Temp
emit_boolean_exclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
6986 Builder
bld(ctx
->program
, ctx
->block
);
6988 //subgroupExclusiveAnd(val) -> mbcnt(exec & ~val) == 0
6989 //subgroupExclusiveOr(val) -> mbcnt(val & exec) != 0
6990 //subgroupExclusiveXor(val) -> mbcnt(val & exec) & 1 != 0
6992 if (op
== nir_op_iand
)
6993 tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
6995 tmp
= bld
.sop2(Builder::s_and
, bld
.def(s2
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
6997 Builder::Result lohi
= bld
.pseudo(aco_opcode::p_split_vector
, bld
.def(s1
), bld
.def(s1
), tmp
);
6998 Temp lo
= lohi
.def(0).getTemp();
6999 Temp hi
= lohi
.def(1).getTemp();
7000 Temp mbcnt
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(lo
), Operand(hi
));
7002 Definition cmp_def
= Definition();
7003 if (op
== nir_op_iand
)
7004 cmp_def
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7005 else if (op
== nir_op_ior
)
7006 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), mbcnt
).def(0);
7007 else if (op
== nir_op_ixor
)
7008 cmp_def
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u),
7009 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), mbcnt
)).def(0);
7010 cmp_def
.setHint(vcc
);
7011 return cmp_def
.getTemp();
7014 Temp
emit_boolean_inclusive_scan(isel_context
*ctx
, nir_op op
, Temp src
)
7016 Builder
bld(ctx
->program
, ctx
->block
);
7018 //subgroupInclusiveAnd(val) -> subgroupExclusiveAnd(val) && val
7019 //subgroupInclusiveOr(val) -> subgroupExclusiveOr(val) || val
7020 //subgroupInclusiveXor(val) -> subgroupExclusiveXor(val) ^^ val
7021 Temp tmp
= emit_boolean_exclusive_scan(ctx
, op
, src
);
7022 if (op
== nir_op_iand
)
7023 return bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7024 else if (op
== nir_op_ior
)
7025 return bld
.sop2(Builder::s_or
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7026 else if (op
== nir_op_ixor
)
7027 return bld
.sop2(Builder::s_xor
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), tmp
, src
);
7033 void emit_uniform_subgroup(isel_context
*ctx
, nir_intrinsic_instr
*instr
, Temp src
)
7035 Builder
bld(ctx
->program
, ctx
->block
);
7036 Definition
dst(get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7037 if (src
.regClass().type() == RegType::vgpr
) {
7038 bld
.pseudo(aco_opcode::p_as_uniform
, dst
, src
);
7039 } else if (src
.regClass() == s1
) {
7040 bld
.sop1(aco_opcode::s_mov_b32
, dst
, src
);
7041 } else if (src
.regClass() == s2
) {
7042 bld
.sop1(aco_opcode::s_mov_b64
, dst
, src
);
7044 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7048 void emit_interp_center(isel_context
*ctx
, Temp dst
, Temp pos1
, Temp pos2
)
7050 Builder
bld(ctx
->program
, ctx
->block
);
7051 Temp persp_center
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7052 Temp p1
= emit_extract_vector(ctx
, persp_center
, 0, v1
);
7053 Temp p2
= emit_extract_vector(ctx
, persp_center
, 1, v1
);
7055 Temp ddx_1
, ddx_2
, ddy_1
, ddy_2
;
7056 uint32_t dpp_ctrl0
= dpp_quad_perm(0, 0, 0, 0);
7057 uint32_t dpp_ctrl1
= dpp_quad_perm(1, 1, 1, 1);
7058 uint32_t dpp_ctrl2
= dpp_quad_perm(2, 2, 2, 2);
7061 if (ctx
->program
->chip_class
>= GFX8
) {
7062 Temp tl_1
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p1
, dpp_ctrl0
);
7063 ddx_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl1
);
7064 ddy_1
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p1
, tl_1
, dpp_ctrl2
);
7065 Temp tl_2
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), p2
, dpp_ctrl0
);
7066 ddx_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl1
);
7067 ddy_2
= bld
.vop2_dpp(aco_opcode::v_sub_f32
, bld
.def(v1
), p2
, tl_2
, dpp_ctrl2
);
7069 Temp tl_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl0
);
7070 ddx_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl1
);
7071 ddx_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_1
, tl_1
);
7072 ddx_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p1
, (1 << 15) | dpp_ctrl2
);
7073 ddx_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddx_2
, tl_1
);
7074 Temp tl_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl0
);
7075 ddy_1
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl1
);
7076 ddy_1
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_1
, tl_2
);
7077 ddy_2
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), p2
, (1 << 15) | dpp_ctrl2
);
7078 ddy_2
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), ddy_2
, tl_2
);
7081 /* res_k = p_k + ddx_k * pos1 + ddy_k * pos2 */
7082 aco_opcode mad
= ctx
->program
->chip_class
>= GFX10_3
? aco_opcode::v_fma_f32
: aco_opcode::v_mad_f32
;
7083 Temp tmp1
= bld
.vop3(mad
, bld
.def(v1
), ddx_1
, pos1
, p1
);
7084 Temp tmp2
= bld
.vop3(mad
, bld
.def(v1
), ddx_2
, pos1
, p2
);
7085 tmp1
= bld
.vop3(mad
, bld
.def(v1
), ddy_1
, pos2
, tmp1
);
7086 tmp2
= bld
.vop3(mad
, bld
.def(v1
), ddy_2
, pos2
, tmp2
);
7087 Temp wqm1
= bld
.tmp(v1
);
7088 emit_wqm(ctx
, tmp1
, wqm1
, true);
7089 Temp wqm2
= bld
.tmp(v1
);
7090 emit_wqm(ctx
, tmp2
, wqm2
, true);
7091 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), wqm1
, wqm2
);
7095 void visit_intrinsic(isel_context
*ctx
, nir_intrinsic_instr
*instr
)
7097 Builder
bld(ctx
->program
, ctx
->block
);
7098 switch(instr
->intrinsic
) {
7099 case nir_intrinsic_load_barycentric_sample
:
7100 case nir_intrinsic_load_barycentric_pixel
:
7101 case nir_intrinsic_load_barycentric_centroid
: {
7102 glsl_interp_mode mode
= (glsl_interp_mode
)nir_intrinsic_interp_mode(instr
);
7103 Temp bary
= Temp(0, s2
);
7105 case INTERP_MODE_SMOOTH
:
7106 case INTERP_MODE_NONE
:
7107 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7108 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_center
);
7109 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7110 bary
= ctx
->persp_centroid
;
7111 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7112 bary
= get_arg(ctx
, ctx
->args
->ac
.persp_sample
);
7114 case INTERP_MODE_NOPERSPECTIVE
:
7115 if (instr
->intrinsic
== nir_intrinsic_load_barycentric_pixel
)
7116 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_center
);
7117 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
7118 bary
= ctx
->linear_centroid
;
7119 else if (instr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
7120 bary
= get_arg(ctx
, ctx
->args
->ac
.linear_sample
);
7125 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7126 Temp p1
= emit_extract_vector(ctx
, bary
, 0, v1
);
7127 Temp p2
= emit_extract_vector(ctx
, bary
, 1, v1
);
7128 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7129 Operand(p1
), Operand(p2
));
7130 emit_split_vector(ctx
, dst
, 2);
7133 case nir_intrinsic_load_barycentric_model
: {
7134 Temp model
= get_arg(ctx
, ctx
->args
->ac
.pull_model
);
7136 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7137 Temp p1
= emit_extract_vector(ctx
, model
, 0, v1
);
7138 Temp p2
= emit_extract_vector(ctx
, model
, 1, v1
);
7139 Temp p3
= emit_extract_vector(ctx
, model
, 2, v1
);
7140 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7141 Operand(p1
), Operand(p2
), Operand(p3
));
7142 emit_split_vector(ctx
, dst
, 3);
7145 case nir_intrinsic_load_barycentric_at_sample
: {
7146 uint32_t sample_pos_offset
= RING_PS_SAMPLE_POSITIONS
* 16;
7147 switch (ctx
->options
->key
.fs
.num_samples
) {
7148 case 2: sample_pos_offset
+= 1 << 3; break;
7149 case 4: sample_pos_offset
+= 3 << 3; break;
7150 case 8: sample_pos_offset
+= 7 << 3; break;
7154 Temp addr
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7155 nir_const_value
* const_addr
= nir_src_as_const_value(instr
->src
[0]);
7156 Temp private_segment_buffer
= ctx
->program
->private_segment_buffer
;
7157 //TODO: bounds checking?
7158 if (addr
.type() == RegType::sgpr
) {
7161 sample_pos_offset
+= const_addr
->u32
<< 3;
7162 offset
= Operand(sample_pos_offset
);
7163 } else if (ctx
->options
->chip_class
>= GFX9
) {
7164 offset
= bld
.sop2(aco_opcode::s_lshl3_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7166 offset
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(3u));
7167 offset
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), bld
.def(s1
, scc
), addr
, Operand(sample_pos_offset
));
7170 Operand off
= bld
.copy(bld
.def(s1
), Operand(offset
));
7171 sample_pos
= bld
.smem(aco_opcode::s_load_dwordx2
, bld
.def(s2
), private_segment_buffer
, off
);
7173 } else if (ctx
->options
->chip_class
>= GFX9
) {
7174 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7175 sample_pos
= bld
.global(aco_opcode::global_load_dwordx2
, bld
.def(v2
), addr
, private_segment_buffer
, sample_pos_offset
);
7176 } else if (ctx
->options
->chip_class
>= GFX7
) {
7177 /* addr += private_segment_buffer + sample_pos_offset */
7178 Temp tmp0
= bld
.tmp(s1
);
7179 Temp tmp1
= bld
.tmp(s1
);
7180 bld
.pseudo(aco_opcode::p_split_vector
, Definition(tmp0
), Definition(tmp1
), private_segment_buffer
);
7181 Definition scc_tmp
= bld
.def(s1
, scc
);
7182 tmp0
= bld
.sop2(aco_opcode::s_add_u32
, bld
.def(s1
), scc_tmp
, tmp0
, Operand(sample_pos_offset
));
7183 tmp1
= bld
.sop2(aco_opcode::s_addc_u32
, bld
.def(s1
), bld
.def(s1
, scc
), tmp1
, Operand(0u), bld
.scc(scc_tmp
.getTemp()));
7184 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7185 Temp pck0
= bld
.tmp(v1
);
7186 Temp carry
= bld
.vadd32(Definition(pck0
), tmp0
, addr
, true).def(1).getTemp();
7187 tmp1
= as_vgpr(ctx
, tmp1
);
7188 Temp pck1
= bld
.vop2_e64(aco_opcode::v_addc_co_u32
, bld
.def(v1
), bld
.hint_vcc(bld
.def(bld
.lm
)), tmp1
, Operand(0u), carry
);
7189 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), pck0
, pck1
);
7191 /* sample_pos = flat_load_dwordx2 addr */
7192 sample_pos
= bld
.flat(aco_opcode::flat_load_dwordx2
, bld
.def(v2
), addr
, Operand(s1
));
7194 assert(ctx
->options
->chip_class
== GFX6
);
7196 uint32_t rsrc_conf
= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
7197 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
7198 Temp rsrc
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
), private_segment_buffer
, Operand(0u), Operand(rsrc_conf
));
7200 addr
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(3u), addr
);
7201 addr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), addr
, Operand(0u));
7203 sample_pos
= bld
.tmp(v2
);
7205 aco_ptr
<MUBUF_instruction
> load
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dwordx2
, Format::MUBUF
, 3, 1)};
7206 load
->definitions
[0] = Definition(sample_pos
);
7207 load
->operands
[0] = Operand(rsrc
);
7208 load
->operands
[1] = Operand(addr
);
7209 load
->operands
[2] = Operand(0u);
7210 load
->offset
= sample_pos_offset
;
7212 load
->addr64
= true;
7215 load
->disable_wqm
= false;
7216 ctx
->block
->instructions
.emplace_back(std::move(load
));
7219 /* sample_pos -= 0.5 */
7220 Temp pos1
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7221 Temp pos2
= bld
.tmp(RegClass(sample_pos
.type(), 1));
7222 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), sample_pos
);
7223 pos1
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos1
, Operand(0x3f000000u
));
7224 pos2
= bld
.vop2_e64(aco_opcode::v_sub_f32
, bld
.def(v1
), pos2
, Operand(0x3f000000u
));
7226 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7229 case nir_intrinsic_load_barycentric_at_offset
: {
7230 Temp offset
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7231 RegClass rc
= RegClass(offset
.type(), 1);
7232 Temp pos1
= bld
.tmp(rc
), pos2
= bld
.tmp(rc
);
7233 bld
.pseudo(aco_opcode::p_split_vector
, Definition(pos1
), Definition(pos2
), offset
);
7234 emit_interp_center(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), pos1
, pos2
);
7237 case nir_intrinsic_load_front_face
: {
7238 bld
.vopc(aco_opcode::v_cmp_lg_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7239 Operand(0u), get_arg(ctx
, ctx
->args
->ac
.front_face
)).def(0).setHint(vcc
);
7242 case nir_intrinsic_load_view_index
: {
7243 if (ctx
->stage
& (sw_vs
| sw_gs
| sw_tcs
| sw_tes
)) {
7244 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7245 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.view_index
)));
7251 case nir_intrinsic_load_layer_id
: {
7252 unsigned idx
= nir_intrinsic_base(instr
);
7253 bld
.vintrp(aco_opcode::v_interp_mov_f32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7254 Operand(2u), bld
.m0(get_arg(ctx
, ctx
->args
->ac
.prim_mask
)), idx
, 0);
7257 case nir_intrinsic_load_frag_coord
: {
7258 emit_load_frag_coord(ctx
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), 4);
7261 case nir_intrinsic_load_sample_pos
: {
7262 Temp posx
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[0]);
7263 Temp posy
= get_arg(ctx
, ctx
->args
->ac
.frag_pos
[1]);
7264 bld
.pseudo(aco_opcode::p_create_vector
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7265 posx
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posx
) : Operand(0u),
7266 posy
.id() ? bld
.vop1(aco_opcode::v_fract_f32
, bld
.def(v1
), posy
) : Operand(0u));
7269 case nir_intrinsic_load_tess_coord
:
7270 visit_load_tess_coord(ctx
, instr
);
7272 case nir_intrinsic_load_interpolated_input
:
7273 visit_load_interpolated_input(ctx
, instr
);
7275 case nir_intrinsic_store_output
:
7276 visit_store_output(ctx
, instr
);
7278 case nir_intrinsic_load_input
:
7279 case nir_intrinsic_load_input_vertex
:
7280 visit_load_input(ctx
, instr
);
7282 case nir_intrinsic_load_output
:
7283 visit_load_output(ctx
, instr
);
7285 case nir_intrinsic_load_per_vertex_input
:
7286 visit_load_per_vertex_input(ctx
, instr
);
7288 case nir_intrinsic_load_per_vertex_output
:
7289 visit_load_per_vertex_output(ctx
, instr
);
7291 case nir_intrinsic_store_per_vertex_output
:
7292 visit_store_per_vertex_output(ctx
, instr
);
7294 case nir_intrinsic_load_ubo
:
7295 visit_load_ubo(ctx
, instr
);
7297 case nir_intrinsic_load_push_constant
:
7298 visit_load_push_constant(ctx
, instr
);
7300 case nir_intrinsic_load_constant
:
7301 visit_load_constant(ctx
, instr
);
7303 case nir_intrinsic_vulkan_resource_index
:
7304 visit_load_resource(ctx
, instr
);
7306 case nir_intrinsic_discard
:
7307 visit_discard(ctx
, instr
);
7309 case nir_intrinsic_discard_if
:
7310 visit_discard_if(ctx
, instr
);
7312 case nir_intrinsic_load_shared
:
7313 visit_load_shared(ctx
, instr
);
7315 case nir_intrinsic_store_shared
:
7316 visit_store_shared(ctx
, instr
);
7318 case nir_intrinsic_shared_atomic_add
:
7319 case nir_intrinsic_shared_atomic_imin
:
7320 case nir_intrinsic_shared_atomic_umin
:
7321 case nir_intrinsic_shared_atomic_imax
:
7322 case nir_intrinsic_shared_atomic_umax
:
7323 case nir_intrinsic_shared_atomic_and
:
7324 case nir_intrinsic_shared_atomic_or
:
7325 case nir_intrinsic_shared_atomic_xor
:
7326 case nir_intrinsic_shared_atomic_exchange
:
7327 case nir_intrinsic_shared_atomic_comp_swap
:
7328 case nir_intrinsic_shared_atomic_fadd
:
7329 visit_shared_atomic(ctx
, instr
);
7331 case nir_intrinsic_image_deref_load
:
7332 visit_image_load(ctx
, instr
);
7334 case nir_intrinsic_image_deref_store
:
7335 visit_image_store(ctx
, instr
);
7337 case nir_intrinsic_image_deref_atomic_add
:
7338 case nir_intrinsic_image_deref_atomic_umin
:
7339 case nir_intrinsic_image_deref_atomic_imin
:
7340 case nir_intrinsic_image_deref_atomic_umax
:
7341 case nir_intrinsic_image_deref_atomic_imax
:
7342 case nir_intrinsic_image_deref_atomic_and
:
7343 case nir_intrinsic_image_deref_atomic_or
:
7344 case nir_intrinsic_image_deref_atomic_xor
:
7345 case nir_intrinsic_image_deref_atomic_exchange
:
7346 case nir_intrinsic_image_deref_atomic_comp_swap
:
7347 visit_image_atomic(ctx
, instr
);
7349 case nir_intrinsic_image_deref_size
:
7350 visit_image_size(ctx
, instr
);
7352 case nir_intrinsic_load_ssbo
:
7353 visit_load_ssbo(ctx
, instr
);
7355 case nir_intrinsic_store_ssbo
:
7356 visit_store_ssbo(ctx
, instr
);
7358 case nir_intrinsic_load_global
:
7359 visit_load_global(ctx
, instr
);
7361 case nir_intrinsic_store_global
:
7362 visit_store_global(ctx
, instr
);
7364 case nir_intrinsic_global_atomic_add
:
7365 case nir_intrinsic_global_atomic_imin
:
7366 case nir_intrinsic_global_atomic_umin
:
7367 case nir_intrinsic_global_atomic_imax
:
7368 case nir_intrinsic_global_atomic_umax
:
7369 case nir_intrinsic_global_atomic_and
:
7370 case nir_intrinsic_global_atomic_or
:
7371 case nir_intrinsic_global_atomic_xor
:
7372 case nir_intrinsic_global_atomic_exchange
:
7373 case nir_intrinsic_global_atomic_comp_swap
:
7374 visit_global_atomic(ctx
, instr
);
7376 case nir_intrinsic_ssbo_atomic_add
:
7377 case nir_intrinsic_ssbo_atomic_imin
:
7378 case nir_intrinsic_ssbo_atomic_umin
:
7379 case nir_intrinsic_ssbo_atomic_imax
:
7380 case nir_intrinsic_ssbo_atomic_umax
:
7381 case nir_intrinsic_ssbo_atomic_and
:
7382 case nir_intrinsic_ssbo_atomic_or
:
7383 case nir_intrinsic_ssbo_atomic_xor
:
7384 case nir_intrinsic_ssbo_atomic_exchange
:
7385 case nir_intrinsic_ssbo_atomic_comp_swap
:
7386 visit_atomic_ssbo(ctx
, instr
);
7388 case nir_intrinsic_load_scratch
:
7389 visit_load_scratch(ctx
, instr
);
7391 case nir_intrinsic_store_scratch
:
7392 visit_store_scratch(ctx
, instr
);
7394 case nir_intrinsic_get_buffer_size
:
7395 visit_get_buffer_size(ctx
, instr
);
7397 case nir_intrinsic_scoped_barrier
:
7398 emit_scoped_barrier(ctx
, instr
);
7400 case nir_intrinsic_load_num_work_groups
: {
7401 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7402 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.num_work_groups
)));
7403 emit_split_vector(ctx
, dst
, 3);
7406 case nir_intrinsic_load_local_invocation_id
: {
7407 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7408 bld
.copy(Definition(dst
), Operand(get_arg(ctx
, ctx
->args
->ac
.local_invocation_ids
)));
7409 emit_split_vector(ctx
, dst
, 3);
7412 case nir_intrinsic_load_work_group_id
: {
7413 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7414 struct ac_arg
*args
= ctx
->args
->ac
.workgroup_ids
;
7415 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
),
7416 args
[0].used
? Operand(get_arg(ctx
, args
[0])) : Operand(0u),
7417 args
[1].used
? Operand(get_arg(ctx
, args
[1])) : Operand(0u),
7418 args
[2].used
? Operand(get_arg(ctx
, args
[2])) : Operand(0u));
7419 emit_split_vector(ctx
, dst
, 3);
7422 case nir_intrinsic_load_local_invocation_index
: {
7423 Temp id
= emit_mbcnt(ctx
, bld
.def(v1
));
7425 /* The tg_size bits [6:11] contain the subgroup id,
7426 * we need this multiplied by the wave size, and then OR the thread id to it.
7428 if (ctx
->program
->wave_size
== 64) {
7429 /* After the s_and the bits are already multiplied by 64 (left shifted by 6) so we can just feed that to v_or */
7430 Temp tg_num
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(0xfc0u
),
7431 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7432 bld
.vop2(aco_opcode::v_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, id
);
7434 /* Extract the bit field and multiply the result by 32 (left shift by 5), then do the OR */
7435 Temp tg_num
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
7436 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7437 bld
.vop3(aco_opcode::v_lshl_or_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), tg_num
, Operand(0x5u
), id
);
7441 case nir_intrinsic_load_subgroup_id
: {
7442 if (ctx
->stage
== compute_cs
) {
7443 bld
.sop2(aco_opcode::s_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
),
7444 get_arg(ctx
, ctx
->args
->ac
.tg_size
), Operand(0x6u
| (0x6u
<< 16)));
7446 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x0u
));
7450 case nir_intrinsic_load_subgroup_invocation
: {
7451 emit_mbcnt(ctx
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)));
7454 case nir_intrinsic_load_num_subgroups
: {
7455 if (ctx
->stage
== compute_cs
)
7456 bld
.sop2(aco_opcode::s_and_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), bld
.def(s1
, scc
), Operand(0x3fu
),
7457 get_arg(ctx
, ctx
->args
->ac
.tg_size
));
7459 bld
.sop1(aco_opcode::s_mov_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)), Operand(0x1u
));
7462 case nir_intrinsic_ballot
: {
7463 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7464 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7465 Definition tmp
= bld
.def(dst
.regClass());
7466 Definition lanemask_tmp
= dst
.size() == bld
.lm
.size() ? tmp
: bld
.def(src
.regClass());
7467 if (instr
->src
[0].ssa
->bit_size
== 1) {
7468 assert(src
.regClass() == bld
.lm
);
7469 bld
.sop2(Builder::s_and
, lanemask_tmp
, bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
);
7470 } else if (instr
->src
[0].ssa
->bit_size
== 32 && src
.regClass() == v1
) {
7471 bld
.vopc(aco_opcode::v_cmp_lg_u32
, lanemask_tmp
, Operand(0u), src
);
7472 } else if (instr
->src
[0].ssa
->bit_size
== 64 && src
.regClass() == v2
) {
7473 bld
.vopc(aco_opcode::v_cmp_lg_u64
, lanemask_tmp
, Operand(0u), src
);
7475 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7477 if (dst
.size() != bld
.lm
.size()) {
7478 /* Wave32 with ballot size set to 64 */
7479 bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
), lanemask_tmp
.getTemp(), Operand(0u));
7481 emit_wqm(ctx
, tmp
.getTemp(), dst
);
7484 case nir_intrinsic_shuffle
:
7485 case nir_intrinsic_read_invocation
: {
7486 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7487 if (!nir_src_is_divergent(instr
->src
[0])) {
7488 emit_uniform_subgroup(ctx
, instr
, src
);
7490 Temp tid
= get_ssa_temp(ctx
, instr
->src
[1].ssa
);
7491 if (instr
->intrinsic
== nir_intrinsic_read_invocation
|| !nir_src_is_divergent(instr
->src
[1]))
7492 tid
= bld
.as_uniform(tid
);
7493 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7494 if (src
.regClass() == v1b
|| src
.regClass() == v2b
) {
7495 Temp tmp
= bld
.tmp(v1
);
7496 tmp
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), tmp
);
7497 if (dst
.type() == RegType::vgpr
)
7498 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(src
.regClass() == v1b
? v3b
: v2b
), tmp
);
7500 bld
.pseudo(aco_opcode::p_as_uniform
, Definition(dst
), tmp
);
7501 } else if (src
.regClass() == v1
) {
7502 emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, src
), dst
);
7503 } else if (src
.regClass() == v2
) {
7504 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7505 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7506 lo
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, lo
));
7507 hi
= emit_wqm(ctx
, emit_bpermute(ctx
, bld
, tid
, hi
));
7508 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7509 emit_split_vector(ctx
, dst
, 2);
7510 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == s1
) {
7511 assert(src
.regClass() == bld
.lm
);
7512 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
, tid
);
7513 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7514 } else if (instr
->dest
.ssa
.bit_size
== 1 && tid
.regClass() == v1
) {
7515 assert(src
.regClass() == bld
.lm
);
7517 if (ctx
->program
->chip_class
<= GFX7
)
7518 tmp
= bld
.vop3(aco_opcode::v_lshr_b64
, bld
.def(v2
), src
, tid
);
7519 else if (ctx
->program
->wave_size
== 64)
7520 tmp
= bld
.vop3(aco_opcode::v_lshrrev_b64
, bld
.def(v2
), tid
, src
);
7522 tmp
= bld
.vop2_e64(aco_opcode::v_lshrrev_b32
, bld
.def(v1
), tid
, src
);
7523 tmp
= emit_extract_vector(ctx
, tmp
, 0, v1
);
7524 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(1u), tmp
);
7525 emit_wqm(ctx
, bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), tmp
), dst
);
7527 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7532 case nir_intrinsic_load_sample_id
: {
7533 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
7534 get_arg(ctx
, ctx
->args
->ac
.ancillary
), Operand(8u), Operand(4u));
7537 case nir_intrinsic_load_sample_mask_in
: {
7538 visit_load_sample_mask_in(ctx
, instr
);
7541 case nir_intrinsic_read_first_invocation
: {
7542 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7543 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7544 if (src
.regClass() == v1b
|| src
.regClass() == v2b
|| src
.regClass() == v1
) {
7546 bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), src
),
7548 } else if (src
.regClass() == v2
) {
7549 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7550 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7551 lo
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), lo
));
7552 hi
= emit_wqm(ctx
, bld
.vop1(aco_opcode::v_readfirstlane_b32
, bld
.def(s1
), hi
));
7553 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7554 emit_split_vector(ctx
, dst
, 2);
7555 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7556 assert(src
.regClass() == bld
.lm
);
7557 Temp tmp
= bld
.sopc(Builder::s_bitcmp1
, bld
.def(s1
, scc
), src
,
7558 bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)));
7559 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7560 } else if (src
.regClass() == s1
) {
7561 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), src
);
7562 } else if (src
.regClass() == s2
) {
7563 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), src
);
7565 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7569 case nir_intrinsic_vote_all
: {
7570 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7571 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7572 assert(src
.regClass() == bld
.lm
);
7573 assert(dst
.regClass() == bld
.lm
);
7575 Temp tmp
= bld
.sop2(Builder::s_andn2
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), Operand(exec
, bld
.lm
), src
).def(1).getTemp();
7576 Temp cond
= bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
));
7577 bld
.sop1(Builder::s_not
, Definition(dst
), bld
.def(s1
, scc
), cond
);
7580 case nir_intrinsic_vote_any
: {
7581 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7582 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7583 assert(src
.regClass() == bld
.lm
);
7584 assert(dst
.regClass() == bld
.lm
);
7586 Temp tmp
= bool_to_scalar_condition(ctx
, src
);
7587 bool_to_vector_condition(ctx
, emit_wqm(ctx
, tmp
), dst
);
7590 case nir_intrinsic_reduce
:
7591 case nir_intrinsic_inclusive_scan
:
7592 case nir_intrinsic_exclusive_scan
: {
7593 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7594 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7595 nir_op op
= (nir_op
) nir_intrinsic_reduction_op(instr
);
7596 unsigned cluster_size
= instr
->intrinsic
== nir_intrinsic_reduce
?
7597 nir_intrinsic_cluster_size(instr
) : 0;
7598 cluster_size
= util_next_power_of_two(MIN2(cluster_size
? cluster_size
: ctx
->program
->wave_size
, ctx
->program
->wave_size
));
7600 if (!nir_src_is_divergent(instr
->src
[0]) && (op
== nir_op_ior
|| op
== nir_op_iand
)) {
7601 emit_uniform_subgroup(ctx
, instr
, src
);
7602 } else if (instr
->dest
.ssa
.bit_size
== 1) {
7603 if (op
== nir_op_imul
|| op
== nir_op_umin
|| op
== nir_op_imin
)
7605 else if (op
== nir_op_iadd
)
7607 else if (op
== nir_op_umax
|| op
== nir_op_imax
)
7609 assert(op
== nir_op_iand
|| op
== nir_op_ior
|| op
== nir_op_ixor
);
7611 switch (instr
->intrinsic
) {
7612 case nir_intrinsic_reduce
:
7613 emit_wqm(ctx
, emit_boolean_reduce(ctx
, op
, cluster_size
, src
), dst
);
7615 case nir_intrinsic_exclusive_scan
:
7616 emit_wqm(ctx
, emit_boolean_exclusive_scan(ctx
, op
, src
), dst
);
7618 case nir_intrinsic_inclusive_scan
:
7619 emit_wqm(ctx
, emit_boolean_inclusive_scan(ctx
, op
, src
), dst
);
7624 } else if (cluster_size
== 1) {
7625 bld
.copy(Definition(dst
), src
);
7627 unsigned bit_size
= instr
->src
[0].ssa
->bit_size
;
7629 src
= emit_extract_vector(ctx
, src
, 0, RegClass::get(RegType::vgpr
, bit_size
/ 8));
7633 #define CASEI(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : (bit_size == 8) ? name##8 : name##64; break;
7634 #define CASEF(name) case nir_op_##name: reduce_op = (bit_size == 32) ? name##32 : (bit_size == 16) ? name##16 : name##64; break;
7649 unreachable("unknown reduction op");
7655 switch (instr
->intrinsic
) {
7656 case nir_intrinsic_reduce
: aco_op
= aco_opcode::p_reduce
; break;
7657 case nir_intrinsic_inclusive_scan
: aco_op
= aco_opcode::p_inclusive_scan
; break;
7658 case nir_intrinsic_exclusive_scan
: aco_op
= aco_opcode::p_exclusive_scan
; break;
7660 unreachable("unknown reduce intrinsic");
7663 aco_ptr
<Pseudo_reduction_instruction
> reduce
{create_instruction
<Pseudo_reduction_instruction
>(aco_op
, Format::PSEUDO_REDUCTION
, 3, 5)};
7664 reduce
->operands
[0] = Operand(src
);
7665 // filled in by aco_reduce_assign.cpp, used internally as part of the
7667 assert(dst
.size() == 1 || dst
.size() == 2);
7668 reduce
->operands
[1] = Operand(RegClass(RegType::vgpr
, dst
.size()).as_linear());
7669 reduce
->operands
[2] = Operand(v1
.as_linear());
7671 Temp tmp_dst
= bld
.tmp(dst
.regClass());
7672 reduce
->definitions
[0] = Definition(tmp_dst
);
7673 reduce
->definitions
[1] = bld
.def(ctx
->program
->lane_mask
); // used internally
7674 reduce
->definitions
[2] = Definition();
7675 reduce
->definitions
[3] = Definition(scc
, s1
);
7676 reduce
->definitions
[4] = Definition();
7677 reduce
->reduce_op
= reduce_op
;
7678 reduce
->cluster_size
= cluster_size
;
7679 ctx
->block
->instructions
.emplace_back(std::move(reduce
));
7681 emit_wqm(ctx
, tmp_dst
, dst
);
7685 case nir_intrinsic_quad_broadcast
: {
7686 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7687 if (!nir_dest_is_divergent(instr
->dest
)) {
7688 emit_uniform_subgroup(ctx
, instr
, src
);
7690 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7691 unsigned lane
= nir_src_as_const_value(instr
->src
[1])->u32
;
7692 uint32_t dpp_ctrl
= dpp_quad_perm(lane
, lane
, lane
, lane
);
7694 if (instr
->dest
.ssa
.bit_size
== 1) {
7695 assert(src
.regClass() == bld
.lm
);
7696 assert(dst
.regClass() == bld
.lm
);
7697 uint32_t half_mask
= 0x11111111u
<< lane
;
7698 Temp mask_tmp
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s2
), Operand(half_mask
), Operand(half_mask
));
7699 Temp tmp
= bld
.tmp(bld
.lm
);
7700 bld
.sop1(Builder::s_wqm
, Definition(tmp
),
7701 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), mask_tmp
,
7702 bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
))));
7703 emit_wqm(ctx
, tmp
, dst
);
7704 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7705 Temp tmp
= bld
.tmp(v1
);
7706 if (ctx
->program
->chip_class
>= GFX8
)
7707 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7709 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7710 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7711 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7712 Temp tmp
= bld
.tmp(v1
);
7713 if (ctx
->program
->chip_class
>= GFX8
)
7714 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7716 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), tmp
);
7717 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7718 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7719 if (ctx
->program
->chip_class
>= GFX8
)
7720 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), dst
);
7722 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, (1 << 15) | dpp_ctrl
), dst
);
7723 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7724 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7725 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7726 if (ctx
->program
->chip_class
>= GFX8
) {
7727 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7728 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7730 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, (1 << 15) | dpp_ctrl
));
7731 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, (1 << 15) | dpp_ctrl
));
7733 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7734 emit_split_vector(ctx
, dst
, 2);
7736 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7741 case nir_intrinsic_quad_swap_horizontal
:
7742 case nir_intrinsic_quad_swap_vertical
:
7743 case nir_intrinsic_quad_swap_diagonal
:
7744 case nir_intrinsic_quad_swizzle_amd
: {
7745 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7746 if (!nir_dest_is_divergent(instr
->dest
)) {
7747 emit_uniform_subgroup(ctx
, instr
, src
);
7750 uint16_t dpp_ctrl
= 0;
7751 switch (instr
->intrinsic
) {
7752 case nir_intrinsic_quad_swap_horizontal
:
7753 dpp_ctrl
= dpp_quad_perm(1, 0, 3, 2);
7755 case nir_intrinsic_quad_swap_vertical
:
7756 dpp_ctrl
= dpp_quad_perm(2, 3, 0, 1);
7758 case nir_intrinsic_quad_swap_diagonal
:
7759 dpp_ctrl
= dpp_quad_perm(3, 2, 1, 0);
7761 case nir_intrinsic_quad_swizzle_amd
:
7762 dpp_ctrl
= nir_intrinsic_swizzle_mask(instr
);
7767 if (ctx
->program
->chip_class
< GFX8
)
7768 dpp_ctrl
|= (1 << 15);
7770 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7771 if (instr
->dest
.ssa
.bit_size
== 1) {
7772 assert(src
.regClass() == bld
.lm
);
7773 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7774 if (ctx
->program
->chip_class
>= GFX8
)
7775 src
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7777 src
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7778 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7779 emit_wqm(ctx
, tmp
, dst
);
7780 } else if (instr
->dest
.ssa
.bit_size
== 8) {
7781 Temp tmp
= bld
.tmp(v1
);
7782 if (ctx
->program
->chip_class
>= GFX8
)
7783 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7785 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7786 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v3b
), tmp
);
7787 } else if (instr
->dest
.ssa
.bit_size
== 16) {
7788 Temp tmp
= bld
.tmp(v1
);
7789 if (ctx
->program
->chip_class
>= GFX8
)
7790 emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7792 emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
), tmp
);
7793 bld
.pseudo(aco_opcode::p_split_vector
, Definition(dst
), bld
.def(v2b
), tmp
);
7794 } else if (instr
->dest
.ssa
.bit_size
== 32) {
7796 if (ctx
->program
->chip_class
>= GFX8
)
7797 tmp
= bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7799 tmp
= bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), src
, dpp_ctrl
);
7800 emit_wqm(ctx
, tmp
, dst
);
7801 } else if (instr
->dest
.ssa
.bit_size
== 64) {
7802 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7803 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7804 if (ctx
->program
->chip_class
>= GFX8
) {
7805 lo
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7806 hi
= emit_wqm(ctx
, bld
.vop1_dpp(aco_opcode::v_mov_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7808 lo
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), lo
, dpp_ctrl
));
7809 hi
= emit_wqm(ctx
, bld
.ds(aco_opcode::ds_swizzle_b32
, bld
.def(v1
), hi
, dpp_ctrl
));
7811 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7812 emit_split_vector(ctx
, dst
, 2);
7814 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7818 case nir_intrinsic_masked_swizzle_amd
: {
7819 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7820 if (!nir_dest_is_divergent(instr
->dest
)) {
7821 emit_uniform_subgroup(ctx
, instr
, src
);
7824 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7825 uint32_t mask
= nir_intrinsic_swizzle_mask(instr
);
7826 if (instr
->dest
.ssa
.bit_size
== 1) {
7827 assert(src
.regClass() == bld
.lm
);
7828 src
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), Operand(0u), Operand((uint32_t)-1), src
);
7829 src
= emit_masked_swizzle(ctx
, bld
, src
, mask
);
7830 Temp tmp
= bld
.vopc(aco_opcode::v_cmp_lg_u32
, bld
.def(bld
.lm
), Operand(0u), src
);
7831 emit_wqm(ctx
, tmp
, dst
);
7832 } else if (dst
.regClass() == v1b
) {
7833 Temp tmp
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
));
7834 emit_extract_vector(ctx
, tmp
, 0, dst
);
7835 } else if (dst
.regClass() == v2b
) {
7836 Temp tmp
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
));
7837 emit_extract_vector(ctx
, tmp
, 0, dst
);
7838 } else if (dst
.regClass() == v1
) {
7839 emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, src
, mask
), dst
);
7840 } else if (dst
.regClass() == v2
) {
7841 Temp lo
= bld
.tmp(v1
), hi
= bld
.tmp(v1
);
7842 bld
.pseudo(aco_opcode::p_split_vector
, Definition(lo
), Definition(hi
), src
);
7843 lo
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, lo
, mask
));
7844 hi
= emit_wqm(ctx
, emit_masked_swizzle(ctx
, bld
, hi
, mask
));
7845 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7846 emit_split_vector(ctx
, dst
, 2);
7848 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7852 case nir_intrinsic_write_invocation_amd
: {
7853 Temp src
= as_vgpr(ctx
, get_ssa_temp(ctx
, instr
->src
[0].ssa
));
7854 Temp val
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[1].ssa
));
7855 Temp lane
= bld
.as_uniform(get_ssa_temp(ctx
, instr
->src
[2].ssa
));
7856 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7857 if (dst
.regClass() == v1
) {
7858 /* src2 is ignored for writelane. RA assigns the same reg for dst */
7859 emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val
, lane
, src
), dst
);
7860 } else if (dst
.regClass() == v2
) {
7861 Temp src_lo
= bld
.tmp(v1
), src_hi
= bld
.tmp(v1
);
7862 Temp val_lo
= bld
.tmp(s1
), val_hi
= bld
.tmp(s1
);
7863 bld
.pseudo(aco_opcode::p_split_vector
, Definition(src_lo
), Definition(src_hi
), src
);
7864 bld
.pseudo(aco_opcode::p_split_vector
, Definition(val_lo
), Definition(val_hi
), val
);
7865 Temp lo
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_lo
, lane
, src_hi
));
7866 Temp hi
= emit_wqm(ctx
, bld
.writelane(bld
.def(v1
), val_hi
, lane
, src_hi
));
7867 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), lo
, hi
);
7868 emit_split_vector(ctx
, dst
, 2);
7870 isel_err(&instr
->instr
, "Unimplemented NIR instr bit size");
7874 case nir_intrinsic_mbcnt_amd
: {
7875 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7876 RegClass rc
= RegClass(src
.type(), 1);
7877 Temp mask_lo
= bld
.tmp(rc
), mask_hi
= bld
.tmp(rc
);
7878 bld
.pseudo(aco_opcode::p_split_vector
, Definition(mask_lo
), Definition(mask_hi
), src
);
7879 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7880 Temp wqm_tmp
= emit_mbcnt(ctx
, bld
.def(v1
), Operand(mask_lo
), Operand(mask_hi
));
7881 emit_wqm(ctx
, wqm_tmp
, dst
);
7884 case nir_intrinsic_load_helper_invocation
: {
7885 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7886 bld
.pseudo(aco_opcode::p_load_helper
, Definition(dst
));
7887 ctx
->block
->kind
|= block_kind_needs_lowering
;
7888 ctx
->program
->needs_exact
= true;
7891 case nir_intrinsic_is_helper_invocation
: {
7892 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7893 bld
.pseudo(aco_opcode::p_is_helper
, Definition(dst
));
7894 ctx
->block
->kind
|= block_kind_needs_lowering
;
7895 ctx
->program
->needs_exact
= true;
7898 case nir_intrinsic_demote
:
7899 bld
.pseudo(aco_opcode::p_demote_to_helper
, Operand(-1u));
7901 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7902 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7903 ctx
->block
->kind
|= block_kind_uses_demote
;
7904 ctx
->program
->needs_exact
= true;
7906 case nir_intrinsic_demote_if
: {
7907 Temp src
= get_ssa_temp(ctx
, instr
->src
[0].ssa
);
7908 assert(src
.regClass() == bld
.lm
);
7909 Temp cond
= bld
.sop2(Builder::s_and
, bld
.def(bld
.lm
), bld
.def(s1
, scc
), src
, Operand(exec
, bld
.lm
));
7910 bld
.pseudo(aco_opcode::p_demote_to_helper
, cond
);
7912 if (ctx
->cf_info
.loop_nest_depth
|| ctx
->cf_info
.parent_if
.is_divergent
)
7913 ctx
->cf_info
.exec_potentially_empty_discard
= true;
7914 ctx
->block
->kind
|= block_kind_uses_demote
;
7915 ctx
->program
->needs_exact
= true;
7918 case nir_intrinsic_first_invocation
: {
7919 emit_wqm(ctx
, bld
.sop1(Builder::s_ff1_i32
, bld
.def(s1
), Operand(exec
, bld
.lm
)),
7920 get_ssa_temp(ctx
, &instr
->dest
.ssa
));
7923 case nir_intrinsic_shader_clock
: {
7924 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7925 if (nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_SUBGROUP
&& ctx
->options
->chip_class
>= GFX10_3
) {
7926 /* "((size - 1) << 11) | register" (SHADER_CYCLES is encoded as register 29) */
7927 Temp clock
= bld
.sopk(aco_opcode::s_getreg_b32
, bld
.def(s1
), ((20 - 1) << 11) | 29);
7928 bld
.pseudo(aco_opcode::p_create_vector
, Definition(dst
), clock
, Operand(0u));
7931 nir_intrinsic_memory_scope(instr
) == NIR_SCOPE_DEVICE
?
7932 aco_opcode::s_memrealtime
: aco_opcode::s_memtime
;
7933 bld
.smem(opcode
, Definition(dst
), memory_sync_info(0, semantic_volatile
));
7935 emit_split_vector(ctx
, dst
, 2);
7938 case nir_intrinsic_load_vertex_id_zero_base
: {
7939 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7940 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.vertex_id
));
7943 case nir_intrinsic_load_first_vertex
: {
7944 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7945 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.base_vertex
));
7948 case nir_intrinsic_load_base_instance
: {
7949 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7950 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.start_instance
));
7953 case nir_intrinsic_load_instance_id
: {
7954 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7955 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.instance_id
));
7958 case nir_intrinsic_load_draw_id
: {
7959 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7960 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.draw_id
));
7963 case nir_intrinsic_load_invocation_id
: {
7964 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7966 if (ctx
->shader
->info
.stage
== MESA_SHADER_GEOMETRY
) {
7967 if (ctx
->options
->chip_class
>= GFX10
)
7968 bld
.vop2_e64(aco_opcode::v_and_b32
, Definition(dst
), Operand(127u), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7970 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
));
7971 } else if (ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
7972 bld
.vop3(aco_opcode::v_bfe_u32
, Definition(dst
),
7973 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
), Operand(8u), Operand(5u));
7975 unreachable("Unsupported stage for load_invocation_id");
7980 case nir_intrinsic_load_primitive_id
: {
7981 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
7983 switch (ctx
->shader
->info
.stage
) {
7984 case MESA_SHADER_GEOMETRY
:
7985 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
));
7987 case MESA_SHADER_TESS_CTRL
:
7988 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
));
7990 case MESA_SHADER_TESS_EVAL
:
7991 bld
.copy(Definition(dst
), get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
));
7994 unreachable("Unimplemented shader stage for nir_intrinsic_load_primitive_id");
7999 case nir_intrinsic_load_patch_vertices_in
: {
8000 assert(ctx
->shader
->info
.stage
== MESA_SHADER_TESS_CTRL
||
8001 ctx
->shader
->info
.stage
== MESA_SHADER_TESS_EVAL
);
8003 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8004 bld
.copy(Definition(dst
), Operand(ctx
->args
->options
->key
.tcs
.input_vertices
));
8007 case nir_intrinsic_emit_vertex_with_counter
: {
8008 visit_emit_vertex_with_counter(ctx
, instr
);
8011 case nir_intrinsic_end_primitive_with_counter
: {
8012 unsigned stream
= nir_intrinsic_stream_id(instr
);
8013 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
->gs_wave_id
), -1, sendmsg_gs(true, false, stream
));
8016 case nir_intrinsic_set_vertex_count
: {
8017 /* unused, the HW keeps track of this for us */
8021 isel_err(&instr
->instr
, "Unimplemented intrinsic instr");
8029 void tex_fetch_ptrs(isel_context
*ctx
, nir_tex_instr
*instr
,
8030 Temp
*res_ptr
, Temp
*samp_ptr
, Temp
*fmask_ptr
,
8031 enum glsl_base_type
*stype
)
8033 nir_deref_instr
*texture_deref_instr
= NULL
;
8034 nir_deref_instr
*sampler_deref_instr
= NULL
;
8037 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8038 switch (instr
->src
[i
].src_type
) {
8039 case nir_tex_src_texture_deref
:
8040 texture_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8042 case nir_tex_src_sampler_deref
:
8043 sampler_deref_instr
= nir_src_as_deref(instr
->src
[i
].src
);
8045 case nir_tex_src_plane
:
8046 plane
= nir_src_as_int(instr
->src
[i
].src
);
8053 *stype
= glsl_get_sampler_result_type(texture_deref_instr
->type
);
8055 if (!sampler_deref_instr
)
8056 sampler_deref_instr
= texture_deref_instr
;
8059 assert(instr
->op
!= nir_texop_txf_ms
&&
8060 instr
->op
!= nir_texop_samples_identical
);
8061 assert(instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
);
8062 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, (aco_descriptor_type
)(ACO_DESC_PLANE_0
+ plane
), instr
, false, false);
8063 } else if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8064 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_BUFFER
, instr
, false, false);
8065 } else if (instr
->op
== nir_texop_fragment_mask_fetch
) {
8066 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8068 *res_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_IMAGE
, instr
, false, false);
8071 *samp_ptr
= get_sampler_desc(ctx
, sampler_deref_instr
, ACO_DESC_SAMPLER
, instr
, false, false);
8073 if (instr
->sampler_dim
< GLSL_SAMPLER_DIM_RECT
&& ctx
->options
->chip_class
< GFX8
) {
8074 /* fix sampler aniso on SI/CI: samp[0] = samp[0] & img[7] */
8075 Builder
bld(ctx
->program
, ctx
->block
);
8077 /* to avoid unnecessary moves, we split and recombine sampler and image */
8078 Temp img
[8] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
),
8079 bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8080 Temp samp
[4] = {bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
), bld
.tmp(s1
)};
8081 bld
.pseudo(aco_opcode::p_split_vector
, Definition(img
[0]), Definition(img
[1]),
8082 Definition(img
[2]), Definition(img
[3]), Definition(img
[4]),
8083 Definition(img
[5]), Definition(img
[6]), Definition(img
[7]), *res_ptr
);
8084 bld
.pseudo(aco_opcode::p_split_vector
, Definition(samp
[0]), Definition(samp
[1]),
8085 Definition(samp
[2]), Definition(samp
[3]), *samp_ptr
);
8087 samp
[0] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), samp
[0], img
[7]);
8088 *res_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s8
),
8089 img
[0], img
[1], img
[2], img
[3],
8090 img
[4], img
[5], img
[6], img
[7]);
8091 *samp_ptr
= bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(s4
),
8092 samp
[0], samp
[1], samp
[2], samp
[3]);
8095 if (fmask_ptr
&& (instr
->op
== nir_texop_txf_ms
||
8096 instr
->op
== nir_texop_samples_identical
))
8097 *fmask_ptr
= get_sampler_desc(ctx
, texture_deref_instr
, ACO_DESC_FMASK
, instr
, false, false);
8100 void build_cube_select(isel_context
*ctx
, Temp ma
, Temp id
, Temp deriv
,
8101 Temp
*out_ma
, Temp
*out_sc
, Temp
*out_tc
)
8103 Builder
bld(ctx
->program
, ctx
->block
);
8105 Temp deriv_x
= emit_extract_vector(ctx
, deriv
, 0, v1
);
8106 Temp deriv_y
= emit_extract_vector(ctx
, deriv
, 1, v1
);
8107 Temp deriv_z
= emit_extract_vector(ctx
, deriv
, 2, v1
);
8109 Operand
neg_one(0xbf800000u
);
8110 Operand
one(0x3f800000u
);
8111 Operand
two(0x40000000u
);
8112 Operand
four(0x40800000u
);
8114 Temp is_ma_positive
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), ma
);
8115 Temp sgn_ma
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, one
, is_ma_positive
);
8116 Temp neg_sgn_ma
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
), Operand(0u), sgn_ma
);
8118 Temp is_ma_z
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.hint_vcc(bld
.def(bld
.lm
)), four
, id
);
8119 Temp is_ma_y
= bld
.vopc(aco_opcode::v_cmp_le_f32
, bld
.def(bld
.lm
), two
, id
);
8120 is_ma_y
= bld
.sop2(Builder::s_andn2
, bld
.hint_vcc(bld
.def(bld
.lm
)), is_ma_y
, is_ma_z
);
8121 Temp is_not_ma_x
= bld
.sop2(aco_opcode::s_or_b64
, bld
.hint_vcc(bld
.def(bld
.lm
)), bld
.def(s1
, scc
), is_ma_z
, is_ma_y
);
8124 Temp tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_z
, deriv_x
, is_not_ma_x
);
8125 Temp sgn
= bld
.vop2_e64(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8126 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_sgn_ma
, sgn_ma
, is_ma_z
),
8128 *out_sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8131 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_y
, deriv_z
, is_ma_y
);
8132 sgn
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), neg_one
, sgn_ma
, is_ma_y
);
8133 *out_tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tmp
, sgn
);
8136 tmp
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8137 bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), deriv_x
, deriv_y
, is_ma_y
),
8139 tmp
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x7fffffffu
), tmp
);
8140 *out_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), two
, tmp
);
8143 void prepare_cube_coords(isel_context
*ctx
, std::vector
<Temp
>& coords
, Temp
* ddx
, Temp
* ddy
, bool is_deriv
, bool is_array
)
8145 Builder
bld(ctx
->program
, ctx
->block
);
8146 Temp ma
, tc
, sc
, id
;
8147 aco_opcode madak
= ctx
->program
->chip_class
>= GFX10_3
? aco_opcode::v_fmaak_f32
: aco_opcode::v_madak_f32
;
8148 aco_opcode madmk
= ctx
->program
->chip_class
>= GFX10_3
? aco_opcode::v_fmamk_f32
: aco_opcode::v_madmk_f32
;
8151 coords
[3] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[3]);
8153 // see comment in ac_prepare_cube_coords()
8154 if (ctx
->options
->chip_class
<= GFX8
)
8155 coords
[3] = bld
.vop2(aco_opcode::v_max_f32
, bld
.def(v1
), Operand(0u), coords
[3]);
8158 ma
= bld
.vop3(aco_opcode::v_cubema_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8160 aco_ptr
<VOP3A_instruction
> vop3a
{create_instruction
<VOP3A_instruction
>(aco_opcode::v_rcp_f32
, asVOP3(Format::VOP1
), 1, 1)};
8161 vop3a
->operands
[0] = Operand(ma
);
8162 vop3a
->abs
[0] = true;
8163 Temp invma
= bld
.tmp(v1
);
8164 vop3a
->definitions
[0] = Definition(invma
);
8165 ctx
->block
->instructions
.emplace_back(std::move(vop3a
));
8167 sc
= bld
.vop3(aco_opcode::v_cubesc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8169 sc
= bld
.vop2(madak
, bld
.def(v1
), sc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8171 tc
= bld
.vop3(aco_opcode::v_cubetc_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8173 tc
= bld
.vop2(madak
, bld
.def(v1
), tc
, invma
, Operand(0x3fc00000u
/*1.5*/));
8175 id
= bld
.vop3(aco_opcode::v_cubeid_f32
, bld
.def(v1
), coords
[0], coords
[1], coords
[2]);
8178 sc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), sc
, invma
);
8179 tc
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), tc
, invma
);
8181 for (unsigned i
= 0; i
< 2; i
++) {
8182 // see comment in ac_prepare_cube_coords()
8184 Temp deriv_sc
, deriv_tc
;
8185 build_cube_select(ctx
, ma
, id
, i
? *ddy
: *ddx
,
8186 &deriv_ma
, &deriv_sc
, &deriv_tc
);
8188 deriv_ma
= bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, invma
);
8190 Temp x
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8191 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_sc
, invma
),
8192 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, sc
));
8193 Temp y
= bld
.vop2(aco_opcode::v_sub_f32
, bld
.def(v1
),
8194 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_tc
, invma
),
8195 bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), deriv_ma
, tc
));
8196 *(i
? ddy
: ddx
) = bld
.pseudo(aco_opcode::p_create_vector
, bld
.def(v2
), x
, y
);
8199 sc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), sc
);
8200 tc
= bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), Operand(0x3fc00000u
/*1.5*/), tc
);
8204 id
= bld
.vop2(madmk
, bld
.def(v1
), coords
[3], id
, Operand(0x41000000u
/*8.0*/));
8211 void get_const_vec(nir_ssa_def
*vec
, nir_const_value
*cv
[4])
8213 if (vec
->parent_instr
->type
!= nir_instr_type_alu
)
8215 nir_alu_instr
*vec_instr
= nir_instr_as_alu(vec
->parent_instr
);
8216 if (vec_instr
->op
!= nir_op_vec(vec
->num_components
))
8219 for (unsigned i
= 0; i
< vec
->num_components
; i
++) {
8220 cv
[i
] = vec_instr
->src
[i
].swizzle
[0] == 0 ?
8221 nir_src_as_const_value(vec_instr
->src
[i
].src
) : NULL
;
8225 void visit_tex(isel_context
*ctx
, nir_tex_instr
*instr
)
8227 Builder
bld(ctx
->program
, ctx
->block
);
8228 bool has_bias
= false, has_lod
= false, level_zero
= false, has_compare
= false,
8229 has_offset
= false, has_ddx
= false, has_ddy
= false, has_derivs
= false, has_sample_index
= false,
8230 has_clamped_lod
= false;
8231 Temp resource
, sampler
, fmask_ptr
, bias
= Temp(), compare
= Temp(), sample_index
= Temp(),
8232 lod
= Temp(), offset
= Temp(), ddx
= Temp(), ddy
= Temp(),
8233 clamped_lod
= Temp();
8234 std::vector
<Temp
> coords
;
8235 std::vector
<Temp
> derivs
;
8236 nir_const_value
*sample_index_cv
= NULL
;
8237 nir_const_value
*const_offset
[4] = {NULL
, NULL
, NULL
, NULL
};
8238 enum glsl_base_type stype
;
8239 tex_fetch_ptrs(ctx
, instr
, &resource
, &sampler
, &fmask_ptr
, &stype
);
8241 bool tg4_integer_workarounds
= ctx
->options
->chip_class
<= GFX8
&& instr
->op
== nir_texop_tg4
&&
8242 (stype
== GLSL_TYPE_UINT
|| stype
== GLSL_TYPE_INT
);
8243 bool tg4_integer_cube_workaround
= tg4_integer_workarounds
&&
8244 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
;
8246 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
8247 switch (instr
->src
[i
].src_type
) {
8248 case nir_tex_src_coord
: {
8249 Temp coord
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8250 for (unsigned i
= 0; i
< coord
.size(); i
++)
8251 coords
.emplace_back(emit_extract_vector(ctx
, coord
, i
, v1
));
8254 case nir_tex_src_bias
:
8255 bias
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8258 case nir_tex_src_lod
: {
8259 nir_const_value
*val
= nir_src_as_const_value(instr
->src
[i
].src
);
8261 if (val
&& val
->f32
<= 0.0) {
8264 lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8269 case nir_tex_src_min_lod
:
8270 clamped_lod
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8271 has_clamped_lod
= true;
8273 case nir_tex_src_comparator
:
8274 if (instr
->is_shadow
) {
8275 compare
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8279 case nir_tex_src_offset
:
8280 offset
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8281 get_const_vec(instr
->src
[i
].src
.ssa
, const_offset
);
8284 case nir_tex_src_ddx
:
8285 ddx
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8288 case nir_tex_src_ddy
:
8289 ddy
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8292 case nir_tex_src_ms_index
:
8293 sample_index
= get_ssa_temp(ctx
, instr
->src
[i
].src
.ssa
);
8294 sample_index_cv
= nir_src_as_const_value(instr
->src
[i
].src
);
8295 has_sample_index
= true;
8297 case nir_tex_src_texture_offset
:
8298 case nir_tex_src_sampler_offset
:
8304 if (instr
->op
== nir_texop_txs
&& instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
8305 return get_buffer_size(ctx
, resource
, get_ssa_temp(ctx
, &instr
->dest
.ssa
), true);
8307 if (instr
->op
== nir_texop_texture_samples
) {
8308 Temp dword3
= emit_extract_vector(ctx
, resource
, 3, s1
);
8310 Temp samples_log2
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(16u | 4u<<16));
8311 Temp samples
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(1u), samples_log2
);
8312 Temp type
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), dword3
, Operand(28u | 4u<<16 /* offset=28, width=4 */));
8314 Operand default_sample
= Operand(1u);
8315 if (ctx
->options
->robust_buffer_access
) {
8316 /* Extract the second dword of the descriptor, if it's
8317 * all zero, then it's a null descriptor.
8319 Temp dword1
= emit_extract_vector(ctx
, resource
, 1, s1
);
8320 Temp is_non_null_descriptor
= bld
.sopc(aco_opcode::s_cmp_gt_u32
, bld
.def(s1
, scc
), dword1
, Operand(0u));
8321 default_sample
= Operand(is_non_null_descriptor
);
8324 Temp is_msaa
= bld
.sopc(aco_opcode::s_cmp_ge_u32
, bld
.def(s1
, scc
), type
, Operand(14u));
8325 bld
.sop2(aco_opcode::s_cselect_b32
, Definition(get_ssa_temp(ctx
, &instr
->dest
.ssa
)),
8326 samples
, default_sample
, bld
.scc(is_msaa
));
8330 if (has_offset
&& instr
->op
!= nir_texop_txf
&& instr
->op
!= nir_texop_txf_ms
) {
8331 aco_ptr
<Instruction
> tmp_instr
;
8332 Temp acc
, pack
= Temp();
8334 uint32_t pack_const
= 0;
8335 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8336 if (!const_offset
[i
])
8338 pack_const
|= (const_offset
[i
]->u32
& 0x3Fu
) << (8u * i
);
8341 if (offset
.type() == RegType::sgpr
) {
8342 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8343 if (const_offset
[i
])
8346 acc
= emit_extract_vector(ctx
, offset
, i
, s1
);
8347 acc
= bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(0x3Fu
));
8350 acc
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), acc
, Operand(8u * i
));
8353 if (pack
== Temp()) {
8356 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), pack
, acc
);
8360 if (pack_const
&& pack
!= Temp())
8361 pack
= bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), Operand(pack_const
), pack
);
8363 for (unsigned i
= 0; i
< offset
.size(); i
++) {
8364 if (const_offset
[i
])
8367 acc
= emit_extract_vector(ctx
, offset
, i
, v1
);
8368 acc
= bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0x3Fu
), acc
);
8371 acc
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(8u * i
), acc
);
8374 if (pack
== Temp()) {
8377 pack
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), pack
, acc
);
8381 if (pack_const
&& pack
!= Temp())
8382 pack
= bld
.sop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(pack_const
), pack
);
8384 if (pack_const
&& pack
== Temp())
8385 offset
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(pack_const
));
8386 else if (pack
== Temp())
8392 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&& instr
->coord_components
)
8393 prepare_cube_coords(ctx
, coords
, &ddx
, &ddy
, instr
->op
== nir_texop_txd
, instr
->is_array
&& instr
->op
!= nir_texop_lod
);
8395 /* pack derivatives */
8396 if (has_ddx
|| has_ddy
) {
8397 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&& ctx
->options
->chip_class
== GFX9
) {
8398 assert(has_ddx
&& has_ddy
&& ddx
.size() == 1 && ddy
.size() == 1);
8399 Temp zero
= bld
.copy(bld
.def(v1
), Operand(0u));
8400 derivs
= {ddx
, zero
, ddy
, zero
};
8402 for (unsigned i
= 0; has_ddx
&& i
< ddx
.size(); i
++)
8403 derivs
.emplace_back(emit_extract_vector(ctx
, ddx
, i
, v1
));
8404 for (unsigned i
= 0; has_ddy
&& i
< ddy
.size(); i
++)
8405 derivs
.emplace_back(emit_extract_vector(ctx
, ddy
, i
, v1
));
8410 if (instr
->coord_components
> 1 &&
8411 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8413 instr
->op
!= nir_texop_txf
)
8414 coords
[1] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[1]);
8416 if (instr
->coord_components
> 2 &&
8417 (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
||
8418 instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8419 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS
||
8420 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8422 instr
->op
!= nir_texop_txf
&&
8423 instr
->op
!= nir_texop_txf_ms
&&
8424 instr
->op
!= nir_texop_fragment_fetch
&&
8425 instr
->op
!= nir_texop_fragment_mask_fetch
)
8426 coords
[2] = bld
.vop1(aco_opcode::v_rndne_f32
, bld
.def(v1
), coords
[2]);
8428 if (ctx
->options
->chip_class
== GFX9
&&
8429 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8430 instr
->op
!= nir_texop_lod
&& instr
->coord_components
) {
8431 assert(coords
.size() > 0 && coords
.size() < 3);
8433 coords
.insert(std::next(coords
.begin()), bld
.copy(bld
.def(v1
), instr
->op
== nir_texop_txf
?
8434 Operand((uint32_t) 0) :
8435 Operand((uint32_t) 0x3f000000)));
8438 bool da
= should_declare_array(ctx
, instr
->sampler_dim
, instr
->is_array
);
8440 if (instr
->op
== nir_texop_samples_identical
)
8441 resource
= fmask_ptr
;
8443 else if ((instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
||
8444 instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
) &&
8445 instr
->op
!= nir_texop_txs
&&
8446 instr
->op
!= nir_texop_fragment_fetch
&&
8447 instr
->op
!= nir_texop_fragment_mask_fetch
) {
8448 assert(has_sample_index
);
8449 Operand
op(sample_index
);
8450 if (sample_index_cv
)
8451 op
= Operand(sample_index_cv
->u32
);
8452 sample_index
= adjust_sample_index_using_fmask(ctx
, da
, coords
, op
, fmask_ptr
);
8455 if (has_offset
&& (instr
->op
== nir_texop_txf
|| instr
->op
== nir_texop_txf_ms
)) {
8456 for (unsigned i
= 0; i
< std::min(offset
.size(), instr
->coord_components
); i
++) {
8457 Temp off
= emit_extract_vector(ctx
, offset
, i
, v1
);
8458 coords
[i
] = bld
.vadd32(bld
.def(v1
), coords
[i
], off
);
8463 /* Build tex instruction */
8464 unsigned dmask
= nir_ssa_def_components_read(&instr
->dest
.ssa
);
8465 unsigned dim
= ctx
->options
->chip_class
>= GFX10
&& instr
->sampler_dim
!= GLSL_SAMPLER_DIM_BUF
8466 ? ac_get_sampler_dim(ctx
->options
->chip_class
, instr
->sampler_dim
, instr
->is_array
)
8468 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8471 /* gather4 selects the component by dmask and always returns vec4 */
8472 if (instr
->op
== nir_texop_tg4
) {
8473 assert(instr
->dest
.ssa
.num_components
== 4);
8474 if (instr
->is_shadow
)
8477 dmask
= 1 << instr
->component
;
8478 if (tg4_integer_cube_workaround
|| dst
.type() == RegType::sgpr
)
8479 tmp_dst
= bld
.tmp(v4
);
8480 } else if (instr
->op
== nir_texop_samples_identical
) {
8481 tmp_dst
= bld
.tmp(v1
);
8482 } else if (util_bitcount(dmask
) != instr
->dest
.ssa
.num_components
|| dst
.type() == RegType::sgpr
) {
8483 tmp_dst
= bld
.tmp(RegClass(RegType::vgpr
, util_bitcount(dmask
)));
8486 aco_ptr
<MIMG_instruction
> tex
;
8487 if (instr
->op
== nir_texop_txs
|| instr
->op
== nir_texop_query_levels
) {
8489 lod
= bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8491 bool div_by_6
= instr
->op
== nir_texop_txs
&&
8492 instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
8495 if (tmp_dst
.id() == dst
.id() && div_by_6
)
8496 tmp_dst
= bld
.tmp(tmp_dst
.regClass());
8498 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8499 tex
->operands
[0] = Operand(resource
);
8500 tex
->operands
[1] = Operand(s4
); /* no sampler */
8501 tex
->operands
[2] = Operand(as_vgpr(ctx
,lod
));
8502 if (ctx
->options
->chip_class
== GFX9
&&
8503 instr
->op
== nir_texop_txs
&&
8504 instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
&&
8506 tex
->dmask
= (dmask
& 0x1) | ((dmask
& 0x2) << 1);
8507 } else if (instr
->op
== nir_texop_query_levels
) {
8508 tex
->dmask
= 1 << 3;
8513 tex
->definitions
[0] = Definition(tmp_dst
);
8515 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8518 /* divide 3rd value by 6 by multiplying with magic number */
8519 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8520 Temp c
= bld
.copy(bld
.def(s1
), Operand((uint32_t) 0x2AAAAAAB));
8521 Temp by_6
= bld
.vop3(aco_opcode::v_mul_hi_i32
, bld
.def(v1
), emit_extract_vector(ctx
, tmp_dst
, 2, v1
), c
);
8522 assert(instr
->dest
.ssa
.num_components
== 3);
8523 Temp tmp
= dst
.type() == RegType::vgpr
? dst
: bld
.tmp(v3
);
8524 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8525 emit_extract_vector(ctx
, tmp_dst
, 0, v1
),
8526 emit_extract_vector(ctx
, tmp_dst
, 1, v1
),
8531 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8535 Temp tg4_compare_cube_wa64
= Temp();
8537 if (tg4_integer_workarounds
) {
8538 tex
.reset(create_instruction
<MIMG_instruction
>(aco_opcode::image_get_resinfo
, Format::MIMG
, 3, 1));
8539 tex
->operands
[0] = Operand(resource
);
8540 tex
->operands
[1] = Operand(s4
); /* no sampler */
8541 tex
->operands
[2] = bld
.vop1(aco_opcode::v_mov_b32
, bld
.def(v1
), Operand(0u));
8545 Temp size
= bld
.tmp(v2
);
8546 tex
->definitions
[0] = Definition(size
);
8547 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8548 emit_split_vector(ctx
, size
, size
.size());
8551 for (unsigned i
= 0; i
< 2; i
++) {
8552 half_texel
[i
] = emit_extract_vector(ctx
, size
, i
, v1
);
8553 half_texel
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_i32
, bld
.def(v1
), half_texel
[i
]);
8554 half_texel
[i
] = bld
.vop1(aco_opcode::v_rcp_iflag_f32
, bld
.def(v1
), half_texel
[i
]);
8555 half_texel
[i
] = bld
.vop2(aco_opcode::v_mul_f32
, bld
.def(v1
), Operand(0xbf000000/*-0.5*/), half_texel
[i
]);
8558 Temp new_coords
[2] = {
8559 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[0], half_texel
[0]),
8560 bld
.vop2(aco_opcode::v_add_f32
, bld
.def(v1
), coords
[1], half_texel
[1])
8563 if (tg4_integer_cube_workaround
) {
8564 // see comment in ac_nir_to_llvm.c's lower_gather4_integer()
8565 Temp desc
[resource
.size()];
8566 aco_ptr
<Instruction
> split
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_split_vector
,
8567 Format::PSEUDO
, 1, resource
.size())};
8568 split
->operands
[0] = Operand(resource
);
8569 for (unsigned i
= 0; i
< resource
.size(); i
++) {
8570 desc
[i
] = bld
.tmp(s1
);
8571 split
->definitions
[i
] = Definition(desc
[i
]);
8573 ctx
->block
->instructions
.emplace_back(std::move(split
));
8575 Temp dfmt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], Operand(20u | (6u << 16)));
8576 Temp compare_cube_wa
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), dfmt
,
8577 Operand((uint32_t)V_008F14_IMG_DATA_FORMAT_8_8_8_8
));
8580 if (stype
== GLSL_TYPE_UINT
) {
8581 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8582 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_USCALED
),
8583 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_UINT
),
8584 bld
.scc(compare_cube_wa
));
8586 nfmt
= bld
.sop2(aco_opcode::s_cselect_b32
, bld
.def(s1
),
8587 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SSCALED
),
8588 Operand((uint32_t)V_008F14_IMG_NUM_FORMAT_SINT
),
8589 bld
.scc(compare_cube_wa
));
8591 tg4_compare_cube_wa64
= bld
.tmp(bld
.lm
);
8592 bool_to_vector_condition(ctx
, compare_cube_wa
, tg4_compare_cube_wa64
);
8594 nfmt
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), nfmt
, Operand(26u));
8596 desc
[1] = bld
.sop2(aco_opcode::s_and_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1],
8597 Operand((uint32_t)C_008F14_NUM_FORMAT
));
8598 desc
[1] = bld
.sop2(aco_opcode::s_or_b32
, bld
.def(s1
), bld
.def(s1
, scc
), desc
[1], nfmt
);
8600 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
,
8601 Format::PSEUDO
, resource
.size(), 1)};
8602 for (unsigned i
= 0; i
< resource
.size(); i
++)
8603 vec
->operands
[i
] = Operand(desc
[i
]);
8604 resource
= bld
.tmp(resource
.regClass());
8605 vec
->definitions
[0] = Definition(resource
);
8606 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8608 new_coords
[0] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8609 new_coords
[0], coords
[0], tg4_compare_cube_wa64
);
8610 new_coords
[1] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
8611 new_coords
[1], coords
[1], tg4_compare_cube_wa64
);
8613 coords
[0] = new_coords
[0];
8614 coords
[1] = new_coords
[1];
8617 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
) {
8618 //FIXME: if (ctx->abi->gfx9_stride_size_workaround) return ac_build_buffer_load_format_gfx9_safe()
8620 assert(coords
.size() == 1);
8621 unsigned last_bit
= util_last_bit(nir_ssa_def_components_read(&instr
->dest
.ssa
));
8625 op
= aco_opcode::buffer_load_format_x
; break;
8627 op
= aco_opcode::buffer_load_format_xy
; break;
8629 op
= aco_opcode::buffer_load_format_xyz
; break;
8631 op
= aco_opcode::buffer_load_format_xyzw
; break;
8633 unreachable("Tex instruction loads more than 4 components.");
8636 /* if the instruction return value matches exactly the nir dest ssa, we can use it directly */
8637 if (last_bit
== instr
->dest
.ssa
.num_components
&& dst
.type() == RegType::vgpr
)
8640 tmp_dst
= bld
.tmp(RegType::vgpr
, last_bit
);
8642 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(op
, Format::MUBUF
, 3, 1)};
8643 mubuf
->operands
[0] = Operand(resource
);
8644 mubuf
->operands
[1] = Operand(coords
[0]);
8645 mubuf
->operands
[2] = Operand((uint32_t) 0);
8646 mubuf
->definitions
[0] = Definition(tmp_dst
);
8647 mubuf
->idxen
= true;
8648 ctx
->block
->instructions
.emplace_back(std::move(mubuf
));
8650 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, (1 << last_bit
) - 1);
8654 /* gather MIMG address components */
8655 std::vector
<Temp
> args
;
8657 args
.emplace_back(offset
);
8659 args
.emplace_back(bias
);
8661 args
.emplace_back(compare
);
8663 args
.insert(args
.end(), derivs
.begin(), derivs
.end());
8665 args
.insert(args
.end(), coords
.begin(), coords
.end());
8666 if (has_sample_index
)
8667 args
.emplace_back(sample_index
);
8669 args
.emplace_back(lod
);
8670 if (has_clamped_lod
)
8671 args
.emplace_back(clamped_lod
);
8673 Temp arg
= bld
.tmp(RegClass(RegType::vgpr
, args
.size()));
8674 aco_ptr
<Instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, args
.size(), 1)};
8675 vec
->definitions
[0] = Definition(arg
);
8676 for (unsigned i
= 0; i
< args
.size(); i
++)
8677 vec
->operands
[i
] = Operand(args
[i
]);
8678 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8681 if (instr
->op
== nir_texop_txf
||
8682 instr
->op
== nir_texop_txf_ms
||
8683 instr
->op
== nir_texop_samples_identical
||
8684 instr
->op
== nir_texop_fragment_fetch
||
8685 instr
->op
== nir_texop_fragment_mask_fetch
) {
8686 aco_opcode op
= level_zero
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_MS
|| instr
->sampler_dim
== GLSL_SAMPLER_DIM_SUBPASS_MS
? aco_opcode::image_load
: aco_opcode::image_load_mip
;
8687 tex
.reset(create_instruction
<MIMG_instruction
>(op
, Format::MIMG
, 3, 1));
8688 tex
->operands
[0] = Operand(resource
);
8689 tex
->operands
[1] = Operand(s4
); /* no sampler */
8690 tex
->operands
[2] = Operand(arg
);
8695 tex
->definitions
[0] = Definition(tmp_dst
);
8696 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8698 if (instr
->op
== nir_texop_samples_identical
) {
8699 assert(dmask
== 1 && dst
.regClass() == v1
);
8700 assert(dst
.id() != tmp_dst
.id());
8702 Temp tmp
= bld
.tmp(bld
.lm
);
8703 bld
.vopc(aco_opcode::v_cmp_eq_u32
, Definition(tmp
), Operand(0u), tmp_dst
).def(0).setHint(vcc
);
8704 bld
.vop2_e64(aco_opcode::v_cndmask_b32
, Definition(dst
), Operand(0u), Operand((uint32_t)-1), tmp
);
8707 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, dmask
);
8712 // TODO: would be better to do this by adding offsets, but needs the opcodes ordered.
8713 aco_opcode opcode
= aco_opcode::image_sample
;
8714 if (has_offset
) { /* image_sample_*_o */
8715 if (has_clamped_lod
) {
8717 opcode
= aco_opcode::image_sample_c_cl_o
;
8719 opcode
= aco_opcode::image_sample_c_d_cl_o
;
8721 opcode
= aco_opcode::image_sample_c_b_cl_o
;
8723 opcode
= aco_opcode::image_sample_cl_o
;
8725 opcode
= aco_opcode::image_sample_d_cl_o
;
8727 opcode
= aco_opcode::image_sample_b_cl_o
;
8729 } else if (has_compare
) {
8730 opcode
= aco_opcode::image_sample_c_o
;
8732 opcode
= aco_opcode::image_sample_c_d_o
;
8734 opcode
= aco_opcode::image_sample_c_b_o
;
8736 opcode
= aco_opcode::image_sample_c_lz_o
;
8738 opcode
= aco_opcode::image_sample_c_l_o
;
8740 opcode
= aco_opcode::image_sample_o
;
8742 opcode
= aco_opcode::image_sample_d_o
;
8744 opcode
= aco_opcode::image_sample_b_o
;
8746 opcode
= aco_opcode::image_sample_lz_o
;
8748 opcode
= aco_opcode::image_sample_l_o
;
8750 } else if (has_clamped_lod
) { /* image_sample_*_cl */
8752 opcode
= aco_opcode::image_sample_c_cl
;
8754 opcode
= aco_opcode::image_sample_c_d_cl
;
8756 opcode
= aco_opcode::image_sample_c_b_cl
;
8758 opcode
= aco_opcode::image_sample_cl
;
8760 opcode
= aco_opcode::image_sample_d_cl
;
8762 opcode
= aco_opcode::image_sample_b_cl
;
8764 } else { /* no offset */
8766 opcode
= aco_opcode::image_sample_c
;
8768 opcode
= aco_opcode::image_sample_c_d
;
8770 opcode
= aco_opcode::image_sample_c_b
;
8772 opcode
= aco_opcode::image_sample_c_lz
;
8774 opcode
= aco_opcode::image_sample_c_l
;
8776 opcode
= aco_opcode::image_sample
;
8778 opcode
= aco_opcode::image_sample_d
;
8780 opcode
= aco_opcode::image_sample_b
;
8782 opcode
= aco_opcode::image_sample_lz
;
8784 opcode
= aco_opcode::image_sample_l
;
8788 if (instr
->op
== nir_texop_tg4
) {
8789 if (has_offset
) { /* image_gather4_*_o */
8791 opcode
= aco_opcode::image_gather4_c_lz_o
;
8793 opcode
= aco_opcode::image_gather4_c_l_o
;
8795 opcode
= aco_opcode::image_gather4_c_b_o
;
8797 opcode
= aco_opcode::image_gather4_lz_o
;
8799 opcode
= aco_opcode::image_gather4_l_o
;
8801 opcode
= aco_opcode::image_gather4_b_o
;
8805 opcode
= aco_opcode::image_gather4_c_lz
;
8807 opcode
= aco_opcode::image_gather4_c_l
;
8809 opcode
= aco_opcode::image_gather4_c_b
;
8811 opcode
= aco_opcode::image_gather4_lz
;
8813 opcode
= aco_opcode::image_gather4_l
;
8815 opcode
= aco_opcode::image_gather4_b
;
8818 } else if (instr
->op
== nir_texop_lod
) {
8819 opcode
= aco_opcode::image_get_lod
;
8822 /* we don't need the bias, sample index, compare value or offset to be
8823 * computed in WQM but if the p_create_vector copies the coordinates, then it
8824 * needs to be in WQM */
8825 if (ctx
->stage
== fragment_fs
&&
8826 !has_derivs
&& !has_lod
&& !level_zero
&&
8827 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_MS
&&
8828 instr
->sampler_dim
!= GLSL_SAMPLER_DIM_SUBPASS_MS
)
8829 arg
= emit_wqm(ctx
, arg
, bld
.tmp(arg
.regClass()), true);
8831 tex
.reset(create_instruction
<MIMG_instruction
>(opcode
, Format::MIMG
, 3, 1));
8832 tex
->operands
[0] = Operand(resource
);
8833 tex
->operands
[1] = Operand(sampler
);
8834 tex
->operands
[2] = Operand(arg
);
8838 tex
->definitions
[0] = Definition(tmp_dst
);
8839 ctx
->block
->instructions
.emplace_back(std::move(tex
));
8841 if (tg4_integer_cube_workaround
) {
8842 assert(tmp_dst
.id() != dst
.id());
8843 assert(tmp_dst
.size() == dst
.size() && dst
.size() == 4);
8845 emit_split_vector(ctx
, tmp_dst
, tmp_dst
.size());
8847 for (unsigned i
= 0; i
< dst
.size(); i
++) {
8848 val
[i
] = emit_extract_vector(ctx
, tmp_dst
, i
, v1
);
8850 if (stype
== GLSL_TYPE_UINT
)
8851 cvt_val
= bld
.vop1(aco_opcode::v_cvt_u32_f32
, bld
.def(v1
), val
[i
]);
8853 cvt_val
= bld
.vop1(aco_opcode::v_cvt_i32_f32
, bld
.def(v1
), val
[i
]);
8854 val
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), val
[i
], cvt_val
, tg4_compare_cube_wa64
);
8856 Temp tmp
= dst
.regClass() == v4
? dst
: bld
.tmp(v4
);
8857 tmp_dst
= bld
.pseudo(aco_opcode::p_create_vector
, Definition(tmp
),
8858 val
[0], val
[1], val
[2], val
[3]);
8860 unsigned mask
= instr
->op
== nir_texop_tg4
? 0xF : dmask
;
8861 expand_vector(ctx
, tmp_dst
, dst
, instr
->dest
.ssa
.num_components
, mask
);
8866 Operand
get_phi_operand(isel_context
*ctx
, nir_ssa_def
*ssa
, RegClass rc
, bool logical
)
8868 Temp tmp
= get_ssa_temp(ctx
, ssa
);
8869 if (ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
8871 } else if (logical
&& ssa
->bit_size
== 1 && ssa
->parent_instr
->type
== nir_instr_type_load_const
) {
8872 if (ctx
->program
->wave_size
== 64)
8873 return Operand(nir_instr_as_load_const(ssa
->parent_instr
)->value
[0].b
? UINT64_MAX
: 0u);
8875 return Operand(nir_instr_as_load_const(ssa
->parent_instr
)->value
[0].b
? UINT32_MAX
: 0u);
8877 return Operand(tmp
);
8881 void visit_phi(isel_context
*ctx
, nir_phi_instr
*instr
)
8883 aco_ptr
<Pseudo_instruction
> phi
;
8884 Temp dst
= get_ssa_temp(ctx
, &instr
->dest
.ssa
);
8885 assert(instr
->dest
.ssa
.bit_size
!= 1 || dst
.regClass() == ctx
->program
->lane_mask
);
8887 bool logical
= !dst
.is_linear() || nir_dest_is_divergent(instr
->dest
);
8888 logical
|= ctx
->block
->kind
& block_kind_merge
;
8889 aco_opcode opcode
= logical
? aco_opcode::p_phi
: aco_opcode::p_linear_phi
;
8891 /* we want a sorted list of sources, since the predecessor list is also sorted */
8892 std::map
<unsigned, nir_ssa_def
*> phi_src
;
8893 nir_foreach_phi_src(src
, instr
)
8894 phi_src
[src
->pred
->index
] = src
->src
.ssa
;
8896 std::vector
<unsigned>& preds
= logical
? ctx
->block
->logical_preds
: ctx
->block
->linear_preds
;
8897 unsigned num_operands
= 0;
8898 Operand operands
[std::max(exec_list_length(&instr
->srcs
), (unsigned)preds
.size()) + 1];
8899 unsigned num_defined
= 0;
8900 unsigned cur_pred_idx
= 0;
8901 for (std::pair
<unsigned, nir_ssa_def
*> src
: phi_src
) {
8902 if (cur_pred_idx
< preds
.size()) {
8903 /* handle missing preds (IF merges with discard/break) and extra preds (loop exit with discard) */
8904 unsigned block
= ctx
->cf_info
.nir_to_aco
[src
.first
];
8905 unsigned skipped
= 0;
8906 while (cur_pred_idx
+ skipped
< preds
.size() && preds
[cur_pred_idx
+ skipped
] != block
)
8908 if (cur_pred_idx
+ skipped
< preds
.size()) {
8909 for (unsigned i
= 0; i
< skipped
; i
++)
8910 operands
[num_operands
++] = Operand(dst
.regClass());
8911 cur_pred_idx
+= skipped
;
8916 /* Handle missing predecessors at the end. This shouldn't happen with loop
8917 * headers and we can't ignore these sources for loop header phis. */
8918 if (!(ctx
->block
->kind
& block_kind_loop_header
) && cur_pred_idx
>= preds
.size())
8921 Operand op
= get_phi_operand(ctx
, src
.second
, dst
.regClass(), logical
);
8922 operands
[num_operands
++] = op
;
8923 num_defined
+= !op
.isUndefined();
8925 /* handle block_kind_continue_or_break at loop exit blocks */
8926 while (cur_pred_idx
++ < preds
.size())
8927 operands
[num_operands
++] = Operand(dst
.regClass());
8929 /* If the loop ends with a break, still add a linear continue edge in case
8930 * that break is divergent or continue_or_break is used. We'll either remove
8931 * this operand later in visit_loop() if it's not necessary or replace the
8932 * undef with something correct. */
8933 if (!logical
&& ctx
->block
->kind
& block_kind_loop_header
) {
8934 nir_loop
*loop
= nir_cf_node_as_loop(instr
->instr
.block
->cf_node
.parent
);
8935 nir_block
*last
= nir_loop_last_block(loop
);
8936 if (last
->successors
[0] != instr
->instr
.block
)
8937 operands
[num_operands
++] = Operand(RegClass());
8940 if (num_defined
== 0) {
8941 Builder
bld(ctx
->program
, ctx
->block
);
8942 if (dst
.regClass() == s1
) {
8943 bld
.sop1(aco_opcode::s_mov_b32
, Definition(dst
), Operand(0u));
8944 } else if (dst
.regClass() == v1
) {
8945 bld
.vop1(aco_opcode::v_mov_b32
, Definition(dst
), Operand(0u));
8947 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
8948 for (unsigned i
= 0; i
< dst
.size(); i
++)
8949 vec
->operands
[i
] = Operand(0u);
8950 vec
->definitions
[0] = Definition(dst
);
8951 ctx
->block
->instructions
.emplace_back(std::move(vec
));
8956 /* we can use a linear phi in some cases if one src is undef */
8957 if (dst
.is_linear() && ctx
->block
->kind
& block_kind_merge
&& num_defined
== 1) {
8958 phi
.reset(create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, num_operands
, 1));
8960 Block
*linear_else
= &ctx
->program
->blocks
[ctx
->block
->linear_preds
[1]];
8961 Block
*invert
= &ctx
->program
->blocks
[linear_else
->linear_preds
[0]];
8962 assert(invert
->kind
& block_kind_invert
);
8964 unsigned then_block
= invert
->linear_preds
[0];
8966 Block
* insert_block
= NULL
;
8967 for (unsigned i
= 0; i
< num_operands
; i
++) {
8968 Operand op
= operands
[i
];
8969 if (op
.isUndefined())
8971 insert_block
= ctx
->block
->logical_preds
[i
] == then_block
? invert
: ctx
->block
;
8972 phi
->operands
[0] = op
;
8975 assert(insert_block
); /* should be handled by the "num_defined == 0" case above */
8976 phi
->operands
[1] = Operand(dst
.regClass());
8977 phi
->definitions
[0] = Definition(dst
);
8978 insert_block
->instructions
.emplace(insert_block
->instructions
.begin(), std::move(phi
));
8982 /* try to scalarize vector phis */
8983 if (instr
->dest
.ssa
.bit_size
!= 1 && dst
.size() > 1) {
8984 // TODO: scalarize linear phis on divergent ifs
8985 bool can_scalarize
= (opcode
== aco_opcode::p_phi
|| !(ctx
->block
->kind
& block_kind_merge
));
8986 std::array
<Temp
, NIR_MAX_VEC_COMPONENTS
> new_vec
;
8987 for (unsigned i
= 0; can_scalarize
&& (i
< num_operands
); i
++) {
8988 Operand src
= operands
[i
];
8989 if (src
.isTemp() && ctx
->allocated_vec
.find(src
.tempId()) == ctx
->allocated_vec
.end())
8990 can_scalarize
= false;
8992 if (can_scalarize
) {
8993 unsigned num_components
= instr
->dest
.ssa
.num_components
;
8994 assert(dst
.size() % num_components
== 0);
8995 RegClass rc
= RegClass(dst
.type(), dst
.size() / num_components
);
8997 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, num_components
, 1)};
8998 for (unsigned k
= 0; k
< num_components
; k
++) {
8999 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9000 for (unsigned i
= 0; i
< num_operands
; i
++) {
9001 Operand src
= operands
[i
];
9002 phi
->operands
[i
] = src
.isTemp() ? Operand(ctx
->allocated_vec
[src
.tempId()][k
]) : Operand(rc
);
9004 Temp phi_dst
= {ctx
->program
->allocateId(), rc
};
9005 phi
->definitions
[0] = Definition(phi_dst
);
9006 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9007 new_vec
[k
] = phi_dst
;
9008 vec
->operands
[k
] = Operand(phi_dst
);
9010 vec
->definitions
[0] = Definition(dst
);
9011 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9012 ctx
->allocated_vec
.emplace(dst
.id(), new_vec
);
9017 phi
.reset(create_instruction
<Pseudo_instruction
>(opcode
, Format::PSEUDO
, num_operands
, 1));
9018 for (unsigned i
= 0; i
< num_operands
; i
++)
9019 phi
->operands
[i
] = operands
[i
];
9020 phi
->definitions
[0] = Definition(dst
);
9021 ctx
->block
->instructions
.emplace(ctx
->block
->instructions
.begin(), std::move(phi
));
9025 void visit_undef(isel_context
*ctx
, nir_ssa_undef_instr
*instr
)
9027 Temp dst
= get_ssa_temp(ctx
, &instr
->def
);
9029 assert(dst
.type() == RegType::sgpr
);
9031 if (dst
.size() == 1) {
9032 Builder(ctx
->program
, ctx
->block
).copy(Definition(dst
), Operand(0u));
9034 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, dst
.size(), 1)};
9035 for (unsigned i
= 0; i
< dst
.size(); i
++)
9036 vec
->operands
[i
] = Operand(0u);
9037 vec
->definitions
[0] = Definition(dst
);
9038 ctx
->block
->instructions
.emplace_back(std::move(vec
));
9042 void visit_jump(isel_context
*ctx
, nir_jump_instr
*instr
)
9044 Builder
bld(ctx
->program
, ctx
->block
);
9045 Block
*logical_target
;
9046 append_logical_end(ctx
->block
);
9047 unsigned idx
= ctx
->block
->index
;
9049 switch (instr
->type
) {
9050 case nir_jump_break
:
9051 logical_target
= ctx
->cf_info
.parent_loop
.exit
;
9052 add_logical_edge(idx
, logical_target
);
9053 ctx
->block
->kind
|= block_kind_break
;
9055 if (!ctx
->cf_info
.parent_if
.is_divergent
&&
9056 !ctx
->cf_info
.parent_loop
.has_divergent_continue
) {
9057 /* uniform break - directly jump out of the loop */
9058 ctx
->block
->kind
|= block_kind_uniform
;
9059 ctx
->cf_info
.has_branch
= true;
9060 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9061 add_linear_edge(idx
, logical_target
);
9064 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9065 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9067 case nir_jump_continue
:
9068 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9069 add_logical_edge(idx
, logical_target
);
9070 ctx
->block
->kind
|= block_kind_continue
;
9072 if (ctx
->cf_info
.parent_if
.is_divergent
) {
9073 /* for potential uniform breaks after this continue,
9074 we must ensure that they are handled correctly */
9075 ctx
->cf_info
.parent_loop
.has_divergent_continue
= true;
9076 ctx
->cf_info
.parent_loop
.has_divergent_branch
= true;
9077 ctx
->cf_info
.nir_to_aco
[instr
->instr
.block
->index
] = ctx
->block
->index
;
9079 /* uniform continue - directly jump to the loop header */
9080 ctx
->block
->kind
|= block_kind_uniform
;
9081 ctx
->cf_info
.has_branch
= true;
9082 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9083 add_linear_edge(idx
, logical_target
);
9088 isel_err(&instr
->instr
, "Unknown NIR jump instr");
9092 if (ctx
->cf_info
.parent_if
.is_divergent
&& !ctx
->cf_info
.exec_potentially_empty_break
) {
9093 ctx
->cf_info
.exec_potentially_empty_break
= true;
9094 ctx
->cf_info
.exec_potentially_empty_break_depth
= ctx
->cf_info
.loop_nest_depth
;
9097 /* remove critical edges from linear CFG */
9098 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9099 Block
* break_block
= ctx
->program
->create_and_insert_block();
9100 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9101 break_block
->kind
|= block_kind_uniform
;
9102 add_linear_edge(idx
, break_block
);
9103 /* the loop_header pointer might be invalidated by this point */
9104 if (instr
->type
== nir_jump_continue
)
9105 logical_target
= &ctx
->program
->blocks
[ctx
->cf_info
.parent_loop
.header_idx
];
9106 add_linear_edge(break_block
->index
, logical_target
);
9107 bld
.reset(break_block
);
9108 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9110 Block
* continue_block
= ctx
->program
->create_and_insert_block();
9111 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9112 add_linear_edge(idx
, continue_block
);
9113 append_logical_start(continue_block
);
9114 ctx
->block
= continue_block
;
9118 void visit_block(isel_context
*ctx
, nir_block
*block
)
9120 nir_foreach_instr(instr
, block
) {
9121 switch (instr
->type
) {
9122 case nir_instr_type_alu
:
9123 visit_alu_instr(ctx
, nir_instr_as_alu(instr
));
9125 case nir_instr_type_load_const
:
9126 visit_load_const(ctx
, nir_instr_as_load_const(instr
));
9128 case nir_instr_type_intrinsic
:
9129 visit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
9131 case nir_instr_type_tex
:
9132 visit_tex(ctx
, nir_instr_as_tex(instr
));
9134 case nir_instr_type_phi
:
9135 visit_phi(ctx
, nir_instr_as_phi(instr
));
9137 case nir_instr_type_ssa_undef
:
9138 visit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
9140 case nir_instr_type_deref
:
9142 case nir_instr_type_jump
:
9143 visit_jump(ctx
, nir_instr_as_jump(instr
));
9146 isel_err(instr
, "Unknown NIR instr type");
9151 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9152 ctx
->cf_info
.nir_to_aco
[block
->index
] = ctx
->block
->index
;
9157 static Operand
create_continue_phis(isel_context
*ctx
, unsigned first
, unsigned last
,
9158 aco_ptr
<Instruction
>& header_phi
, Operand
*vals
)
9160 vals
[0] = Operand(header_phi
->definitions
[0].getTemp());
9161 RegClass rc
= vals
[0].regClass();
9163 unsigned loop_nest_depth
= ctx
->program
->blocks
[first
].loop_nest_depth
;
9165 unsigned next_pred
= 1;
9167 for (unsigned idx
= first
+ 1; idx
<= last
; idx
++) {
9168 Block
& block
= ctx
->program
->blocks
[idx
];
9169 if (block
.loop_nest_depth
!= loop_nest_depth
) {
9170 vals
[idx
- first
] = vals
[idx
- 1 - first
];
9174 if (block
.kind
& block_kind_continue
) {
9175 vals
[idx
- first
] = header_phi
->operands
[next_pred
];
9180 bool all_same
= true;
9181 for (unsigned i
= 1; all_same
&& (i
< block
.linear_preds
.size()); i
++)
9182 all_same
= vals
[block
.linear_preds
[i
] - first
] == vals
[block
.linear_preds
[0] - first
];
9186 val
= vals
[block
.linear_preds
[0] - first
];
9188 aco_ptr
<Instruction
> phi(create_instruction
<Pseudo_instruction
>(
9189 aco_opcode::p_linear_phi
, Format::PSEUDO
, block
.linear_preds
.size(), 1));
9190 for (unsigned i
= 0; i
< block
.linear_preds
.size(); i
++)
9191 phi
->operands
[i
] = vals
[block
.linear_preds
[i
] - first
];
9192 val
= Operand(Temp(ctx
->program
->allocateId(), rc
));
9193 phi
->definitions
[0] = Definition(val
.getTemp());
9194 block
.instructions
.emplace(block
.instructions
.begin(), std::move(phi
));
9196 vals
[idx
- first
] = val
;
9199 return vals
[last
- first
];
9202 static void visit_loop(isel_context
*ctx
, nir_loop
*loop
)
9204 //TODO: we might want to wrap the loop around a branch if exec_potentially_empty=true
9205 append_logical_end(ctx
->block
);
9206 ctx
->block
->kind
|= block_kind_loop_preheader
| block_kind_uniform
;
9207 Builder
bld(ctx
->program
, ctx
->block
);
9208 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9209 unsigned loop_preheader_idx
= ctx
->block
->index
;
9211 Block loop_exit
= Block();
9212 loop_exit
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9213 loop_exit
.kind
|= (block_kind_loop_exit
| (ctx
->block
->kind
& block_kind_top_level
));
9215 Block
* loop_header
= ctx
->program
->create_and_insert_block();
9216 loop_header
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
+ 1;
9217 loop_header
->kind
|= block_kind_loop_header
;
9218 add_edge(loop_preheader_idx
, loop_header
);
9219 ctx
->block
= loop_header
;
9221 /* emit loop body */
9222 unsigned loop_header_idx
= loop_header
->index
;
9223 loop_info_RAII
loop_raii(ctx
, loop_header_idx
, &loop_exit
);
9224 append_logical_start(ctx
->block
);
9225 bool unreachable
= visit_cf_list(ctx
, &loop
->body
);
9227 //TODO: what if a loop ends with a unconditional or uniformly branched continue and this branch is never taken?
9228 if (!ctx
->cf_info
.has_branch
) {
9229 append_logical_end(ctx
->block
);
9230 if (ctx
->cf_info
.exec_potentially_empty_discard
|| ctx
->cf_info
.exec_potentially_empty_break
) {
9231 /* Discards can result in code running with an empty exec mask.
9232 * This would result in divergent breaks not ever being taken. As a
9233 * workaround, break the loop when the loop mask is empty instead of
9234 * always continuing. */
9235 ctx
->block
->kind
|= (block_kind_continue_or_break
| block_kind_uniform
);
9236 unsigned block_idx
= ctx
->block
->index
;
9238 /* create helper blocks to avoid critical edges */
9239 Block
*break_block
= ctx
->program
->create_and_insert_block();
9240 break_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9241 break_block
->kind
= block_kind_uniform
;
9242 bld
.reset(break_block
);
9243 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9244 add_linear_edge(block_idx
, break_block
);
9245 add_linear_edge(break_block
->index
, &loop_exit
);
9247 Block
*continue_block
= ctx
->program
->create_and_insert_block();
9248 continue_block
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9249 continue_block
->kind
= block_kind_uniform
;
9250 bld
.reset(continue_block
);
9251 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9252 add_linear_edge(block_idx
, continue_block
);
9253 add_linear_edge(continue_block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9255 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9256 add_logical_edge(block_idx
, &ctx
->program
->blocks
[loop_header_idx
]);
9257 ctx
->block
= &ctx
->program
->blocks
[block_idx
];
9259 ctx
->block
->kind
|= (block_kind_continue
| block_kind_uniform
);
9260 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9261 add_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9263 add_linear_edge(ctx
->block
->index
, &ctx
->program
->blocks
[loop_header_idx
]);
9266 bld
.reset(ctx
->block
);
9267 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
9270 /* Fixup phis in loop header from unreachable blocks.
9271 * has_branch/has_divergent_branch also indicates if the loop ends with a
9272 * break/continue instruction, but we don't emit those if unreachable=true */
9274 assert(ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
);
9275 bool linear
= ctx
->cf_info
.has_branch
;
9276 bool logical
= ctx
->cf_info
.has_branch
|| ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9277 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9278 if ((logical
&& instr
->opcode
== aco_opcode::p_phi
) ||
9279 (linear
&& instr
->opcode
== aco_opcode::p_linear_phi
)) {
9280 /* the last operand should be the one that needs to be removed */
9281 instr
->operands
.pop_back();
9282 } else if (!is_phi(instr
)) {
9288 /* Fixup linear phis in loop header from expecting a continue. Both this fixup
9289 * and the previous one shouldn't both happen at once because a break in the
9290 * merge block would get CSE'd */
9291 if (nir_loop_last_block(loop
)->successors
[0] != nir_loop_first_block(loop
)) {
9292 unsigned num_vals
= ctx
->cf_info
.has_branch
? 1 : (ctx
->block
->index
- loop_header_idx
+ 1);
9293 Operand vals
[num_vals
];
9294 for (aco_ptr
<Instruction
>& instr
: ctx
->program
->blocks
[loop_header_idx
].instructions
) {
9295 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9296 if (ctx
->cf_info
.has_branch
)
9297 instr
->operands
.pop_back();
9299 instr
->operands
.back() = create_continue_phis(ctx
, loop_header_idx
, ctx
->block
->index
, instr
, vals
);
9300 } else if (!is_phi(instr
)) {
9306 ctx
->cf_info
.has_branch
= false;
9308 // TODO: if the loop has not a single exit, we must add one °°
9309 /* emit loop successor block */
9310 ctx
->block
= ctx
->program
->insert_block(std::move(loop_exit
));
9311 append_logical_start(ctx
->block
);
9314 // TODO: check if it is beneficial to not branch on continues
9315 /* trim linear phis in loop header */
9316 for (auto&& instr
: loop_entry
->instructions
) {
9317 if (instr
->opcode
== aco_opcode::p_linear_phi
) {
9318 aco_ptr
<Pseudo_instruction
> new_phi
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_linear_phi
, Format::PSEUDO
, loop_entry
->linear_predecessors
.size(), 1)};
9319 new_phi
->definitions
[0] = instr
->definitions
[0];
9320 for (unsigned i
= 0; i
< new_phi
->operands
.size(); i
++)
9321 new_phi
->operands
[i
] = instr
->operands
[i
];
9322 /* check that the remaining operands are all the same */
9323 for (unsigned i
= new_phi
->operands
.size(); i
< instr
->operands
.size(); i
++)
9324 assert(instr
->operands
[i
].tempId() == instr
->operands
.back().tempId());
9325 instr
.swap(new_phi
);
9326 } else if (instr
->opcode
== aco_opcode::p_phi
) {
9335 static void begin_divergent_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9339 append_logical_end(ctx
->block
);
9340 ctx
->block
->kind
|= block_kind_branch
;
9342 /* branch to linear then block */
9343 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9344 aco_ptr
<Pseudo_branch_instruction
> branch
;
9345 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_z
, Format::PSEUDO_BRANCH
, 1, 1));
9346 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9347 branch
->definitions
[0].setHint(vcc
);
9348 branch
->operands
[0] = Operand(cond
);
9349 ctx
->block
->instructions
.push_back(std::move(branch
));
9351 ic
->BB_if_idx
= ctx
->block
->index
;
9352 ic
->BB_invert
= Block();
9353 ic
->BB_invert
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9354 /* Invert blocks are intentionally not marked as top level because they
9355 * are not part of the logical cfg. */
9356 ic
->BB_invert
.kind
|= block_kind_invert
;
9357 ic
->BB_endif
= Block();
9358 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9359 ic
->BB_endif
.kind
|= (block_kind_merge
| (ctx
->block
->kind
& block_kind_top_level
));
9361 ic
->exec_potentially_empty_discard_old
= ctx
->cf_info
.exec_potentially_empty_discard
;
9362 ic
->exec_potentially_empty_break_old
= ctx
->cf_info
.exec_potentially_empty_break
;
9363 ic
->exec_potentially_empty_break_depth_old
= ctx
->cf_info
.exec_potentially_empty_break_depth
;
9364 ic
->divergent_old
= ctx
->cf_info
.parent_if
.is_divergent
;
9365 ctx
->cf_info
.parent_if
.is_divergent
= true;
9367 /* divergent branches use cbranch_execz */
9368 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9369 ctx
->cf_info
.exec_potentially_empty_break
= false;
9370 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9372 /** emit logical then block */
9373 Block
* BB_then_logical
= ctx
->program
->create_and_insert_block();
9374 BB_then_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9375 add_edge(ic
->BB_if_idx
, BB_then_logical
);
9376 ctx
->block
= BB_then_logical
;
9377 append_logical_start(BB_then_logical
);
9380 static void begin_divergent_if_else(isel_context
*ctx
, if_context
*ic
)
9382 Block
*BB_then_logical
= ctx
->block
;
9383 append_logical_end(BB_then_logical
);
9384 /* branch from logical then block to invert block */
9385 aco_ptr
<Pseudo_branch_instruction
> branch
;
9386 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 1));
9387 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9388 branch
->definitions
[0].setHint(vcc
);
9389 BB_then_logical
->instructions
.emplace_back(std::move(branch
));
9390 add_linear_edge(BB_then_logical
->index
, &ic
->BB_invert
);
9391 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9392 add_logical_edge(BB_then_logical
->index
, &ic
->BB_endif
);
9393 BB_then_logical
->kind
|= block_kind_uniform
;
9394 assert(!ctx
->cf_info
.has_branch
);
9395 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9396 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9398 /** emit linear then block */
9399 Block
* BB_then_linear
= ctx
->program
->create_and_insert_block();
9400 BB_then_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9401 BB_then_linear
->kind
|= block_kind_uniform
;
9402 add_linear_edge(ic
->BB_if_idx
, BB_then_linear
);
9403 /* branch from linear then block to invert block */
9404 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 1));
9405 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9406 branch
->definitions
[0].setHint(vcc
);
9407 BB_then_linear
->instructions
.emplace_back(std::move(branch
));
9408 add_linear_edge(BB_then_linear
->index
, &ic
->BB_invert
);
9410 /** emit invert merge block */
9411 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_invert
));
9412 ic
->invert_idx
= ctx
->block
->index
;
9414 /* branch to linear else block (skip else) */
9415 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_cbranch_nz
, Format::PSEUDO_BRANCH
, 1, 1));
9416 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9417 branch
->definitions
[0].setHint(vcc
);
9418 branch
->operands
[0] = Operand(ic
->cond
);
9419 ctx
->block
->instructions
.push_back(std::move(branch
));
9421 ic
->exec_potentially_empty_discard_old
|= ctx
->cf_info
.exec_potentially_empty_discard
;
9422 ic
->exec_potentially_empty_break_old
|= ctx
->cf_info
.exec_potentially_empty_break
;
9423 ic
->exec_potentially_empty_break_depth_old
=
9424 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9425 /* divergent branches use cbranch_execz */
9426 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9427 ctx
->cf_info
.exec_potentially_empty_break
= false;
9428 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9430 /** emit logical else block */
9431 Block
* BB_else_logical
= ctx
->program
->create_and_insert_block();
9432 BB_else_logical
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9433 add_logical_edge(ic
->BB_if_idx
, BB_else_logical
);
9434 add_linear_edge(ic
->invert_idx
, BB_else_logical
);
9435 ctx
->block
= BB_else_logical
;
9436 append_logical_start(BB_else_logical
);
9439 static void end_divergent_if(isel_context
*ctx
, if_context
*ic
)
9441 Block
*BB_else_logical
= ctx
->block
;
9442 append_logical_end(BB_else_logical
);
9444 /* branch from logical else block to endif block */
9445 aco_ptr
<Pseudo_branch_instruction
> branch
;
9446 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 1));
9447 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9448 branch
->definitions
[0].setHint(vcc
);
9449 BB_else_logical
->instructions
.emplace_back(std::move(branch
));
9450 add_linear_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9451 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9452 add_logical_edge(BB_else_logical
->index
, &ic
->BB_endif
);
9453 BB_else_logical
->kind
|= block_kind_uniform
;
9455 assert(!ctx
->cf_info
.has_branch
);
9456 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9459 /** emit linear else block */
9460 Block
* BB_else_linear
= ctx
->program
->create_and_insert_block();
9461 BB_else_linear
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9462 BB_else_linear
->kind
|= block_kind_uniform
;
9463 add_linear_edge(ic
->invert_idx
, BB_else_linear
);
9465 /* branch from linear else block to endif block */
9466 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 1));
9467 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9468 branch
->definitions
[0].setHint(vcc
);
9469 BB_else_linear
->instructions
.emplace_back(std::move(branch
));
9470 add_linear_edge(BB_else_linear
->index
, &ic
->BB_endif
);
9473 /** emit endif merge block */
9474 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9475 append_logical_start(ctx
->block
);
9478 ctx
->cf_info
.parent_if
.is_divergent
= ic
->divergent_old
;
9479 ctx
->cf_info
.exec_potentially_empty_discard
|= ic
->exec_potentially_empty_discard_old
;
9480 ctx
->cf_info
.exec_potentially_empty_break
|= ic
->exec_potentially_empty_break_old
;
9481 ctx
->cf_info
.exec_potentially_empty_break_depth
=
9482 std::min(ic
->exec_potentially_empty_break_depth_old
, ctx
->cf_info
.exec_potentially_empty_break_depth
);
9483 if (ctx
->cf_info
.loop_nest_depth
== ctx
->cf_info
.exec_potentially_empty_break_depth
&&
9484 !ctx
->cf_info
.parent_if
.is_divergent
) {
9485 ctx
->cf_info
.exec_potentially_empty_break
= false;
9486 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9488 /* uniform control flow never has an empty exec-mask */
9489 if (!ctx
->cf_info
.loop_nest_depth
&& !ctx
->cf_info
.parent_if
.is_divergent
) {
9490 ctx
->cf_info
.exec_potentially_empty_discard
= false;
9491 ctx
->cf_info
.exec_potentially_empty_break
= false;
9492 ctx
->cf_info
.exec_potentially_empty_break_depth
= UINT16_MAX
;
9496 static void begin_uniform_if_then(isel_context
*ctx
, if_context
*ic
, Temp cond
)
9498 assert(cond
.regClass() == s1
);
9500 append_logical_end(ctx
->block
);
9501 ctx
->block
->kind
|= block_kind_uniform
;
9503 aco_ptr
<Pseudo_branch_instruction
> branch
;
9504 aco_opcode branch_opcode
= aco_opcode::p_cbranch_z
;
9505 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(branch_opcode
, Format::PSEUDO_BRANCH
, 1, 1));
9506 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9507 branch
->definitions
[0].setHint(vcc
);
9508 branch
->operands
[0] = Operand(cond
);
9509 branch
->operands
[0].setFixed(scc
);
9510 ctx
->block
->instructions
.emplace_back(std::move(branch
));
9512 ic
->BB_if_idx
= ctx
->block
->index
;
9513 ic
->BB_endif
= Block();
9514 ic
->BB_endif
.loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9515 ic
->BB_endif
.kind
|= ctx
->block
->kind
& block_kind_top_level
;
9517 ctx
->cf_info
.has_branch
= false;
9518 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9520 /** emit then block */
9521 Block
* BB_then
= ctx
->program
->create_and_insert_block();
9522 BB_then
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9523 add_edge(ic
->BB_if_idx
, BB_then
);
9524 append_logical_start(BB_then
);
9525 ctx
->block
= BB_then
;
9528 static void begin_uniform_if_else(isel_context
*ctx
, if_context
*ic
)
9530 Block
*BB_then
= ctx
->block
;
9532 ic
->uniform_has_then_branch
= ctx
->cf_info
.has_branch
;
9533 ic
->then_branch_divergent
= ctx
->cf_info
.parent_loop
.has_divergent_branch
;
9535 if (!ic
->uniform_has_then_branch
) {
9536 append_logical_end(BB_then
);
9537 /* branch from then block to endif block */
9538 aco_ptr
<Pseudo_branch_instruction
> branch
;
9539 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 1));
9540 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9541 branch
->definitions
[0].setHint(vcc
);
9542 BB_then
->instructions
.emplace_back(std::move(branch
));
9543 add_linear_edge(BB_then
->index
, &ic
->BB_endif
);
9544 if (!ic
->then_branch_divergent
)
9545 add_logical_edge(BB_then
->index
, &ic
->BB_endif
);
9546 BB_then
->kind
|= block_kind_uniform
;
9549 ctx
->cf_info
.has_branch
= false;
9550 ctx
->cf_info
.parent_loop
.has_divergent_branch
= false;
9552 /** emit else block */
9553 Block
* BB_else
= ctx
->program
->create_and_insert_block();
9554 BB_else
->loop_nest_depth
= ctx
->cf_info
.loop_nest_depth
;
9555 add_edge(ic
->BB_if_idx
, BB_else
);
9556 append_logical_start(BB_else
);
9557 ctx
->block
= BB_else
;
9560 static void end_uniform_if(isel_context
*ctx
, if_context
*ic
)
9562 Block
*BB_else
= ctx
->block
;
9564 if (!ctx
->cf_info
.has_branch
) {
9565 append_logical_end(BB_else
);
9566 /* branch from then block to endif block */
9567 aco_ptr
<Pseudo_branch_instruction
> branch
;
9568 branch
.reset(create_instruction
<Pseudo_branch_instruction
>(aco_opcode::p_branch
, Format::PSEUDO_BRANCH
, 0, 1));
9569 branch
->definitions
[0] = {ctx
->program
->allocateId(), s2
};
9570 branch
->definitions
[0].setHint(vcc
);
9571 BB_else
->instructions
.emplace_back(std::move(branch
));
9572 add_linear_edge(BB_else
->index
, &ic
->BB_endif
);
9573 if (!ctx
->cf_info
.parent_loop
.has_divergent_branch
)
9574 add_logical_edge(BB_else
->index
, &ic
->BB_endif
);
9575 BB_else
->kind
|= block_kind_uniform
;
9578 ctx
->cf_info
.has_branch
&= ic
->uniform_has_then_branch
;
9579 ctx
->cf_info
.parent_loop
.has_divergent_branch
&= ic
->then_branch_divergent
;
9581 /** emit endif merge block */
9582 if (!ctx
->cf_info
.has_branch
) {
9583 ctx
->block
= ctx
->program
->insert_block(std::move(ic
->BB_endif
));
9584 append_logical_start(ctx
->block
);
9588 static bool visit_if(isel_context
*ctx
, nir_if
*if_stmt
)
9590 Temp cond
= get_ssa_temp(ctx
, if_stmt
->condition
.ssa
);
9591 Builder
bld(ctx
->program
, ctx
->block
);
9592 aco_ptr
<Pseudo_branch_instruction
> branch
;
9595 if (!nir_src_is_divergent(if_stmt
->condition
)) { /* uniform condition */
9597 * Uniform conditionals are represented in the following way*) :
9599 * The linear and logical CFG:
9602 * BB_THEN (logical) BB_ELSE (logical)
9606 * *) Exceptions may be due to break and continue statements within loops
9607 * If a break/continue happens within uniform control flow, it branches
9608 * to the loop exit/entry block. Otherwise, it branches to the next
9612 // TODO: in a post-RA optimizer, we could check if the condition is in VCC and omit this instruction
9613 assert(cond
.regClass() == ctx
->program
->lane_mask
);
9614 cond
= bool_to_scalar_condition(ctx
, cond
);
9616 begin_uniform_if_then(ctx
, &ic
, cond
);
9617 visit_cf_list(ctx
, &if_stmt
->then_list
);
9619 begin_uniform_if_else(ctx
, &ic
);
9620 visit_cf_list(ctx
, &if_stmt
->else_list
);
9622 end_uniform_if(ctx
, &ic
);
9623 } else { /* non-uniform condition */
9625 * To maintain a logical and linear CFG without critical edges,
9626 * non-uniform conditionals are represented in the following way*) :
9631 * BB_THEN (logical) BB_THEN (linear)
9633 * BB_INVERT (linear)
9635 * BB_ELSE (logical) BB_ELSE (linear)
9642 * BB_THEN (logical) BB_ELSE (logical)
9646 * *) Exceptions may be due to break and continue statements within loops
9649 begin_divergent_if_then(ctx
, &ic
, cond
);
9650 visit_cf_list(ctx
, &if_stmt
->then_list
);
9652 begin_divergent_if_else(ctx
, &ic
);
9653 visit_cf_list(ctx
, &if_stmt
->else_list
);
9655 end_divergent_if(ctx
, &ic
);
9658 return !ctx
->cf_info
.has_branch
&& !ctx
->block
->logical_preds
.empty();
9661 static bool visit_cf_list(isel_context
*ctx
,
9662 struct exec_list
*list
)
9664 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
9665 switch (node
->type
) {
9666 case nir_cf_node_block
:
9667 visit_block(ctx
, nir_cf_node_as_block(node
));
9669 case nir_cf_node_if
:
9670 if (!visit_if(ctx
, nir_cf_node_as_if(node
)))
9673 case nir_cf_node_loop
:
9674 visit_loop(ctx
, nir_cf_node_as_loop(node
));
9677 unreachable("unimplemented cf list type");
9683 static void create_null_export(isel_context
*ctx
)
9685 /* Some shader stages always need to have exports.
9686 * So when there is none, we need to add a null export.
9689 unsigned dest
= (ctx
->program
->stage
& hw_fs
) ? 9 /* NULL */ : V_008DFC_SQ_EXP_POS
;
9690 bool vm
= (ctx
->program
->stage
& hw_fs
) || ctx
->program
->chip_class
>= GFX10
;
9691 Builder
bld(ctx
->program
, ctx
->block
);
9692 bld
.exp(aco_opcode::exp
, Operand(v1
), Operand(v1
), Operand(v1
), Operand(v1
),
9693 /* enabled_mask */ 0, dest
, /* compr */ false, /* done */ true, vm
);
9696 static bool export_vs_varying(isel_context
*ctx
, int slot
, bool is_pos
, int *next_pos
)
9698 assert(ctx
->stage
== vertex_vs
||
9699 ctx
->stage
== tess_eval_vs
||
9700 ctx
->stage
== gs_copy_vs
||
9701 ctx
->stage
== ngg_vertex_gs
||
9702 ctx
->stage
== ngg_tess_eval_gs
);
9704 int offset
= (ctx
->stage
& sw_tes
)
9705 ? ctx
->program
->info
->tes
.outinfo
.vs_output_param_offset
[slot
]
9706 : ctx
->program
->info
->vs
.outinfo
.vs_output_param_offset
[slot
];
9707 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9708 if (!is_pos
&& !mask
)
9710 if (!is_pos
&& offset
== AC_EXP_PARAM_UNDEFINED
)
9712 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9713 exp
->enabled_mask
= mask
;
9714 for (unsigned i
= 0; i
< 4; ++i
) {
9715 if (mask
& (1 << i
))
9716 exp
->operands
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9718 exp
->operands
[i
] = Operand(v1
);
9720 /* GFX10 (Navi1x) skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
9721 * Setting valid_mask=1 prevents it and has no other effect.
9723 exp
->valid_mask
= ctx
->options
->chip_class
== GFX10
&& is_pos
&& *next_pos
== 0;
9725 exp
->compressed
= false;
9727 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9729 exp
->dest
= V_008DFC_SQ_EXP_PARAM
+ offset
;
9730 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9735 static void export_vs_psiz_layer_viewport(isel_context
*ctx
, int *next_pos
)
9737 aco_ptr
<Export_instruction
> exp
{create_instruction
<Export_instruction
>(aco_opcode::exp
, Format::EXP
, 4, 0)};
9738 exp
->enabled_mask
= 0;
9739 for (unsigned i
= 0; i
< 4; ++i
)
9740 exp
->operands
[i
] = Operand(v1
);
9741 if (ctx
->outputs
.mask
[VARYING_SLOT_PSIZ
]) {
9742 exp
->operands
[0] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_PSIZ
* 4u]);
9743 exp
->enabled_mask
|= 0x1;
9745 if (ctx
->outputs
.mask
[VARYING_SLOT_LAYER
]) {
9746 exp
->operands
[2] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u]);
9747 exp
->enabled_mask
|= 0x4;
9749 if (ctx
->outputs
.mask
[VARYING_SLOT_VIEWPORT
]) {
9750 if (ctx
->options
->chip_class
< GFX9
) {
9751 exp
->operands
[3] = Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]);
9752 exp
->enabled_mask
|= 0x8;
9754 Builder
bld(ctx
->program
, ctx
->block
);
9756 Temp out
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u),
9757 Operand(ctx
->outputs
.temps
[VARYING_SLOT_VIEWPORT
* 4u]));
9758 if (exp
->operands
[2].isTemp())
9759 out
= bld
.vop2(aco_opcode::v_or_b32
, bld
.def(v1
), Operand(out
), exp
->operands
[2]);
9761 exp
->operands
[2] = Operand(out
);
9762 exp
->enabled_mask
|= 0x4;
9765 exp
->valid_mask
= ctx
->options
->chip_class
== GFX10
&& *next_pos
== 0;
9767 exp
->compressed
= false;
9768 exp
->dest
= V_008DFC_SQ_EXP_POS
+ (*next_pos
)++;
9769 ctx
->block
->instructions
.emplace_back(std::move(exp
));
9772 static void create_export_phis(isel_context
*ctx
)
9774 /* Used when exports are needed, but the output temps are defined in a preceding block.
9775 * This function will set up phis in order to access the outputs in the next block.
9778 assert(ctx
->block
->instructions
.back()->opcode
== aco_opcode::p_logical_start
);
9779 aco_ptr
<Instruction
> logical_start
= aco_ptr
<Instruction
>(ctx
->block
->instructions
.back().release());
9780 ctx
->block
->instructions
.pop_back();
9782 Builder
bld(ctx
->program
, ctx
->block
);
9784 for (unsigned slot
= 0; slot
<= VARYING_SLOT_VAR31
; ++slot
) {
9785 uint64_t mask
= ctx
->outputs
.mask
[slot
];
9786 for (unsigned i
= 0; i
< 4; ++i
) {
9787 if (!(mask
& (1 << i
)))
9790 Temp old
= ctx
->outputs
.temps
[slot
* 4 + i
];
9791 Temp phi
= bld
.pseudo(aco_opcode::p_phi
, bld
.def(v1
), old
, Operand(v1
));
9792 ctx
->outputs
.temps
[slot
* 4 + i
] = phi
;
9796 bld
.insert(std::move(logical_start
));
9799 static void create_vs_exports(isel_context
*ctx
)
9801 assert(ctx
->stage
== vertex_vs
||
9802 ctx
->stage
== tess_eval_vs
||
9803 ctx
->stage
== gs_copy_vs
||
9804 ctx
->stage
== ngg_vertex_gs
||
9805 ctx
->stage
== ngg_tess_eval_gs
);
9807 radv_vs_output_info
*outinfo
= (ctx
->stage
& sw_tes
)
9808 ? &ctx
->program
->info
->tes
.outinfo
9809 : &ctx
->program
->info
->vs
.outinfo
;
9811 if (outinfo
->export_prim_id
&& !(ctx
->stage
& hw_ngg_gs
)) {
9812 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
9813 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = get_arg(ctx
, ctx
->args
->vs_prim_id
);
9816 if (ctx
->options
->key
.has_multiview_view_index
) {
9817 ctx
->outputs
.mask
[VARYING_SLOT_LAYER
] |= 0x1;
9818 ctx
->outputs
.temps
[VARYING_SLOT_LAYER
* 4u] = as_vgpr(ctx
, get_arg(ctx
, ctx
->args
->ac
.view_index
));
9821 /* the order these position exports are created is important */
9823 bool exported_pos
= export_vs_varying(ctx
, VARYING_SLOT_POS
, true, &next_pos
);
9824 if (outinfo
->writes_pointsize
|| outinfo
->writes_layer
|| outinfo
->writes_viewport_index
) {
9825 export_vs_psiz_layer_viewport(ctx
, &next_pos
);
9826 exported_pos
= true;
9828 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9829 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, true, &next_pos
);
9830 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9831 exported_pos
|= export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, true, &next_pos
);
9833 if (ctx
->export_clip_dists
) {
9834 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 0)
9835 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST0
, false, &next_pos
);
9836 if (ctx
->num_clip_distances
+ ctx
->num_cull_distances
> 4)
9837 export_vs_varying(ctx
, VARYING_SLOT_CLIP_DIST1
, false, &next_pos
);
9840 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
9841 if (i
< VARYING_SLOT_VAR0
&&
9842 i
!= VARYING_SLOT_LAYER
&&
9843 i
!= VARYING_SLOT_PRIMITIVE_ID
&&
9844 i
!= VARYING_SLOT_VIEWPORT
)
9847 export_vs_varying(ctx
, i
, false, NULL
);
9851 create_null_export(ctx
);
9854 static bool export_fs_mrt_z(isel_context
*ctx
)
9856 Builder
bld(ctx
->program
, ctx
->block
);
9857 unsigned enabled_channels
= 0;
9861 for (unsigned i
= 0; i
< 4; ++i
) {
9862 values
[i
] = Operand(v1
);
9865 /* Both stencil and sample mask only need 16-bits. */
9866 if (!ctx
->program
->info
->ps
.writes_z
&&
9867 (ctx
->program
->info
->ps
.writes_stencil
||
9868 ctx
->program
->info
->ps
.writes_sample_mask
)) {
9869 compr
= true; /* COMPR flag */
9871 if (ctx
->program
->info
->ps
.writes_stencil
) {
9872 /* Stencil should be in X[23:16]. */
9873 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9874 values
[0] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(16u), values
[0]);
9875 enabled_channels
|= 0x3;
9878 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9879 /* SampleMask should be in Y[15:0]. */
9880 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9881 enabled_channels
|= 0xc;
9884 if (ctx
->program
->info
->ps
.writes_z
) {
9885 values
[0] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_DEPTH
* 4u]);
9886 enabled_channels
|= 0x1;
9889 if (ctx
->program
->info
->ps
.writes_stencil
) {
9890 values
[1] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_STENCIL
* 4u]);
9891 enabled_channels
|= 0x2;
9894 if (ctx
->program
->info
->ps
.writes_sample_mask
) {
9895 values
[2] = Operand(ctx
->outputs
.temps
[FRAG_RESULT_SAMPLE_MASK
* 4u]);
9896 enabled_channels
|= 0x4;
9900 /* GFX6 (except OLAND and HAINAN) has a bug that it only looks at the X
9901 * writemask component.
9903 if (ctx
->options
->chip_class
== GFX6
&&
9904 ctx
->options
->family
!= CHIP_OLAND
&&
9905 ctx
->options
->family
!= CHIP_HAINAN
) {
9906 enabled_channels
|= 0x1;
9909 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
9910 enabled_channels
, V_008DFC_SQ_EXP_MRTZ
, compr
);
9915 static bool export_fs_mrt_color(isel_context
*ctx
, int slot
)
9917 Builder
bld(ctx
->program
, ctx
->block
);
9918 unsigned write_mask
= ctx
->outputs
.mask
[slot
];
9921 for (unsigned i
= 0; i
< 4; ++i
) {
9922 if (write_mask
& (1 << i
)) {
9923 values
[i
] = Operand(ctx
->outputs
.temps
[slot
* 4u + i
]);
9925 values
[i
] = Operand(v1
);
9929 unsigned target
, col_format
;
9930 unsigned enabled_channels
= 0;
9931 aco_opcode compr_op
= (aco_opcode
)0;
9933 slot
-= FRAG_RESULT_DATA0
;
9934 target
= V_008DFC_SQ_EXP_MRT
+ slot
;
9935 col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * slot
)) & 0xf;
9937 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> slot
) & 1;
9938 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> slot
) & 1;
9939 bool is_16bit
= values
[0].regClass() == v2b
;
9943 case V_028714_SPI_SHADER_ZERO
:
9944 enabled_channels
= 0; /* writemask */
9945 target
= V_008DFC_SQ_EXP_NULL
;
9948 case V_028714_SPI_SHADER_32_R
:
9949 enabled_channels
= 1;
9952 case V_028714_SPI_SHADER_32_GR
:
9953 enabled_channels
= 0x3;
9956 case V_028714_SPI_SHADER_32_AR
:
9957 if (ctx
->options
->chip_class
>= GFX10
) {
9958 /* Special case: on GFX10, the outputs are different for 32_AR */
9959 enabled_channels
= 0x3;
9960 values
[1] = values
[3];
9961 values
[3] = Operand(v1
);
9963 enabled_channels
= 0x9;
9967 case V_028714_SPI_SHADER_FP16_ABGR
:
9968 enabled_channels
= 0x5;
9969 compr_op
= aco_opcode::v_cvt_pkrtz_f16_f32
;
9971 if (ctx
->options
->chip_class
>= GFX9
) {
9972 /* Pack the FP16 values together instead of converting them to
9973 * FP32 and back to FP16.
9974 * TODO: use p_create_vector and let the compiler optimizes.
9976 compr_op
= aco_opcode::v_pack_b32_f16
;
9978 for (unsigned i
= 0; i
< 4; i
++) {
9979 if ((write_mask
>> i
) & 1)
9980 values
[i
] = bld
.vop1(aco_opcode::v_cvt_f32_f16
, bld
.def(v1
), values
[i
]);
9986 case V_028714_SPI_SHADER_UNORM16_ABGR
:
9987 enabled_channels
= 0x5;
9988 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
9989 compr_op
= aco_opcode::v_cvt_pknorm_u16_f16
;
9991 compr_op
= aco_opcode::v_cvt_pknorm_u16_f32
;
9995 case V_028714_SPI_SHADER_SNORM16_ABGR
:
9996 enabled_channels
= 0x5;
9997 if (is_16bit
&& ctx
->options
->chip_class
>= GFX9
) {
9998 compr_op
= aco_opcode::v_cvt_pknorm_i16_f16
;
10000 compr_op
= aco_opcode::v_cvt_pknorm_i16_f32
;
10004 case V_028714_SPI_SHADER_UINT16_ABGR
: {
10005 enabled_channels
= 0x5;
10006 compr_op
= aco_opcode::v_cvt_pk_u16_u32
;
10007 if (is_int8
|| is_int10
) {
10009 uint32_t max_rgb
= is_int8
? 255 : is_int10
? 1023 : 0;
10010 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10012 for (unsigned i
= 0; i
< 4; i
++) {
10013 if ((write_mask
>> i
) & 1) {
10014 values
[i
] = bld
.vop2(aco_opcode::v_min_u32
, bld
.def(v1
),
10015 i
== 3 && is_int10
? Operand(3u) : Operand(max_rgb_val
),
10019 } else if (is_16bit
) {
10020 for (unsigned i
= 0; i
< 4; i
++) {
10021 if ((write_mask
>> i
) & 1) {
10022 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, false);
10023 values
[i
] = Operand(tmp
);
10030 case V_028714_SPI_SHADER_SINT16_ABGR
:
10031 enabled_channels
= 0x5;
10032 compr_op
= aco_opcode::v_cvt_pk_i16_i32
;
10033 if (is_int8
|| is_int10
) {
10035 uint32_t max_rgb
= is_int8
? 127 : is_int10
? 511 : 0;
10036 uint32_t min_rgb
= is_int8
? -128 :is_int10
? -512 : 0;
10037 Temp max_rgb_val
= bld
.copy(bld
.def(s1
), Operand(max_rgb
));
10038 Temp min_rgb_val
= bld
.copy(bld
.def(s1
), Operand(min_rgb
));
10040 for (unsigned i
= 0; i
< 4; i
++) {
10041 if ((write_mask
>> i
) & 1) {
10042 values
[i
] = bld
.vop2(aco_opcode::v_min_i32
, bld
.def(v1
),
10043 i
== 3 && is_int10
? Operand(1u) : Operand(max_rgb_val
),
10045 values
[i
] = bld
.vop2(aco_opcode::v_max_i32
, bld
.def(v1
),
10046 i
== 3 && is_int10
? Operand(-2u) : Operand(min_rgb_val
),
10050 } else if (is_16bit
) {
10051 for (unsigned i
= 0; i
< 4; i
++) {
10052 if ((write_mask
>> i
) & 1) {
10053 Temp tmp
= convert_int(ctx
, bld
, values
[i
].getTemp(), 16, 32, true);
10054 values
[i
] = Operand(tmp
);
10060 case V_028714_SPI_SHADER_32_ABGR
:
10061 enabled_channels
= 0xF;
10068 if (target
== V_008DFC_SQ_EXP_NULL
)
10071 /* Replace NaN by zero (only 32-bit) to fix game bugs if requested. */
10072 if (ctx
->options
->enable_mrt_output_nan_fixup
&&
10074 (col_format
== V_028714_SPI_SHADER_32_R
||
10075 col_format
== V_028714_SPI_SHADER_32_GR
||
10076 col_format
== V_028714_SPI_SHADER_32_AR
||
10077 col_format
== V_028714_SPI_SHADER_32_ABGR
||
10078 col_format
== V_028714_SPI_SHADER_FP16_ABGR
)) {
10079 for (int i
= 0; i
< 4; i
++) {
10080 if (!(write_mask
& (1 << i
)))
10083 Temp isnan
= bld
.vopc(aco_opcode::v_cmp_class_f32
,
10084 bld
.hint_vcc(bld
.def(bld
.lm
)), values
[i
],
10085 bld
.copy(bld
.def(v1
), Operand(3u)));
10086 values
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
), values
[i
],
10087 bld
.copy(bld
.def(v1
), Operand(0u)), isnan
);
10091 if ((bool) compr_op
) {
10092 for (int i
= 0; i
< 2; i
++) {
10093 /* check if at least one of the values to be compressed is enabled */
10094 unsigned enabled
= (write_mask
>> (i
*2) | write_mask
>> (i
*2+1)) & 0x1;
10096 enabled_channels
|= enabled
<< (i
*2);
10097 values
[i
] = bld
.vop3(compr_op
, bld
.def(v1
),
10098 values
[i
*2].isUndefined() ? Operand(0u) : values
[i
*2],
10099 values
[i
*2+1].isUndefined() ? Operand(0u): values
[i
*2+1]);
10101 values
[i
] = Operand(v1
);
10104 values
[2] = Operand(v1
);
10105 values
[3] = Operand(v1
);
10107 for (int i
= 0; i
< 4; i
++)
10108 values
[i
] = enabled_channels
& (1 << i
) ? values
[i
] : Operand(v1
);
10111 bld
.exp(aco_opcode::exp
, values
[0], values
[1], values
[2], values
[3],
10112 enabled_channels
, target
, (bool) compr_op
);
10116 static void create_fs_exports(isel_context
*ctx
)
10118 bool exported
= false;
10120 /* Export depth, stencil and sample mask. */
10121 if (ctx
->outputs
.mask
[FRAG_RESULT_DEPTH
] ||
10122 ctx
->outputs
.mask
[FRAG_RESULT_STENCIL
] ||
10123 ctx
->outputs
.mask
[FRAG_RESULT_SAMPLE_MASK
])
10124 exported
|= export_fs_mrt_z(ctx
);
10126 /* Export all color render targets. */
10127 for (unsigned i
= FRAG_RESULT_DATA0
; i
< FRAG_RESULT_DATA7
+ 1; ++i
)
10128 if (ctx
->outputs
.mask
[i
])
10129 exported
|= export_fs_mrt_color(ctx
, i
);
10132 create_null_export(ctx
);
10135 static void create_workgroup_barrier(Builder
& bld
)
10137 bld
.barrier(aco_opcode::p_barrier
,
10138 memory_sync_info(storage_shared
, semantic_acqrel
, scope_workgroup
),
10142 static void write_tcs_tess_factors(isel_context
*ctx
)
10144 unsigned outer_comps
;
10145 unsigned inner_comps
;
10147 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
10164 Builder
bld(ctx
->program
, ctx
->block
);
10166 create_workgroup_barrier(bld
);
10168 Temp tcs_rel_ids
= get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
);
10169 Temp invocation_id
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), tcs_rel_ids
, Operand(8u), Operand(5u));
10171 Temp invocation_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), invocation_id
);
10172 if_context ic_invocation_id_is_zero
;
10173 begin_divergent_if_then(ctx
, &ic_invocation_id_is_zero
, invocation_id_is_zero
);
10174 bld
.reset(ctx
->block
);
10176 Temp hs_ring_tess_factor
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_FACTOR
* 16u));
10178 std::pair
<Temp
, unsigned> lds_base
= get_tcs_output_lds_offset(ctx
);
10179 unsigned stride
= inner_comps
+ outer_comps
;
10180 unsigned lds_align
= calculate_lds_alignment(ctx
, lds_base
.second
);
10184 assert(stride
<= (sizeof(out
) / sizeof(Temp
)));
10186 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
10188 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(v2
), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10189 out
[1] = emit_extract_vector(ctx
, tf_outer_vec
, 0, v1
);
10190 out
[0] = emit_extract_vector(ctx
, tf_outer_vec
, 1, v1
);
10192 tf_outer_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, outer_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_out_loc
, lds_align
);
10193 tf_inner_vec
= load_lds(ctx
, 4, bld
.tmp(RegClass(RegType::vgpr
, inner_comps
)), lds_base
.first
, lds_base
.second
+ ctx
->tcs_tess_lvl_in_loc
, lds_align
);
10195 for (unsigned i
= 0; i
< outer_comps
; ++i
)
10196 out
[i
] = emit_extract_vector(ctx
, tf_outer_vec
, i
, v1
);
10197 for (unsigned i
= 0; i
< inner_comps
; ++i
)
10198 out
[outer_comps
+ i
] = emit_extract_vector(ctx
, tf_inner_vec
, i
, v1
);
10201 Temp rel_patch_id
= get_tess_rel_patch_id(ctx
);
10202 Temp tf_base
= get_arg(ctx
, ctx
->args
->tess_factor_offset
);
10203 Temp byte_offset
= bld
.v_mul24_imm(bld
.def(v1
), rel_patch_id
, stride
* 4u);
10204 unsigned tf_const_offset
= 0;
10206 if (ctx
->program
->chip_class
<= GFX8
) {
10207 Temp rel_patch_id_is_zero
= bld
.vopc(aco_opcode::v_cmp_eq_u32
, bld
.hint_vcc(bld
.def(bld
.lm
)), Operand(0u), rel_patch_id
);
10208 if_context ic_rel_patch_id_is_zero
;
10209 begin_divergent_if_then(ctx
, &ic_rel_patch_id_is_zero
, rel_patch_id_is_zero
);
10210 bld
.reset(ctx
->block
);
10212 /* Store the dynamic HS control word. */
10213 Temp control_word
= bld
.copy(bld
.def(v1
), Operand(0x80000000u
));
10214 bld
.mubuf(aco_opcode::buffer_store_dword
,
10215 /* SRSRC */ hs_ring_tess_factor
, /* VADDR */ Operand(v1
), /* SOFFSET */ tf_base
, /* VDATA */ control_word
,
10216 /* immediate OFFSET */ 0, /* OFFEN */ false, /* swizzled */ false, /* idxen*/ false,
10217 /* addr64 */ false, /* disable_wqm */ false, /* glc */ true);
10218 tf_const_offset
+= 4;
10220 begin_divergent_if_else(ctx
, &ic_rel_patch_id_is_zero
);
10221 end_divergent_if(ctx
, &ic_rel_patch_id_is_zero
);
10222 bld
.reset(ctx
->block
);
10225 assert(stride
== 2 || stride
== 4 || stride
== 6);
10226 Temp tf_vec
= create_vec_from_array(ctx
, out
, stride
, RegType::vgpr
, 4u);
10227 store_vmem_mubuf(ctx
, tf_vec
, hs_ring_tess_factor
, byte_offset
, tf_base
, tf_const_offset
, 4, (1 << stride
) - 1, true, memory_sync_info());
10229 /* Store to offchip for TES to read - only if TES reads them */
10230 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
10231 Temp hs_ring_tess_offchip
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), ctx
->program
->private_segment_buffer
, Operand(RING_HS_TESS_OFFCHIP
* 16u));
10232 Temp oc_lds
= get_arg(ctx
, ctx
->args
->oc_lds
);
10234 std::pair
<Temp
, unsigned> vmem_offs_outer
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_out_loc
);
10235 store_vmem_mubuf(ctx
, tf_outer_vec
, hs_ring_tess_offchip
, vmem_offs_outer
.first
, oc_lds
, vmem_offs_outer
.second
, 4, (1 << outer_comps
) - 1, true, memory_sync_info(storage_vmem_output
));
10237 if (likely(inner_comps
)) {
10238 std::pair
<Temp
, unsigned> vmem_offs_inner
= get_tcs_per_patch_output_vmem_offset(ctx
, nullptr, ctx
->tcs_tess_lvl_in_loc
);
10239 store_vmem_mubuf(ctx
, tf_inner_vec
, hs_ring_tess_offchip
, vmem_offs_inner
.first
, oc_lds
, vmem_offs_inner
.second
, 4, (1 << inner_comps
) - 1, true, memory_sync_info(storage_vmem_output
));
10243 begin_divergent_if_else(ctx
, &ic_invocation_id_is_zero
);
10244 end_divergent_if(ctx
, &ic_invocation_id_is_zero
);
10247 static void emit_stream_output(isel_context
*ctx
,
10248 Temp
const *so_buffers
,
10249 Temp
const *so_write_offset
,
10250 const struct radv_stream_output
*output
)
10252 unsigned num_comps
= util_bitcount(output
->component_mask
);
10253 unsigned writemask
= (1 << num_comps
) - 1;
10254 unsigned loc
= output
->location
;
10255 unsigned buf
= output
->buffer
;
10257 assert(num_comps
&& num_comps
<= 4);
10258 if (!num_comps
|| num_comps
> 4)
10261 unsigned start
= ffs(output
->component_mask
) - 1;
10264 bool all_undef
= true;
10265 assert(ctx
->stage
& hw_vs
);
10266 for (unsigned i
= 0; i
< num_comps
; i
++) {
10267 out
[i
] = ctx
->outputs
.temps
[loc
* 4 + start
+ i
];
10268 all_undef
= all_undef
&& !out
[i
].id();
10273 while (writemask
) {
10275 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
10276 if (count
== 3 && ctx
->options
->chip_class
== GFX6
) {
10277 /* GFX6 doesn't support storing vec3, split it. */
10278 writemask
|= 1u << (start
+ 2);
10282 unsigned offset
= output
->offset
+ start
* 4;
10284 Temp write_data
= {ctx
->program
->allocateId(), RegClass(RegType::vgpr
, count
)};
10285 aco_ptr
<Pseudo_instruction
> vec
{create_instruction
<Pseudo_instruction
>(aco_opcode::p_create_vector
, Format::PSEUDO
, count
, 1)};
10286 for (int i
= 0; i
< count
; ++i
)
10287 vec
->operands
[i
] = (ctx
->outputs
.mask
[loc
] & 1 << (start
+ i
)) ? Operand(out
[start
+ i
]) : Operand(0u);
10288 vec
->definitions
[0] = Definition(write_data
);
10289 ctx
->block
->instructions
.emplace_back(std::move(vec
));
10294 opcode
= aco_opcode::buffer_store_dword
;
10297 opcode
= aco_opcode::buffer_store_dwordx2
;
10300 opcode
= aco_opcode::buffer_store_dwordx3
;
10303 opcode
= aco_opcode::buffer_store_dwordx4
;
10306 unreachable("Unsupported dword count.");
10309 aco_ptr
<MUBUF_instruction
> store
{create_instruction
<MUBUF_instruction
>(opcode
, Format::MUBUF
, 4, 0)};
10310 store
->operands
[0] = Operand(so_buffers
[buf
]);
10311 store
->operands
[1] = Operand(so_write_offset
[buf
]);
10312 store
->operands
[2] = Operand((uint32_t) 0);
10313 store
->operands
[3] = Operand(write_data
);
10314 if (offset
> 4095) {
10315 /* Don't think this can happen in RADV, but maybe GL? It's easy to do this anyway. */
10316 Builder
bld(ctx
->program
, ctx
->block
);
10317 store
->operands
[0] = bld
.vadd32(bld
.def(v1
), Operand(offset
), Operand(so_write_offset
[buf
]));
10319 store
->offset
= offset
;
10321 store
->offen
= true;
10323 store
->dlc
= false;
10325 ctx
->block
->instructions
.emplace_back(std::move(store
));
10329 static void emit_streamout(isel_context
*ctx
, unsigned stream
)
10331 Builder
bld(ctx
->program
, ctx
->block
);
10333 Temp so_buffers
[4];
10334 Temp buf_ptr
= convert_pointer_to_64_bit(ctx
, get_arg(ctx
, ctx
->args
->streamout_buffers
));
10335 for (unsigned i
= 0; i
< 4; i
++) {
10336 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10340 Operand off
= bld
.copy(bld
.def(s1
), Operand(i
* 16u));
10341 so_buffers
[i
] = bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), buf_ptr
, off
);
10344 Temp so_vtx_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10345 get_arg(ctx
, ctx
->args
->streamout_config
), Operand(0x70010u
));
10347 Temp tid
= emit_mbcnt(ctx
, bld
.def(v1
));
10349 Temp can_emit
= bld
.vopc(aco_opcode::v_cmp_gt_i32
, bld
.def(bld
.lm
), so_vtx_count
, tid
);
10352 begin_divergent_if_then(ctx
, &ic
, can_emit
);
10354 bld
.reset(ctx
->block
);
10356 Temp so_write_index
= bld
.vadd32(bld
.def(v1
), get_arg(ctx
, ctx
->args
->streamout_write_idx
), tid
);
10358 Temp so_write_offset
[4];
10360 for (unsigned i
= 0; i
< 4; i
++) {
10361 unsigned stride
= ctx
->program
->info
->so
.strides
[i
];
10366 Temp offset
= bld
.sop2(aco_opcode::s_add_i32
, bld
.def(s1
), bld
.def(s1
, scc
),
10367 get_arg(ctx
, ctx
->args
->streamout_write_idx
),
10368 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10369 Temp new_offset
= bld
.vadd32(bld
.def(v1
), offset
, tid
);
10371 so_write_offset
[i
] = bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), new_offset
);
10373 Temp offset
= bld
.v_mul_imm(bld
.def(v1
), so_write_index
, stride
* 4u);
10374 Temp offset2
= bld
.sop2(aco_opcode::s_mul_i32
, bld
.def(s1
), Operand(4u),
10375 get_arg(ctx
, ctx
->args
->streamout_offset
[i
]));
10376 so_write_offset
[i
] = bld
.vadd32(bld
.def(v1
), offset
, offset2
);
10380 for (unsigned i
= 0; i
< ctx
->program
->info
->so
.num_outputs
; i
++) {
10381 struct radv_stream_output
*output
=
10382 &ctx
->program
->info
->so
.outputs
[i
];
10383 if (stream
!= output
->stream
)
10386 emit_stream_output(ctx
, so_buffers
, so_write_offset
, output
);
10389 begin_divergent_if_else(ctx
, &ic
);
10390 end_divergent_if(ctx
, &ic
);
10393 } /* end namespace */
10395 void fix_ls_vgpr_init_bug(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10397 assert(ctx
->shader
->info
.stage
== MESA_SHADER_VERTEX
);
10398 Builder
bld(ctx
->program
, ctx
->block
);
10399 constexpr unsigned hs_idx
= 1u;
10400 Builder::Result hs_thread_count
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10401 get_arg(ctx
, ctx
->args
->merged_wave_info
),
10402 Operand((8u << 16) | (hs_idx
* 8u)));
10403 Temp ls_has_nonzero_hs_threads
= bool_to_vector_condition(ctx
, hs_thread_count
.def(1).getTemp());
10405 /* If there are no HS threads, SPI mistakenly loads the LS VGPRs starting at VGPR 0. */
10407 Temp instance_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10408 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10409 get_arg(ctx
, ctx
->args
->ac
.instance_id
),
10410 ls_has_nonzero_hs_threads
);
10411 Temp rel_auto_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10412 get_arg(ctx
, ctx
->args
->ac
.tcs_rel_ids
),
10413 get_arg(ctx
, ctx
->args
->rel_auto_id
),
10414 ls_has_nonzero_hs_threads
);
10415 Temp vertex_id
= bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10416 get_arg(ctx
, ctx
->args
->ac
.tcs_patch_id
),
10417 get_arg(ctx
, ctx
->args
->ac
.vertex_id
),
10418 ls_has_nonzero_hs_threads
);
10420 ctx
->arg_temps
[ctx
->args
->ac
.instance_id
.arg_index
] = instance_id
;
10421 ctx
->arg_temps
[ctx
->args
->rel_auto_id
.arg_index
] = rel_auto_id
;
10422 ctx
->arg_temps
[ctx
->args
->ac
.vertex_id
.arg_index
] = vertex_id
;
10425 void split_arguments(isel_context
*ctx
, Pseudo_instruction
*startpgm
)
10427 /* Split all arguments except for the first (ring_offsets) and the last
10428 * (exec) so that the dead channels don't stay live throughout the program.
10430 for (int i
= 1; i
< startpgm
->definitions
.size() - 1; i
++) {
10431 if (startpgm
->definitions
[i
].regClass().size() > 1) {
10432 emit_split_vector(ctx
, startpgm
->definitions
[i
].getTemp(),
10433 startpgm
->definitions
[i
].regClass().size());
10438 void handle_bc_optimize(isel_context
*ctx
)
10440 /* needed when SPI_PS_IN_CONTROL.BC_OPTIMIZE_DISABLE is set to 0 */
10441 Builder
bld(ctx
->program
, ctx
->block
);
10442 uint32_t spi_ps_input_ena
= ctx
->program
->config
->spi_ps_input_ena
;
10443 bool uses_center
= G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena
);
10444 bool uses_centroid
= G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
) || G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
);
10445 ctx
->persp_centroid
= get_arg(ctx
, ctx
->args
->ac
.persp_centroid
);
10446 ctx
->linear_centroid
= get_arg(ctx
, ctx
->args
->ac
.linear_centroid
);
10447 if (uses_center
&& uses_centroid
) {
10448 Temp sel
= bld
.vopc_e64(aco_opcode::v_cmp_lt_i32
, bld
.hint_vcc(bld
.def(bld
.lm
)),
10449 get_arg(ctx
, ctx
->args
->ac
.prim_mask
), Operand(0u));
10451 if (G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena
)) {
10453 for (unsigned i
= 0; i
< 2; i
++) {
10454 Temp persp_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_centroid
), i
, v1
);
10455 Temp persp_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.persp_center
), i
, v1
);
10456 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10457 persp_centroid
, persp_center
, sel
);
10459 ctx
->persp_centroid
= bld
.tmp(v2
);
10460 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->persp_centroid
),
10461 Operand(new_coord
[0]), Operand(new_coord
[1]));
10462 emit_split_vector(ctx
, ctx
->persp_centroid
, 2);
10465 if (G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena
)) {
10467 for (unsigned i
= 0; i
< 2; i
++) {
10468 Temp linear_centroid
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_centroid
), i
, v1
);
10469 Temp linear_center
= emit_extract_vector(ctx
, get_arg(ctx
, ctx
->args
->ac
.linear_center
), i
, v1
);
10470 new_coord
[i
] = bld
.vop2(aco_opcode::v_cndmask_b32
, bld
.def(v1
),
10471 linear_centroid
, linear_center
, sel
);
10473 ctx
->linear_centroid
= bld
.tmp(v2
);
10474 bld
.pseudo(aco_opcode::p_create_vector
, Definition(ctx
->linear_centroid
),
10475 Operand(new_coord
[0]), Operand(new_coord
[1]));
10476 emit_split_vector(ctx
, ctx
->linear_centroid
, 2);
10481 void setup_fp_mode(isel_context
*ctx
, nir_shader
*shader
)
10483 Program
*program
= ctx
->program
;
10485 unsigned float_controls
= shader
->info
.float_controls_execution_mode
;
10487 program
->next_fp_mode
.preserve_signed_zero_inf_nan32
=
10488 float_controls
& FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP32
;
10489 program
->next_fp_mode
.preserve_signed_zero_inf_nan16_64
=
10490 float_controls
& (FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP16
|
10491 FLOAT_CONTROLS_SIGNED_ZERO_INF_NAN_PRESERVE_FP64
);
10493 program
->next_fp_mode
.must_flush_denorms32
=
10494 float_controls
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
;
10495 program
->next_fp_mode
.must_flush_denorms16_64
=
10496 float_controls
& (FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16
|
10497 FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP64
);
10499 program
->next_fp_mode
.care_about_round32
=
10500 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP32
);
10502 program
->next_fp_mode
.care_about_round16_64
=
10503 float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
|
10504 FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTE_FP64
);
10506 /* default to preserving fp16 and fp64 denorms, since it's free for fp64 and
10507 * the precision seems needed for Wolfenstein: Youngblood to render correctly */
10508 if (program
->next_fp_mode
.must_flush_denorms16_64
)
10509 program
->next_fp_mode
.denorm16_64
= 0;
10511 program
->next_fp_mode
.denorm16_64
= fp_denorm_keep
;
10513 /* preserving fp32 denorms is expensive, so only do it if asked */
10514 if (float_controls
& FLOAT_CONTROLS_DENORM_PRESERVE_FP32
)
10515 program
->next_fp_mode
.denorm32
= fp_denorm_keep
;
10517 program
->next_fp_mode
.denorm32
= 0;
10519 if (float_controls
& FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP32
)
10520 program
->next_fp_mode
.round32
= fp_round_tz
;
10522 program
->next_fp_mode
.round32
= fp_round_ne
;
10524 if (float_controls
& (FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16
| FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP64
))
10525 program
->next_fp_mode
.round16_64
= fp_round_tz
;
10527 program
->next_fp_mode
.round16_64
= fp_round_ne
;
10529 ctx
->block
->fp_mode
= program
->next_fp_mode
;
10532 void cleanup_cfg(Program
*program
)
10534 /* create linear_succs/logical_succs */
10535 for (Block
& BB
: program
->blocks
) {
10536 for (unsigned idx
: BB
.linear_preds
)
10537 program
->blocks
[idx
].linear_succs
.emplace_back(BB
.index
);
10538 for (unsigned idx
: BB
.logical_preds
)
10539 program
->blocks
[idx
].logical_succs
.emplace_back(BB
.index
);
10543 Temp
merged_wave_info_to_mask(isel_context
*ctx
, unsigned i
)
10545 Builder
bld(ctx
->program
, ctx
->block
);
10547 /* The s_bfm only cares about s0.u[5:0] so we don't need either s_bfe nor s_and here */
10548 Temp count
= i
== 0
10549 ? get_arg(ctx
, ctx
->args
->merged_wave_info
)
10550 : bld
.sop2(aco_opcode::s_lshr_b32
, bld
.def(s1
), bld
.def(s1
, scc
),
10551 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(i
* 8u));
10553 Temp mask
= bld
.sop2(aco_opcode::s_bfm_b64
, bld
.def(s2
), count
, Operand(0u));
10556 if (ctx
->program
->wave_size
== 64) {
10557 /* Special case for 64 active invocations, because 64 doesn't work with s_bfm */
10558 Temp active_64
= bld
.sopc(aco_opcode::s_bitcmp1_b32
, bld
.def(s1
, scc
), count
, Operand(6u /* log2(64) */));
10559 cond
= bld
.sop2(Builder::s_cselect
, bld
.def(bld
.lm
), Operand(-1u), mask
, bld
.scc(active_64
));
10561 /* We use s_bfm_b64 (not _b32) which works with 32, but we need to extract the lower half of the register */
10562 cond
= emit_extract_vector(ctx
, mask
, 0, bld
.lm
);
10568 bool ngg_early_prim_export(isel_context
*ctx
)
10570 /* TODO: Check edge flags, and if they are written, return false. (Needed for OpenGL, not for Vulkan.) */
10574 void ngg_emit_sendmsg_gs_alloc_req(isel_context
*ctx
)
10576 Builder
bld(ctx
->program
, ctx
->block
);
10578 /* It is recommended to do the GS_ALLOC_REQ as soon and as quickly as possible, so we set the maximum priority (3). */
10579 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x3u
);
10581 /* Get the id of the current wave within the threadgroup (workgroup) */
10582 Builder::Result wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10583 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10585 /* Execute the following code only on the first wave (wave id 0),
10586 * use the SCC def to tell if the wave id is zero or not.
10588 Temp cond
= wave_id_in_tg
.def(1).getTemp();
10590 begin_uniform_if_then(ctx
, &ic
, cond
);
10591 begin_uniform_if_else(ctx
, &ic
);
10592 bld
.reset(ctx
->block
);
10594 /* Number of vertices output by VS/TES */
10595 Temp vtx_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10596 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(12u | (9u << 16u)));
10597 /* Number of primitives output by VS/TES */
10598 Temp prm_cnt
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10599 get_arg(ctx
, ctx
->args
->gs_tg_info
), Operand(22u | (9u << 16u)));
10601 /* Put the number of vertices and primitives into m0 for the GS_ALLOC_REQ */
10602 Temp tmp
= bld
.sop2(aco_opcode::s_lshl_b32
, bld
.def(s1
), bld
.def(s1
, scc
), prm_cnt
, Operand(12u));
10603 tmp
= bld
.sop2(aco_opcode::s_or_b32
, bld
.m0(bld
.def(s1
)), bld
.def(s1
, scc
), tmp
, vtx_cnt
);
10605 /* Request the SPI to allocate space for the primitives and vertices that will be exported by the threadgroup. */
10606 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(tmp
), -1, sendmsg_gs_alloc_req
);
10608 end_uniform_if(ctx
, &ic
);
10610 /* After the GS_ALLOC_REQ is done, reset priority to default (0). */
10611 bld
.reset(ctx
->block
);
10612 bld
.sopp(aco_opcode::s_setprio
, -1u, 0x0u
);
10615 Temp
ngg_get_prim_exp_arg(isel_context
*ctx
, unsigned num_vertices
, const Temp vtxindex
[])
10617 Builder
bld(ctx
->program
, ctx
->block
);
10619 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
10620 return get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]);
10623 Temp gs_invocation_id
= get_arg(ctx
, ctx
->args
->ac
.gs_invocation_id
);
10626 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
10627 assert(vtxindex
[i
].id());
10630 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), vtxindex
[i
], Operand(10u * i
), tmp
);
10634 /* The initial edge flag is always false in tess eval shaders. */
10635 if (ctx
->stage
== ngg_vertex_gs
) {
10636 Temp edgeflag
= bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
), gs_invocation_id
, Operand(8 + i
), Operand(1u));
10637 tmp
= bld
.vop3(aco_opcode::v_lshl_add_u32
, bld
.def(v1
), edgeflag
, Operand(10u * i
+ 9u), tmp
);
10641 /* TODO: Set isnull field in case of merged NGG VS+GS. */
10646 void ngg_emit_prim_export(isel_context
*ctx
, unsigned num_vertices_per_primitive
, const Temp vtxindex
[])
10648 Builder
bld(ctx
->program
, ctx
->block
);
10649 Temp prim_exp_arg
= ngg_get_prim_exp_arg(ctx
, num_vertices_per_primitive
, vtxindex
);
10651 bld
.exp(aco_opcode::exp
, prim_exp_arg
, Operand(v1
), Operand(v1
), Operand(v1
),
10652 1 /* enabled mask */, V_008DFC_SQ_EXP_PRIM
/* dest */,
10653 false /* compressed */, true/* done */, false /* valid mask */);
10656 void ngg_emit_nogs_gsthreads(isel_context
*ctx
)
10658 /* Emit the things that NGG GS threads need to do, for shaders that don't have SW GS.
10659 * These must always come before VS exports.
10661 * It is recommended to do these as early as possible. They can be at the beginning when
10662 * there is no SW GS and the shader doesn't write edge flags.
10666 Temp is_gs_thread
= merged_wave_info_to_mask(ctx
, 1);
10667 begin_divergent_if_then(ctx
, &ic
, is_gs_thread
);
10669 Builder
bld(ctx
->program
, ctx
->block
);
10670 constexpr unsigned max_vertices_per_primitive
= 3;
10671 unsigned num_vertices_per_primitive
= max_vertices_per_primitive
;
10673 if (ctx
->stage
== ngg_vertex_gs
) {
10674 /* TODO: optimize for points & lines */
10675 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10676 if (ctx
->shader
->info
.tess
.point_mode
)
10677 num_vertices_per_primitive
= 1;
10678 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
10679 num_vertices_per_primitive
= 2;
10681 unreachable("Unsupported NGG shader stage");
10684 Temp vtxindex
[max_vertices_per_primitive
];
10685 vtxindex
[0] = bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10686 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]));
10687 vtxindex
[1] = num_vertices_per_primitive
< 2 ? Temp(0, v1
) :
10688 bld
.vop3(aco_opcode::v_bfe_u32
, bld
.def(v1
),
10689 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[0]), Operand(16u), Operand(16u));
10690 vtxindex
[2] = num_vertices_per_primitive
< 3 ? Temp(0, v1
) :
10691 bld
.vop2(aco_opcode::v_and_b32
, bld
.def(v1
), Operand(0xffffu
),
10692 get_arg(ctx
, ctx
->args
->gs_vtx_offset
[2]));
10694 /* Export primitive data to the index buffer. */
10695 ngg_emit_prim_export(ctx
, num_vertices_per_primitive
, vtxindex
);
10697 /* Export primitive ID. */
10698 if (ctx
->stage
== ngg_vertex_gs
&& ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10699 /* Copy Primitive IDs from GS threads to the LDS address corresponding to the ES thread of the provoking vertex. */
10700 Temp prim_id
= get_arg(ctx
, ctx
->args
->ac
.gs_prim_id
);
10701 Temp provoking_vtx_index
= vtxindex
[0];
10702 Temp addr
= bld
.v_mul_imm(bld
.def(v1
), provoking_vtx_index
, 4u);
10704 store_lds(ctx
, 4, prim_id
, 0x1u
, addr
, 0u, 4u);
10707 begin_divergent_if_else(ctx
, &ic
);
10708 end_divergent_if(ctx
, &ic
);
10711 void ngg_emit_nogs_output(isel_context
*ctx
)
10713 /* Emits NGG GS output, for stages that don't have SW GS. */
10716 Builder
bld(ctx
->program
, ctx
->block
);
10717 bool late_prim_export
= !ngg_early_prim_export(ctx
);
10719 /* NGG streamout is currently disabled by default. */
10720 assert(!ctx
->args
->shader_info
->so
.num_outputs
);
10722 if (late_prim_export
) {
10723 /* VS exports are output to registers in a predecessor block. Emit phis to get them into this block. */
10724 create_export_phis(ctx
);
10725 /* Do what we need to do in the GS threads. */
10726 ngg_emit_nogs_gsthreads(ctx
);
10728 /* What comes next should be executed on ES threads. */
10729 Temp is_es_thread
= merged_wave_info_to_mask(ctx
, 0);
10730 begin_divergent_if_then(ctx
, &ic
, is_es_thread
);
10731 bld
.reset(ctx
->block
);
10734 /* Export VS outputs */
10735 ctx
->block
->kind
|= block_kind_export_end
;
10736 create_vs_exports(ctx
);
10738 /* Export primitive ID */
10739 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
10742 if (ctx
->stage
== ngg_vertex_gs
) {
10743 /* Wait for GS threads to store primitive ID in LDS. */
10744 create_workgroup_barrier(bld
);
10746 /* Calculate LDS address where the GS threads stored the primitive ID. */
10747 Temp wave_id_in_tg
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10748 get_arg(ctx
, ctx
->args
->merged_wave_info
), Operand(24u | (4u << 16)));
10749 Temp thread_id_in_wave
= emit_mbcnt(ctx
, bld
.def(v1
));
10750 Temp wave_id_mul
= bld
.v_mul24_imm(bld
.def(v1
), as_vgpr(ctx
, wave_id_in_tg
), ctx
->program
->wave_size
);
10751 Temp thread_id_in_tg
= bld
.vadd32(bld
.def(v1
), Operand(wave_id_mul
), Operand(thread_id_in_wave
));
10752 Temp addr
= bld
.v_mul24_imm(bld
.def(v1
), thread_id_in_tg
, 4u);
10754 /* Load primitive ID from LDS. */
10755 prim_id
= load_lds(ctx
, 4, bld
.tmp(v1
), addr
, 0u, 4u);
10756 } else if (ctx
->stage
== ngg_tess_eval_gs
) {
10757 /* TES: Just use the patch ID as the primitive ID. */
10758 prim_id
= get_arg(ctx
, ctx
->args
->ac
.tes_patch_id
);
10760 unreachable("unsupported NGG shader stage.");
10763 ctx
->outputs
.mask
[VARYING_SLOT_PRIMITIVE_ID
] |= 0x1;
10764 ctx
->outputs
.temps
[VARYING_SLOT_PRIMITIVE_ID
* 4u] = prim_id
;
10766 export_vs_varying(ctx
, VARYING_SLOT_PRIMITIVE_ID
, false, nullptr);
10769 if (late_prim_export
) {
10770 begin_divergent_if_else(ctx
, &ic
);
10771 end_divergent_if(ctx
, &ic
);
10772 bld
.reset(ctx
->block
);
10776 void select_program(Program
*program
,
10777 unsigned shader_count
,
10778 struct nir_shader
*const *shaders
,
10779 ac_shader_config
* config
,
10780 struct radv_shader_args
*args
)
10782 isel_context ctx
= setup_isel_context(program
, shader_count
, shaders
, config
, args
, false);
10783 if_context ic_merged_wave_info
;
10784 bool ngg_no_gs
= ctx
.stage
== ngg_vertex_gs
|| ctx
.stage
== ngg_tess_eval_gs
;
10786 for (unsigned i
= 0; i
< shader_count
; i
++) {
10787 nir_shader
*nir
= shaders
[i
];
10788 init_context(&ctx
, nir
);
10790 setup_fp_mode(&ctx
, nir
);
10793 /* needs to be after init_context() for FS */
10794 Pseudo_instruction
*startpgm
= add_startpgm(&ctx
);
10795 append_logical_start(ctx
.block
);
10797 if (unlikely(args
->options
->has_ls_vgpr_init_bug
&& ctx
.stage
== vertex_tess_control_hs
))
10798 fix_ls_vgpr_init_bug(&ctx
, startpgm
);
10800 split_arguments(&ctx
, startpgm
);
10804 ngg_emit_sendmsg_gs_alloc_req(&ctx
);
10806 if (ngg_early_prim_export(&ctx
))
10807 ngg_emit_nogs_gsthreads(&ctx
);
10810 /* In a merged VS+TCS HS, the VS implementation can be completely empty. */
10811 nir_function_impl
*func
= nir_shader_get_entrypoint(nir
);
10812 bool empty_shader
= nir_cf_list_is_empty_block(&func
->body
) &&
10813 ((nir
->info
.stage
== MESA_SHADER_VERTEX
&&
10814 (ctx
.stage
== vertex_tess_control_hs
|| ctx
.stage
== vertex_geometry_gs
)) ||
10815 (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
10816 ctx
.stage
== tess_eval_geometry_gs
));
10818 bool check_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 0 : ((shader_count
>= 2 && !empty_shader
) || ngg_no_gs
);
10819 bool endif_merged_wave_info
= ctx
.tcs_in_out_eq
? i
== 1 : check_merged_wave_info
;
10820 if (check_merged_wave_info
) {
10821 Temp cond
= merged_wave_info_to_mask(&ctx
, i
);
10822 begin_divergent_if_then(&ctx
, &ic_merged_wave_info
, cond
);
10826 Builder
bld(ctx
.program
, ctx
.block
);
10828 create_workgroup_barrier(bld
);
10830 if (ctx
.stage
== vertex_geometry_gs
|| ctx
.stage
== tess_eval_geometry_gs
) {
10831 ctx
.gs_wave_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
, m0
), bld
.def(s1
, scc
), get_arg(&ctx
, args
->merged_wave_info
), Operand((8u << 16) | 16u));
10833 } else if (ctx
.stage
== geometry_gs
)
10834 ctx
.gs_wave_id
= get_arg(&ctx
, args
->gs_wave_id
);
10836 if (ctx
.stage
== fragment_fs
)
10837 handle_bc_optimize(&ctx
);
10839 visit_cf_list(&ctx
, &func
->body
);
10841 if (ctx
.program
->info
->so
.num_outputs
&& (ctx
.stage
& hw_vs
))
10842 emit_streamout(&ctx
, 0);
10844 if (ctx
.stage
& hw_vs
) {
10845 create_vs_exports(&ctx
);
10846 ctx
.block
->kind
|= block_kind_export_end
;
10847 } else if (ngg_no_gs
&& ngg_early_prim_export(&ctx
)) {
10848 ngg_emit_nogs_output(&ctx
);
10849 } else if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
10850 Builder
bld(ctx
.program
, ctx
.block
);
10851 bld
.barrier(aco_opcode::p_barrier
,
10852 memory_sync_info(storage_vmem_output
, semantic_release
, scope_device
));
10853 bld
.sopp(aco_opcode::s_sendmsg
, bld
.m0(ctx
.gs_wave_id
), -1, sendmsg_gs_done(false, false, 0));
10854 } else if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
10855 write_tcs_tess_factors(&ctx
);
10858 if (ctx
.stage
== fragment_fs
) {
10859 create_fs_exports(&ctx
);
10860 ctx
.block
->kind
|= block_kind_export_end
;
10863 if (endif_merged_wave_info
) {
10864 begin_divergent_if_else(&ctx
, &ic_merged_wave_info
);
10865 end_divergent_if(&ctx
, &ic_merged_wave_info
);
10868 if (ngg_no_gs
&& !ngg_early_prim_export(&ctx
))
10869 ngg_emit_nogs_output(&ctx
);
10871 if (i
== 0 && ctx
.stage
== vertex_tess_control_hs
&& ctx
.tcs_in_out_eq
) {
10872 /* Outputs of the previous stage are inputs to the next stage */
10873 ctx
.inputs
= ctx
.outputs
;
10874 ctx
.outputs
= shader_io_state();
10878 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
10880 append_logical_end(ctx
.block
);
10881 ctx
.block
->kind
|= block_kind_uniform
;
10882 Builder
bld(ctx
.program
, ctx
.block
);
10883 if (ctx
.program
->wb_smem_l1_on_end
)
10884 bld
.smem(aco_opcode::s_dcache_wb
, memory_sync_info(storage_buffer
, semantic_volatile
));
10885 bld
.sopp(aco_opcode::s_endpgm
);
10887 cleanup_cfg(program
);
10890 void select_gs_copy_shader(Program
*program
, struct nir_shader
*gs_shader
,
10891 ac_shader_config
* config
,
10892 struct radv_shader_args
*args
)
10894 isel_context ctx
= setup_isel_context(program
, 1, &gs_shader
, config
, args
, true);
10896 ctx
.block
->fp_mode
= program
->next_fp_mode
;
10898 add_startpgm(&ctx
);
10899 append_logical_start(ctx
.block
);
10901 Builder
bld(ctx
.program
, ctx
.block
);
10903 Temp gsvs_ring
= bld
.smem(aco_opcode::s_load_dwordx4
, bld
.def(s4
), program
->private_segment_buffer
, Operand(RING_GSVS_VS
* 16u));
10905 Operand
stream_id(0u);
10906 if (args
->shader_info
->so
.num_outputs
)
10907 stream_id
= bld
.sop2(aco_opcode::s_bfe_u32
, bld
.def(s1
), bld
.def(s1
, scc
),
10908 get_arg(&ctx
, ctx
.args
->streamout_config
), Operand(0x20018u
));
10910 Temp vtx_offset
= bld
.vop2(aco_opcode::v_lshlrev_b32
, bld
.def(v1
), Operand(2u), get_arg(&ctx
, ctx
.args
->ac
.vertex_id
));
10912 std::stack
<Block
> endif_blocks
;
10914 for (unsigned stream
= 0; stream
< 4; stream
++) {
10915 if (stream_id
.isConstant() && stream
!= stream_id
.constantValue())
10918 unsigned num_components
= args
->shader_info
->gs
.num_stream_output_components
[stream
];
10919 if (stream
> 0 && (!num_components
|| !args
->shader_info
->so
.num_outputs
))
10922 memset(ctx
.outputs
.mask
, 0, sizeof(ctx
.outputs
.mask
));
10924 unsigned BB_if_idx
= ctx
.block
->index
;
10925 Block BB_endif
= Block();
10926 if (!stream_id
.isConstant()) {
10928 Temp cond
= bld
.sopc(aco_opcode::s_cmp_eq_u32
, bld
.def(s1
, scc
), stream_id
, Operand(stream
));
10929 append_logical_end(ctx
.block
);
10930 ctx
.block
->kind
|= block_kind_uniform
;
10931 bld
.branch(aco_opcode::p_cbranch_z
, bld
.hint_vcc(bld
.def(s2
)), cond
);
10933 BB_endif
.kind
|= ctx
.block
->kind
& block_kind_top_level
;
10935 ctx
.block
= ctx
.program
->create_and_insert_block();
10936 add_edge(BB_if_idx
, ctx
.block
);
10937 bld
.reset(ctx
.block
);
10938 append_logical_start(ctx
.block
);
10941 unsigned offset
= 0;
10942 for (unsigned i
= 0; i
<= VARYING_SLOT_VAR31
; ++i
) {
10943 if (args
->shader_info
->gs
.output_streams
[i
] != stream
)
10946 unsigned output_usage_mask
= args
->shader_info
->gs
.output_usage_mask
[i
];
10947 unsigned length
= util_last_bit(output_usage_mask
);
10948 for (unsigned j
= 0; j
< length
; ++j
) {
10949 if (!(output_usage_mask
& (1 << j
)))
10952 unsigned const_offset
= offset
* args
->shader_info
->gs
.vertices_out
* 16 * 4;
10953 Temp voffset
= vtx_offset
;
10954 if (const_offset
>= 4096u) {
10955 voffset
= bld
.vadd32(bld
.def(v1
), Operand(const_offset
/ 4096u * 4096u), voffset
);
10956 const_offset
%= 4096u;
10959 aco_ptr
<MUBUF_instruction
> mubuf
{create_instruction
<MUBUF_instruction
>(aco_opcode::buffer_load_dword
, Format::MUBUF
, 3, 1)};
10960 mubuf
->definitions
[0] = bld
.def(v1
);
10961 mubuf
->operands
[0] = Operand(gsvs_ring
);
10962 mubuf
->operands
[1] = Operand(voffset
);
10963 mubuf
->operands
[2] = Operand(0u);
10964 mubuf
->offen
= true;
10965 mubuf
->offset
= const_offset
;
10968 mubuf
->dlc
= args
->options
->chip_class
>= GFX10
;
10970 ctx
.outputs
.mask
[i
] |= 1 << j
;
10971 ctx
.outputs
.temps
[i
* 4u + j
] = mubuf
->definitions
[0].getTemp();
10973 bld
.insert(std::move(mubuf
));
10979 if (args
->shader_info
->so
.num_outputs
) {
10980 emit_streamout(&ctx
, stream
);
10981 bld
.reset(ctx
.block
);
10985 create_vs_exports(&ctx
);
10986 ctx
.block
->kind
|= block_kind_export_end
;
10989 if (!stream_id
.isConstant()) {
10990 append_logical_end(ctx
.block
);
10992 /* branch from then block to endif block */
10993 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
10994 add_edge(ctx
.block
->index
, &BB_endif
);
10995 ctx
.block
->kind
|= block_kind_uniform
;
10997 /* emit else block */
10998 ctx
.block
= ctx
.program
->create_and_insert_block();
10999 add_edge(BB_if_idx
, ctx
.block
);
11000 bld
.reset(ctx
.block
);
11001 append_logical_start(ctx
.block
);
11003 endif_blocks
.push(std::move(BB_endif
));
11007 while (!endif_blocks
.empty()) {
11008 Block BB_endif
= std::move(endif_blocks
.top());
11009 endif_blocks
.pop();
11011 Block
*BB_else
= ctx
.block
;
11013 append_logical_end(BB_else
);
11014 /* branch from else block to endif block */
11015 bld
.branch(aco_opcode::p_branch
, bld
.hint_vcc(bld
.def(s2
)));
11016 add_edge(BB_else
->index
, &BB_endif
);
11017 BB_else
->kind
|= block_kind_uniform
;
11019 /** emit endif merge block */
11020 ctx
.block
= program
->insert_block(std::move(BB_endif
));
11021 bld
.reset(ctx
.block
);
11022 append_logical_start(ctx
.block
);
11025 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11027 append_logical_end(ctx
.block
);
11028 ctx
.block
->kind
|= block_kind_uniform
;
11029 bld
.sopp(aco_opcode::s_endpgm
);
11031 cleanup_cfg(program
);
11034 void select_trap_handler_shader(Program
*program
, struct nir_shader
*shader
,
11035 ac_shader_config
* config
,
11036 struct radv_shader_args
*args
)
11038 assert(args
->options
->chip_class
== GFX8
);
11040 init_program(program
, compute_cs
, args
->shader_info
,
11041 args
->options
->chip_class
, args
->options
->family
, config
);
11043 isel_context ctx
= {};
11044 ctx
.program
= program
;
11046 ctx
.options
= args
->options
;
11047 ctx
.stage
= program
->stage
;
11049 ctx
.block
= ctx
.program
->create_and_insert_block();
11050 ctx
.block
->loop_nest_depth
= 0;
11051 ctx
.block
->kind
= block_kind_top_level
;
11053 program
->workgroup_size
= 1; /* XXX */
11055 add_startpgm(&ctx
);
11056 append_logical_start(ctx
.block
);
11058 Builder
bld(ctx
.program
, ctx
.block
);
11060 /* Load the buffer descriptor from TMA. */
11061 bld
.smem(aco_opcode::s_load_dwordx4
, Definition(PhysReg
{ttmp4
}, s4
),
11062 Operand(PhysReg
{tma
}, s2
), Operand(0u));
11064 /* Store TTMP0-TTMP1. */
11065 bld
.smem(aco_opcode::s_buffer_store_dwordx2
, Operand(PhysReg
{ttmp4
}, s4
),
11066 Operand(0u), Operand(PhysReg
{ttmp0
}, s2
), memory_sync_info(), true);
11068 uint32_t hw_regs_idx
[] = {
11069 2, /* HW_REG_STATUS */
11070 3, /* HW_REG_TRAP_STS */
11071 4, /* HW_REG_HW_ID */
11072 7, /* HW_REG_IB_STS */
11075 /* Store some hardware registers. */
11076 for (unsigned i
= 0; i
< ARRAY_SIZE(hw_regs_idx
); i
++) {
11077 /* "((size - 1) << 11) | register" */
11078 bld
.sopk(aco_opcode::s_getreg_b32
, Definition(PhysReg
{ttmp8
}, s1
),
11079 ((20 - 1) << 11) | hw_regs_idx
[i
]);
11081 bld
.smem(aco_opcode::s_buffer_store_dword
, Operand(PhysReg
{ttmp4
}, s4
),
11082 Operand(8u + i
* 4), Operand(PhysReg
{ttmp8
}, s1
), memory_sync_info(), true);
11085 program
->config
->float_mode
= program
->blocks
[0].fp_mode
.val
;
11087 append_logical_end(ctx
.block
);
11088 ctx
.block
->kind
|= block_kind_uniform
;
11089 bld
.sopp(aco_opcode::s_endpgm
);
11091 cleanup_cfg(program
);