src/bigint_presentation_code/_tests/test_compiler_ir.py

   1 import unittest
   2
   3 from bigint_presentation_code.compiler_ir import (VL, FixedGPRRangeType, Fn,
   4                                                   GlobalMem, GPRRange, GPRType,
   5                                                   OpBigIntAddSub, OpConcat,
   6                                                   OpCopy, OpFuncArg,
   7                                                   OpInputMem, OpLI, OpLoad,
   8                                                   OpSetCA, OpSetVLImm, OpStore,
   9                                                   RegLoc, SSAVal, XERBit,
  10                                                   generate_assembly,
  11                                                   op_set_to_list)
  12 import bigint_presentation_code.compiler_ir2
  13
  14
  15 class TestCompilerIR(unittest.TestCase):
  16     maxDiff = None
  17
  18     def test_op_set_to_list(self):
  19         fn = Fn()
  20         op0 = OpFuncArg(fn, FixedGPRRangeType(GPRRange(3)))
  21         op1 = OpCopy(fn, op0.out, GPRType())
  22         arg = op1.dest
  23         op2 = OpInputMem(fn)
  24         mem = op2.out
  25         op3 = OpSetVLImm(fn, 32)
  26         vl = op3.out
  27         op4 = OpLoad(fn, arg, offset=0, mem=mem, vl=vl)
  28         a = op4.RT
  29         op5 = OpLI(fn, 1)
  30         b_0 = op5.out
  31         op6 = OpSetVLImm(fn, 31)
  32         vl = op6.out
  33         op7 = OpLI(fn, 0, vl=vl)
  34         b_rest = op7.out
  35         op8 = OpConcat(fn, [b_0, b_rest])
  36         b = op8.dest
  37         op9 = OpSetVLImm(fn, 32)
  38         vl = op9.out
  39         op10 = OpSetCA(fn, False)
  40         ca = op10.out
  41         op11 = OpBigIntAddSub(fn, a, b, ca, is_sub=False, vl=vl)
  42         s = op11.out
  43         op12 = OpStore(fn, s, arg, offset=0, mem_in=mem, vl=vl)
  44         mem = op12.mem_out
  45
  46         expected_ops = [
  47             op10,  # OpSetCA(fn, False)
  48             op9,  # OpSetVLImm(fn, 32)
  49             op6,  # OpSetVLImm(fn, 31)
  50             op5,  # OpLI(fn, 1)
  51             op3,  # OpSetVLImm(fn, 32)
  52             op2,  # OpInputMem(fn)
  53             op0,  # OpFuncArg(fn, FixedGPRRangeType(GPRRange(3)))
  54             op7,  # OpLI(fn, 0, vl=vl)
  55             op1,  # OpCopy(fn, op0.out, GPRType())
  56             op8,  # OpConcat(fn, [b_0, b_rest])
  57             op4,  # OpLoad(fn, arg, offset=0, mem=mem, vl=vl)
  58             op11,  # OpBigIntAddSub(fn, a, b, ca, is_sub=False, vl=vl)
  59             op12,  # OpStore(fn, s, arg, offset=0, mem_in=mem, vl=vl)
  60         ]
  61
  62         ops = op_set_to_list(fn.ops[::-1])
  63         if ops != expected_ops:
  64             self.assertEqual(repr(ops), repr(expected_ops))
  65
  66     def tst_generate_assembly(self, use_reg_alloc=False):
  67         fn = Fn()
  68         op0 = OpFuncArg(fn, FixedGPRRangeType(GPRRange(3)))
  69         op1 = OpCopy(fn, op0.out, GPRType())
  70         arg = op1.dest
  71         op2 = OpInputMem(fn)
  72         mem = op2.out
  73         op3 = OpSetVLImm(fn, 32)
  74         vl = op3.out
  75         op4 = OpLoad(fn, arg, offset=0, mem=mem, vl=vl)
  76         a = op4.RT
  77         op5 = OpLI(fn, 0, vl=vl)
  78         b = op5.out
  79         op6 = OpSetCA(fn, True)
  80         ca = op6.out
  81         op7 = OpBigIntAddSub(fn, a, b, ca, is_sub=False, vl=vl)
  82         s = op7.out
  83         op8 = OpStore(fn, s, arg, offset=0, mem_in=mem, vl=vl)
  84         mem = op8.mem_out
  85
  86         assigned_registers = {
  87             op0.out: GPRRange(start=3, length=1),
  88             op1.dest: GPRRange(start=3, length=1),
  89             op2.out: GlobalMem.GlobalMem,
  90             op3.out: VL.VL_MAXVL,
  91             op4.RT: GPRRange(start=78, length=32),
  92             op5.out: GPRRange(start=46, length=32),
  93             op6.out: XERBit.CA,
  94             op7.out: GPRRange(start=14, length=32),
  95             op7.CA_out: XERBit.CA,
  96             op8.mem_out: GlobalMem.GlobalMem,
  97         }  # type: dict[SSAVal, RegLoc] | None
  98
  99         if use_reg_alloc:
 100             assigned_registers = None
 101
 102         asm = generate_assembly(fn.ops, assigned_registers)
 103         self.assertEqual(asm, [
 104             "setvl 0, 0, 32, 0, 1, 1",
 105             "sv.ld *78, 0(3)",
 106             "sv.addi *46, 0, 0",
 107             "subfic 0, 0, -1",
 108             "sv.adde *14, *78, *46",
 109             "sv.std *14, 0(3)",
 110             "bclr 20, 0, 0",
 111         ])
 112
 113     def test_generate_assembly(self):
 114         self.tst_generate_assembly()
 115
 116     def test_generate_assembly_with_register_allocator(self):
 117         self.tst_generate_assembly(use_reg_alloc=True)
 118
 119
 120 if __name__ == "__main__":
 121     unittest.main()