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[bigint-presentation-code.git] / src / bigint_presentation_code / _tests / test_compiler_ir.py
1 import unittest
2
3 from bigint_presentation_code.compiler_ir import (GPR_SIZE_IN_BYTES, BaseTy,
4 Fn, FnAnalysis, GenAsmState,
5 Loc, LocKind, LocSet, OpKind,
6 OpStage, PreRASimState,
7 ProgramPoint, SSAVal, Ty)
8 from bigint_presentation_code.util import OFSet
9
10
11 class TestCompilerIR(unittest.TestCase):
12 maxDiff = None
13
14 def test_program_point(self):
15 # type: () -> None
16 expected = [] # type: list[ProgramPoint]
17 for op_index in range(5):
18 for stage in OpStage:
19 expected.append(ProgramPoint(op_index=op_index, stage=stage))
20
21 for idx, pp in enumerate(expected):
22 if idx + 1 < len(expected):
23 self.assertEqual(pp.next(), expected[idx + 1])
24
25 self.assertEqual(sorted(expected), expected)
26
27 def test_loc_set_hash_intern(self):
28 # type: () -> None
29 # hashes should match all other collections.abc.Set types, which are
30 # supposed to match frozenset but don't until Python 3.11 because of a
31 # bug fixed in:
32 # https://github.com/python/cpython/commit/c878f5d81772dc6f718d6608c78baa4be9a4f176
33 a = LocSet([])
34 self.assertEqual(hash(a), hash(OFSet()))
35 starts = 0, 1, 0, 1, 2
36 GPR = LocKind.GPR
37 expected = OFSet(Loc(kind=GPR, start=i, reg_len=1) for i in starts)
38 b = LocSet(expected)
39 c = LocSet(Loc(kind=GPR, start=i, reg_len=1) for i in starts)
40 d = LocSet(Loc(kind=GPR, start=i, reg_len=1) for i in starts)
41 # hashes should be equal to OFSet's hash
42 self.assertEqual(hash(b), hash(expected))
43 self.assertEqual(hash(c), hash(expected))
44 self.assertEqual(hash(d), hash(expected))
45 # they should intern to the same object
46 self.assertIs(b, d)
47 self.assertIs(c, d)
48
49 def make_add_fn(self):
50 # type: () -> tuple[Fn, SSAVal]
51 fn = Fn()
52 op0 = fn.append_new_op(OpKind.FuncArgR3, name="arg")
53 arg = op0.outputs[0]
54 MAXVL = 32
55 op1 = fn.append_new_op(OpKind.SetVLI, immediates=[MAXVL], name="vl")
56 vl = op1.outputs[0]
57 op2 = fn.append_new_op(
58 OpKind.SvLd, input_vals=[arg, vl], immediates=[0], maxvl=MAXVL,
59 name="ld")
60 a = op2.outputs[0]
61 op3 = fn.append_new_op(OpKind.SvLI, input_vals=[vl], immediates=[0],
62 maxvl=MAXVL, name="li")
63 b = op3.outputs[0]
64 op4 = fn.append_new_op(OpKind.SetCA, name="ca")
65 ca = op4.outputs[0]
66 op5 = fn.append_new_op(
67 OpKind.SvAddE, input_vals=[a, b, ca, vl], maxvl=MAXVL, name="add")
68 s = op5.outputs[0]
69 _ = fn.append_new_op(OpKind.SvStd, input_vals=[s, arg, vl],
70 immediates=[0], maxvl=MAXVL, name="st")
71 return fn, arg
72
73 def test_fn_analysis(self):
74 fn, _arg = self.make_add_fn()
75 fn_analysis = FnAnalysis(fn)
76 self.assertEqual(
77 repr(fn_analysis.uses),
78 "FMap({"
79 "<arg.outputs[0]: <I64>>: OFSet(["
80 "<ld.input_uses[0]: <I64>>, <st.input_uses[1]: <I64>>]), "
81 "<vl.outputs[0]: <VL_MAXVL>>: OFSet(["
82 "<ld.input_uses[1]: <VL_MAXVL>>, <li.input_uses[0]: <VL_MAXVL>>, "
83 "<add.input_uses[3]: <VL_MAXVL>>, "
84 "<st.input_uses[2]: <VL_MAXVL>>]), "
85 "<ld.outputs[0]: <I64*32>>: OFSet(["
86 "<add.input_uses[0]: <I64*32>>]), "
87 "<li.outputs[0]: <I64*32>>: OFSet(["
88 "<add.input_uses[1]: <I64*32>>]), "
89 "<ca.outputs[0]: <CA>>: OFSet([<add.input_uses[2]: <CA>>]), "
90 "<add.outputs[0]: <I64*32>>: OFSet(["
91 "<st.input_uses[0]: <I64*32>>]), "
92 "<add.outputs[1]: <CA>>: OFSet()})"
93 )
94 self.assertEqual(
95 repr(fn_analysis.op_indexes),
96 "FMap({"
97 "arg:\n"
98 " (<...outputs[0]: <I64>>) <= FuncArgR3: 0, "
99 "vl:\n"
100 " (<...outputs[0]: <VL_MAXVL>>) <= SetVLI(0x20): 1, "
101 "ld:\n"
102 " (<...outputs[0]: <I64*32>>) <= SvLd(\n"
103 " <arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, 0x0)"
104 ": 2, "
105 "li:\n"
106 " (<...outputs[0]: <I64*32>>) <= SvLI(\n"
107 " <vl.outputs[0]: <VL_MAXVL>>, 0x0): 3, "
108 "ca:\n"
109 " (<...outputs[0]: <CA>>) <= SetCA: 4, "
110 "add:\n"
111 " (<...outputs[0]: <I64*32>>, <...outputs[1]: <CA>>\n"
112 " ) <= SvAddE(<ld.outputs[0]: <I64*32>>,\n"
113 " <li.outputs[0]: <I64*32>>, <ca.outputs[0]: <CA>>,\n"
114 " <vl.outputs[0]: <VL_MAXVL>>): 5, "
115 "st:\n"
116 " SvStd(<add.outputs[0]: <I64*32>>, <arg.outputs[0]: <I64>>,\n"
117 " <vl.outputs[0]: <VL_MAXVL>>, 0x0): 6"
118 "})"
119 )
120 self.assertEqual(
121 repr(fn_analysis.live_ranges),
122 "FMap({"
123 "<arg.outputs[0]: <I64>>: <range:ops[0]:Early..ops[6]:Late>, "
124 "<vl.outputs[0]: <VL_MAXVL>>: <range:ops[1]:Late..ops[6]:Late>, "
125 "<ld.outputs[0]: <I64*32>>: <range:ops[2]:Early..ops[5]:Late>, "
126 "<li.outputs[0]: <I64*32>>: <range:ops[3]:Early..ops[5]:Late>, "
127 "<ca.outputs[0]: <CA>>: <range:ops[4]:Late..ops[5]:Late>, "
128 "<add.outputs[0]: <I64*32>>: <range:ops[5]:Early..ops[6]:Late>, "
129 "<add.outputs[1]: <CA>>: <range:ops[5]:Early..ops[6]:Early>})"
130 )
131 self.assertEqual(
132 repr(fn_analysis.live_at),
133 "FMap({"
134 "<ops[0]:Early>: OFSet([<arg.outputs[0]: <I64>>]), "
135 "<ops[0]:Late>: OFSet([<arg.outputs[0]: <I64>>]), "
136 "<ops[1]:Early>: OFSet([<arg.outputs[0]: <I64>>]), "
137 "<ops[1]:Late>: OFSet(["
138 "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>]), "
139 "<ops[2]:Early>: OFSet(["
140 "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, "
141 "<ld.outputs[0]: <I64*32>>]), "
142 "<ops[2]:Late>: OFSet(["
143 "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, "
144 "<ld.outputs[0]: <I64*32>>]), "
145 "<ops[3]:Early>: OFSet(["
146 "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, "
147 "<ld.outputs[0]: <I64*32>>, <li.outputs[0]: <I64*32>>]), "
148 "<ops[3]:Late>: OFSet(["
149 "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, "
150 "<ld.outputs[0]: <I64*32>>, <li.outputs[0]: <I64*32>>]), "
151 "<ops[4]:Early>: OFSet(["
152 "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, "
153 "<ld.outputs[0]: <I64*32>>, <li.outputs[0]: <I64*32>>]), "
154 "<ops[4]:Late>: OFSet(["
155 "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, "
156 "<ld.outputs[0]: <I64*32>>, <li.outputs[0]: <I64*32>>, "
157 "<ca.outputs[0]: <CA>>]), "
158 "<ops[5]:Early>: OFSet(["
159 "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, "
160 "<ld.outputs[0]: <I64*32>>, <li.outputs[0]: <I64*32>>, "
161 "<ca.outputs[0]: <CA>>, <add.outputs[0]: <I64*32>>, "
162 "<add.outputs[1]: <CA>>]), "
163 "<ops[5]:Late>: OFSet(["
164 "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, "
165 "<add.outputs[0]: <I64*32>>, <add.outputs[1]: <CA>>]), "
166 "<ops[6]:Early>: OFSet(["
167 "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, "
168 "<add.outputs[0]: <I64*32>>]), "
169 "<ops[6]:Late>: OFSet()})"
170 )
171 self.assertEqual(
172 repr(fn_analysis.def_program_ranges),
173 "FMap({"
174 "<arg.outputs[0]: <I64>>: <range:ops[0]:Early..ops[1]:Early>, "
175 "<vl.outputs[0]: <VL_MAXVL>>: <range:ops[1]:Late..ops[2]:Early>, "
176 "<ld.outputs[0]: <I64*32>>: <range:ops[2]:Early..ops[3]:Early>, "
177 "<li.outputs[0]: <I64*32>>: <range:ops[3]:Early..ops[4]:Early>, "
178 "<ca.outputs[0]: <CA>>: <range:ops[4]:Late..ops[5]:Early>, "
179 "<add.outputs[0]: <I64*32>>: <range:ops[5]:Early..ops[6]:Early>, "
180 "<add.outputs[1]: <CA>>: <range:ops[5]:Early..ops[6]:Early>})"
181 )
182 self.assertEqual(
183 repr(fn_analysis.use_program_points),
184 "FMap({"
185 "<ld.input_uses[0]: <I64>>: <ops[2]:Early>, "
186 "<ld.input_uses[1]: <VL_MAXVL>>: <ops[2]:Early>, "
187 "<li.input_uses[0]: <VL_MAXVL>>: <ops[3]:Early>, "
188 "<add.input_uses[0]: <I64*32>>: <ops[5]:Early>, "
189 "<add.input_uses[1]: <I64*32>>: <ops[5]:Early>, "
190 "<add.input_uses[2]: <CA>>: <ops[5]:Early>, "
191 "<add.input_uses[3]: <VL_MAXVL>>: <ops[5]:Early>, "
192 "<st.input_uses[0]: <I64*32>>: <ops[6]:Early>, "
193 "<st.input_uses[1]: <I64>>: <ops[6]:Early>, "
194 "<st.input_uses[2]: <VL_MAXVL>>: <ops[6]:Early>})"
195 )
196 self.assertEqual(
197 repr(fn_analysis.all_program_points),
198 "<range:ops[0]:Early..ops[7]:Early>")
199 self.assertEqual(repr(fn_analysis.copies), "FMap({})")
200 self.assertEqual(
201 repr(fn_analysis.const_ssa_vals),
202 "FMap({"
203 "<vl.outputs[0]: <VL_MAXVL>>: (32,), "
204 "<li.outputs[0]: <I64*32>>: ("
205 "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, "
206 "0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0), "
207 "<ca.outputs[0]: <CA>>: (1,)})"
208 )
209 self.assertEqual(
210 repr(fn_analysis.const_ssa_val_sub_regs),
211 "FMap({"
212 "<vl.outputs[0]: <VL_MAXVL>>[0]: 32, "
213 "<li.outputs[0]: <I64*32>>[0]: 0, "
214 "<li.outputs[0]: <I64*32>>[1]: 0, "
215 "<li.outputs[0]: <I64*32>>[2]: 0, "
216 "<li.outputs[0]: <I64*32>>[3]: 0, "
217 "<li.outputs[0]: <I64*32>>[4]: 0, "
218 "<li.outputs[0]: <I64*32>>[5]: 0, "
219 "<li.outputs[0]: <I64*32>>[6]: 0, "
220 "<li.outputs[0]: <I64*32>>[7]: 0, "
221 "<li.outputs[0]: <I64*32>>[8]: 0, "
222 "<li.outputs[0]: <I64*32>>[9]: 0, "
223 "<li.outputs[0]: <I64*32>>[10]: 0, "
224 "<li.outputs[0]: <I64*32>>[11]: 0, "
225 "<li.outputs[0]: <I64*32>>[12]: 0, "
226 "<li.outputs[0]: <I64*32>>[13]: 0, "
227 "<li.outputs[0]: <I64*32>>[14]: 0, "
228 "<li.outputs[0]: <I64*32>>[15]: 0, "
229 "<li.outputs[0]: <I64*32>>[16]: 0, "
230 "<li.outputs[0]: <I64*32>>[17]: 0, "
231 "<li.outputs[0]: <I64*32>>[18]: 0, "
232 "<li.outputs[0]: <I64*32>>[19]: 0, "
233 "<li.outputs[0]: <I64*32>>[20]: 0, "
234 "<li.outputs[0]: <I64*32>>[21]: 0, "
235 "<li.outputs[0]: <I64*32>>[22]: 0, "
236 "<li.outputs[0]: <I64*32>>[23]: 0, "
237 "<li.outputs[0]: <I64*32>>[24]: 0, "
238 "<li.outputs[0]: <I64*32>>[25]: 0, "
239 "<li.outputs[0]: <I64*32>>[26]: 0, "
240 "<li.outputs[0]: <I64*32>>[27]: 0, "
241 "<li.outputs[0]: <I64*32>>[28]: 0, "
242 "<li.outputs[0]: <I64*32>>[29]: 0, "
243 "<li.outputs[0]: <I64*32>>[30]: 0, "
244 "<li.outputs[0]: <I64*32>>[31]: 0, "
245 "<ca.outputs[0]: <CA>>[0]: 1})"
246 )
247
248 def test_repr(self):
249 fn, _arg = self.make_add_fn()
250 self.assertEqual(
251 fn.ops_to_str(),
252 "arg:\n"
253 " (<...outputs[0]: <I64>>) <= FuncArgR3\n"
254 "vl:\n"
255 " (<...outputs[0]: <VL_MAXVL>>) <= SetVLI(0x20)\n"
256 "ld:\n"
257 " (<...outputs[0]: <I64*32>>) <= SvLd(\n"
258 " <arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, 0x0)\n"
259 "li:\n"
260 " (<...outputs[0]: <I64*32>>) <= SvLI(\n"
261 " <vl.outputs[0]: <VL_MAXVL>>, 0x0)\n"
262 "ca:\n"
263 " (<...outputs[0]: <CA>>) <= SetCA\n"
264 "add:\n"
265 " (<...outputs[0]: <I64*32>>, <...outputs[1]: <CA>>\n"
266 " ) <= SvAddE(<ld.outputs[0]: <I64*32>>,\n"
267 " <li.outputs[0]: <I64*32>>, <ca.outputs[0]: <CA>>,\n"
268 " <vl.outputs[0]: <VL_MAXVL>>)\n"
269 "st:\n"
270 " SvStd(<add.outputs[0]: <I64*32>>, <arg.outputs[0]: <I64>>,\n"
271 " <vl.outputs[0]: <VL_MAXVL>>, 0x0)"
272 )
273 self.assertEqual(
274 fn.ops_to_str(as_python_literal=True), r"""
275 "arg:\n"
276 " (<...outputs[0]: <I64>>) <= FuncArgR3\n"
277 "vl:\n"
278 " (<...outputs[0]: <VL_MAXVL>>) <= SetVLI(0x20)\n"
279 "ld:\n"
280 " (<...outputs[0]: <I64*32>>) <= SvLd(\n"
281 " <arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, 0x0)\n"
282 "li:\n"
283 " (<...outputs[0]: <I64*32>>) <= SvLI(\n"
284 " <vl.outputs[0]: <VL_MAXVL>>, 0x0)\n"
285 "ca:\n"
286 " (<...outputs[0]: <CA>>) <= SetCA\n"
287 "add:\n"
288 " (<...outputs[0]: <I64*32>>, <...outputs[1]: <CA>>\n"
289 " ) <= SvAddE(<ld.outputs[0]: <I64*32>>,\n"
290 " <li.outputs[0]: <I64*32>>, <ca.outputs[0]: <CA>>,\n"
291 " <vl.outputs[0]: <VL_MAXVL>>)\n"
292 "st:\n"
293 " SvStd(<add.outputs[0]: <I64*32>>, <arg.outputs[0]: <I64>>,\n"
294 " <vl.outputs[0]: <VL_MAXVL>>, 0x0)"
295 """[1:-1]
296 )
297 self.assertEqual([repr(op.properties) for op in fn.ops], [
298 "OpProperties(kind=OpKind.FuncArgR3, "
299 "inputs=(), "
300 "outputs=("
301 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
302 "LocKind.GPR: FBitSet([3])}), ty=<I64>), "
303 "tied_input_index=None, spread_index=None, "
304 "write_stage=OpStage.Early),), maxvl=1, copy_reg_len=0)",
305 "OpProperties(kind=OpKind.SetVLI, "
306 "inputs=(), "
307 "outputs=("
308 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
309 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
310 "tied_input_index=None, spread_index=None, "
311 "write_stage=OpStage.Late),), maxvl=1, copy_reg_len=0)",
312 "OpProperties(kind=OpKind.SvLd, "
313 "inputs=("
314 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
315 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
316 "ty=<I64>), "
317 "tied_input_index=None, spread_index=None, "
318 "write_stage=OpStage.Early), "
319 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
320 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
321 "tied_input_index=None, spread_index=None, "
322 "write_stage=OpStage.Early)), "
323 "outputs=("
324 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
325 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
326 "tied_input_index=None, spread_index=None, "
327 "write_stage=OpStage.Early),), maxvl=32, copy_reg_len=0)",
328 "OpProperties(kind=OpKind.SvLI, "
329 "inputs=("
330 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
331 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
332 "tied_input_index=None, spread_index=None, "
333 "write_stage=OpStage.Early),), "
334 "outputs=("
335 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
336 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
337 "tied_input_index=None, spread_index=None, "
338 "write_stage=OpStage.Early),), maxvl=32, copy_reg_len=0)",
339 "OpProperties(kind=OpKind.SetCA, "
340 "inputs=(), "
341 "outputs=("
342 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
343 "LocKind.CA: FBitSet([0])}), ty=<CA>), "
344 "tied_input_index=None, spread_index=None, "
345 "write_stage=OpStage.Late),), maxvl=1, copy_reg_len=0)",
346 "OpProperties(kind=OpKind.SvAddE, "
347 "inputs=("
348 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
349 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
350 "tied_input_index=None, spread_index=None, "
351 "write_stage=OpStage.Early), "
352 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
353 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
354 "tied_input_index=None, spread_index=None, "
355 "write_stage=OpStage.Early), "
356 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
357 "LocKind.CA: FBitSet([0])}), ty=<CA>), "
358 "tied_input_index=None, spread_index=None, "
359 "write_stage=OpStage.Early), "
360 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
361 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
362 "tied_input_index=None, spread_index=None, "
363 "write_stage=OpStage.Early)), "
364 "outputs=("
365 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
366 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
367 "tied_input_index=None, spread_index=None, "
368 "write_stage=OpStage.Early), "
369 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
370 "LocKind.CA: FBitSet([0])}), ty=<CA>), "
371 "tied_input_index=2, spread_index=None, "
372 "write_stage=OpStage.Early)), maxvl=32, copy_reg_len=0)",
373 "OpProperties(kind=OpKind.SvStd, "
374 "inputs=("
375 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
376 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
377 "tied_input_index=None, spread_index=None, "
378 "write_stage=OpStage.Early), "
379 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
380 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
381 "ty=<I64>), "
382 "tied_input_index=None, spread_index=None, "
383 "write_stage=OpStage.Early), "
384 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
385 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
386 "tied_input_index=None, spread_index=None, "
387 "write_stage=OpStage.Early)), "
388 "outputs=(), maxvl=32, copy_reg_len=0)",
389 ])
390
391 def test_pre_ra_insert_copies(self):
392 fn, _arg = self.make_add_fn()
393 fn.pre_ra_insert_copies()
394 self.assertEqual(
395 fn.ops_to_str(),
396 "arg:\n"
397 " (<...outputs[0]: <I64>>) <= FuncArgR3\n"
398 "arg.out0.copy:\n"
399 " (<...outputs[0]: <I64>>) <= CopyFromReg(\n"
400 " <arg.outputs[0]: <I64>>)\n"
401 "vl:\n"
402 " (<...outputs[0]: <VL_MAXVL>>) <= SetVLI(0x20)\n"
403 "ld.inp0.copy:\n"
404 " (<...outputs[0]: <I64>>) <= CopyToReg(\n"
405 " <arg.out0.copy.outputs[0]: <I64>>)\n"
406 "ld.inp1.setvl:\n"
407 " (<...outputs[0]: <VL_MAXVL>>) <= SetVLI(0x20)\n"
408 "ld:\n"
409 " (<...outputs[0]: <I64*32>>) <= SvLd(\n"
410 " <ld.inp0.copy.outputs[0]: <I64>>,\n"
411 " <ld.inp1.setvl.outputs[0]: <VL_MAXVL>>, 0x0)\n"
412 "ld.out0.setvl:\n"
413 " (<...outputs[0]: <VL_MAXVL>>) <= SetVLI(0x20)\n"
414 "ld.out0.copy:\n"
415 " (<...outputs[0]: <I64*32>>) <= VecCopyFromReg(\n"
416 " <ld.outputs[0]: <I64*32>>,\n"
417 " <ld.out0.setvl.outputs[0]: <VL_MAXVL>>)\n"
418 "li.inp0.setvl:\n"
419 " (<...outputs[0]: <VL_MAXVL>>) <= SetVLI(0x20)\n"
420 "li:\n"
421 " (<...outputs[0]: <I64*32>>) <= SvLI(\n"
422 " <li.inp0.setvl.outputs[0]: <VL_MAXVL>>, 0x0)\n"
423 "li.out0.setvl:\n"
424 " (<...outputs[0]: <VL_MAXVL>>) <= SetVLI(0x20)\n"
425 "li.out0.copy:\n"
426 " (<...outputs[0]: <I64*32>>) <= VecCopyFromReg(\n"
427 " <li.outputs[0]: <I64*32>>,\n"
428 " <li.out0.setvl.outputs[0]: <VL_MAXVL>>)\n"
429 "ca:\n"
430 " (<...outputs[0]: <CA>>) <= SetCA\n"
431 "add.inp0.setvl:\n"
432 " (<...outputs[0]: <VL_MAXVL>>) <= SetVLI(0x20)\n"
433 "add.inp0.copy:\n"
434 " (<...outputs[0]: <I64*32>>) <= VecCopyToReg(\n"
435 " <ld.out0.copy.outputs[0]: <I64*32>>,\n"
436 " <add.inp0.setvl.outputs[0]: <VL_MAXVL>>)\n"
437 "add.inp1.setvl:\n"
438 " (<...outputs[0]: <VL_MAXVL>>) <= SetVLI(0x20)\n"
439 "add.inp1.copy:\n"
440 " (<...outputs[0]: <I64*32>>) <= VecCopyToReg(\n"
441 " <li.out0.copy.outputs[0]: <I64*32>>,\n"
442 " <add.inp1.setvl.outputs[0]: <VL_MAXVL>>)\n"
443 "add.inp3.setvl:\n"
444 " (<...outputs[0]: <VL_MAXVL>>) <= SetVLI(0x20)\n"
445 "add:\n"
446 " (<...outputs[0]: <I64*32>>, <...outputs[1]: <CA>>\n"
447 " ) <= SvAddE(<add.inp0.copy.outputs[0]: <I64*32>>,\n"
448 " <add.inp1.copy.outputs[0]: <I64*32>>,\n"
449 " <ca.outputs[0]: <CA>>,\n"
450 " <add.inp3.setvl.outputs[0]: <VL_MAXVL>>)\n"
451 "add.out0.setvl:\n"
452 " (<...outputs[0]: <VL_MAXVL>>) <= SetVLI(0x20)\n"
453 "add.out0.copy:\n"
454 " (<...outputs[0]: <I64*32>>) <= VecCopyFromReg(\n"
455 " <add.outputs[0]: <I64*32>>,\n"
456 " <add.out0.setvl.outputs[0]: <VL_MAXVL>>)\n"
457 "st.inp0.setvl:\n"
458 " (<...outputs[0]: <VL_MAXVL>>) <= SetVLI(0x20)\n"
459 "st.inp0.copy:\n"
460 " (<...outputs[0]: <I64*32>>) <= VecCopyToReg(\n"
461 " <add.out0.copy.outputs[0]: <I64*32>>,\n"
462 " <st.inp0.setvl.outputs[0]: <VL_MAXVL>>)\n"
463 "st.inp1.copy:\n"
464 " (<...outputs[0]: <I64>>) <= CopyToReg(\n"
465 " <arg.out0.copy.outputs[0]: <I64>>)\n"
466 "st.inp2.setvl:\n"
467 " (<...outputs[0]: <VL_MAXVL>>) <= SetVLI(0x20)\n"
468 "st:\n"
469 " SvStd(<st.inp0.copy.outputs[0]: <I64*32>>,\n"
470 " <st.inp1.copy.outputs[0]: <I64>>,\n"
471 " <st.inp2.setvl.outputs[0]: <VL_MAXVL>>, 0x0)"
472 )
473 self.assertEqual([repr(op.properties) for op in fn.ops], [
474 "OpProperties(kind=OpKind.FuncArgR3, "
475 "inputs=(), "
476 "outputs=("
477 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
478 "LocKind.GPR: FBitSet([3])}), ty=<I64>), "
479 "tied_input_index=None, spread_index=None, "
480 "write_stage=OpStage.Early),), maxvl=1, copy_reg_len=0)",
481 "OpProperties(kind=OpKind.CopyFromReg, "
482 "inputs=("
483 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
484 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
485 "ty=<I64>), "
486 "tied_input_index=None, spread_index=None, "
487 "write_stage=OpStage.Early),), "
488 "outputs=("
489 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
490 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)]), "
491 "LocKind.StackI64: FBitSet(range(0, 512))}), ty=<I64>), "
492 "tied_input_index=None, spread_index=None, "
493 "write_stage=OpStage.Late),), maxvl=1, copy_reg_len=1)",
494 "OpProperties(kind=OpKind.SetVLI, "
495 "inputs=(), "
496 "outputs=("
497 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
498 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
499 "tied_input_index=None, spread_index=None, "
500 "write_stage=OpStage.Late),), maxvl=1, copy_reg_len=0)",
501 "OpProperties(kind=OpKind.CopyToReg, "
502 "inputs=("
503 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
504 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)]), "
505 "LocKind.StackI64: FBitSet(range(0, 512))}), ty=<I64>), "
506 "tied_input_index=None, spread_index=None, "
507 "write_stage=OpStage.Early),), "
508 "outputs=("
509 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
510 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
511 "ty=<I64>), "
512 "tied_input_index=None, spread_index=None, "
513 "write_stage=OpStage.Late),), maxvl=1, copy_reg_len=1)",
514 "OpProperties(kind=OpKind.SetVLI, "
515 "inputs=(), "
516 "outputs=("
517 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
518 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
519 "tied_input_index=None, spread_index=None, "
520 "write_stage=OpStage.Late),), maxvl=1, copy_reg_len=0)",
521 "OpProperties(kind=OpKind.SvLd, "
522 "inputs=("
523 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
524 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
525 "ty=<I64>), "
526 "tied_input_index=None, spread_index=None, "
527 "write_stage=OpStage.Early), "
528 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
529 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
530 "tied_input_index=None, spread_index=None, "
531 "write_stage=OpStage.Early)), "
532 "outputs=("
533 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
534 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
535 "tied_input_index=None, spread_index=None, "
536 "write_stage=OpStage.Early),), maxvl=32, copy_reg_len=0)",
537 "OpProperties(kind=OpKind.SetVLI, "
538 "inputs=(), "
539 "outputs=("
540 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
541 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
542 "tied_input_index=None, spread_index=None, "
543 "write_stage=OpStage.Late),), maxvl=1, copy_reg_len=0)",
544 "OpProperties(kind=OpKind.VecCopyFromReg, "
545 "inputs=("
546 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
547 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
548 "tied_input_index=None, spread_index=None, "
549 "write_stage=OpStage.Early), "
550 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
551 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
552 "tied_input_index=None, spread_index=None, "
553 "write_stage=OpStage.Early)), "
554 "outputs=("
555 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
556 "LocKind.GPR: FBitSet(range(14, 97)), "
557 "LocKind.StackI64: FBitSet(range(0, 481))}), ty=<I64*32>), "
558 "tied_input_index=None, spread_index=None, "
559 "write_stage=OpStage.Late),), maxvl=32, copy_reg_len=32)",
560 "OpProperties(kind=OpKind.SetVLI, "
561 "inputs=(), "
562 "outputs=("
563 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
564 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
565 "tied_input_index=None, spread_index=None, "
566 "write_stage=OpStage.Late),), maxvl=1, copy_reg_len=0)",
567 "OpProperties(kind=OpKind.SvLI, "
568 "inputs=("
569 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
570 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
571 "tied_input_index=None, spread_index=None, "
572 "write_stage=OpStage.Early),), "
573 "outputs=("
574 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
575 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
576 "tied_input_index=None, spread_index=None, "
577 "write_stage=OpStage.Early),), maxvl=32, copy_reg_len=0)",
578 "OpProperties(kind=OpKind.SetVLI, "
579 "inputs=(), "
580 "outputs=("
581 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
582 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
583 "tied_input_index=None, spread_index=None, "
584 "write_stage=OpStage.Late),), maxvl=1, copy_reg_len=0)",
585 "OpProperties(kind=OpKind.VecCopyFromReg, "
586 "inputs=("
587 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
588 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
589 "tied_input_index=None, spread_index=None, "
590 "write_stage=OpStage.Early), "
591 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
592 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
593 "tied_input_index=None, spread_index=None, "
594 "write_stage=OpStage.Early)), "
595 "outputs=("
596 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
597 "LocKind.GPR: FBitSet(range(14, 97)), "
598 "LocKind.StackI64: FBitSet(range(0, 481))}), ty=<I64*32>), "
599 "tied_input_index=None, spread_index=None, "
600 "write_stage=OpStage.Late),), maxvl=32, copy_reg_len=32)",
601 "OpProperties(kind=OpKind.SetCA, "
602 "inputs=(), "
603 "outputs=("
604 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
605 "LocKind.CA: FBitSet([0])}), ty=<CA>), "
606 "tied_input_index=None, spread_index=None, "
607 "write_stage=OpStage.Late),), maxvl=1, copy_reg_len=0)",
608 "OpProperties(kind=OpKind.SetVLI, "
609 "inputs=(), "
610 "outputs=("
611 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
612 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
613 "tied_input_index=None, spread_index=None, "
614 "write_stage=OpStage.Late),), maxvl=1, copy_reg_len=0)",
615 "OpProperties(kind=OpKind.VecCopyToReg, "
616 "inputs=("
617 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
618 "LocKind.GPR: FBitSet(range(14, 97)), "
619 "LocKind.StackI64: FBitSet(range(0, 481))}), ty=<I64*32>), "
620 "tied_input_index=None, spread_index=None, "
621 "write_stage=OpStage.Early), "
622 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
623 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
624 "tied_input_index=None, spread_index=None, "
625 "write_stage=OpStage.Early)), "
626 "outputs=("
627 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
628 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
629 "tied_input_index=None, spread_index=None, "
630 "write_stage=OpStage.Late),), maxvl=32, copy_reg_len=32)",
631 "OpProperties(kind=OpKind.SetVLI, "
632 "inputs=(), "
633 "outputs=("
634 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
635 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
636 "tied_input_index=None, spread_index=None, "
637 "write_stage=OpStage.Late),), maxvl=1, copy_reg_len=0)",
638 "OpProperties(kind=OpKind.VecCopyToReg, "
639 "inputs=("
640 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
641 "LocKind.GPR: FBitSet(range(14, 97)), "
642 "LocKind.StackI64: FBitSet(range(0, 481))}), ty=<I64*32>), "
643 "tied_input_index=None, spread_index=None, "
644 "write_stage=OpStage.Early), "
645 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
646 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
647 "tied_input_index=None, spread_index=None, "
648 "write_stage=OpStage.Early)), "
649 "outputs=("
650 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
651 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
652 "tied_input_index=None, spread_index=None, "
653 "write_stage=OpStage.Late),), maxvl=32, copy_reg_len=32)",
654 "OpProperties(kind=OpKind.SetVLI, "
655 "inputs=(), "
656 "outputs=("
657 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
658 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
659 "tied_input_index=None, spread_index=None, "
660 "write_stage=OpStage.Late),), maxvl=1, copy_reg_len=0)",
661 "OpProperties(kind=OpKind.SvAddE, "
662 "inputs=("
663 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
664 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
665 "tied_input_index=None, spread_index=None, "
666 "write_stage=OpStage.Early), "
667 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
668 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
669 "tied_input_index=None, spread_index=None, "
670 "write_stage=OpStage.Early), "
671 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
672 "LocKind.CA: FBitSet([0])}), ty=<CA>), "
673 "tied_input_index=None, spread_index=None, "
674 "write_stage=OpStage.Early), "
675 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
676 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
677 "tied_input_index=None, spread_index=None, "
678 "write_stage=OpStage.Early)), "
679 "outputs=("
680 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
681 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
682 "tied_input_index=None, spread_index=None, "
683 "write_stage=OpStage.Early), "
684 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
685 "LocKind.CA: FBitSet([0])}), ty=<CA>), "
686 "tied_input_index=2, spread_index=None, "
687 "write_stage=OpStage.Early)), maxvl=32, copy_reg_len=0)",
688 "OpProperties(kind=OpKind.SetVLI, "
689 "inputs=(), "
690 "outputs=("
691 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
692 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
693 "tied_input_index=None, spread_index=None, "
694 "write_stage=OpStage.Late),), maxvl=1, copy_reg_len=0)",
695 "OpProperties(kind=OpKind.VecCopyFromReg, "
696 "inputs=("
697 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
698 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
699 "tied_input_index=None, spread_index=None, "
700 "write_stage=OpStage.Early), "
701 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
702 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
703 "tied_input_index=None, spread_index=None, "
704 "write_stage=OpStage.Early)), "
705 "outputs=("
706 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
707 "LocKind.GPR: FBitSet(range(14, 97)), "
708 "LocKind.StackI64: FBitSet(range(0, 481))}), ty=<I64*32>), "
709 "tied_input_index=None, spread_index=None, "
710 "write_stage=OpStage.Late),), maxvl=32, copy_reg_len=32)",
711 "OpProperties(kind=OpKind.SetVLI, "
712 "inputs=(), "
713 "outputs=("
714 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
715 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
716 "tied_input_index=None, spread_index=None, "
717 "write_stage=OpStage.Late),), maxvl=1, copy_reg_len=0)",
718 "OpProperties(kind=OpKind.VecCopyToReg, "
719 "inputs=("
720 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
721 "LocKind.GPR: FBitSet(range(14, 97)), "
722 "LocKind.StackI64: FBitSet(range(0, 481))}), ty=<I64*32>), "
723 "tied_input_index=None, spread_index=None, "
724 "write_stage=OpStage.Early), "
725 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
726 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
727 "tied_input_index=None, spread_index=None, "
728 "write_stage=OpStage.Early)), "
729 "outputs=("
730 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
731 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
732 "tied_input_index=None, spread_index=None, "
733 "write_stage=OpStage.Late),), maxvl=32, copy_reg_len=32)",
734 "OpProperties(kind=OpKind.CopyToReg, "
735 "inputs=("
736 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
737 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)]), "
738 "LocKind.StackI64: FBitSet(range(0, 512))}), ty=<I64>), "
739 "tied_input_index=None, spread_index=None, "
740 "write_stage=OpStage.Early),), "
741 "outputs=("
742 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
743 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
744 "ty=<I64>), "
745 "tied_input_index=None, spread_index=None, "
746 "write_stage=OpStage.Late),), maxvl=1, copy_reg_len=1)",
747 "OpProperties(kind=OpKind.SetVLI, "
748 "inputs=(), "
749 "outputs=("
750 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
751 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
752 "tied_input_index=None, spread_index=None, "
753 "write_stage=OpStage.Late),), maxvl=1, copy_reg_len=0)",
754 "OpProperties(kind=OpKind.SvStd, "
755 "inputs=("
756 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
757 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
758 "tied_input_index=None, spread_index=None, "
759 "write_stage=OpStage.Early), "
760 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
761 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
762 "ty=<I64>), "
763 "tied_input_index=None, spread_index=None, "
764 "write_stage=OpStage.Early), "
765 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
766 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
767 "tied_input_index=None, spread_index=None, "
768 "write_stage=OpStage.Early)), "
769 "outputs=(), maxvl=32, copy_reg_len=0)",
770 ])
771
772 def test_sim(self):
773 fn, arg = self.make_add_fn()
774 addr = 0x100
775 state = PreRASimState(ssa_vals={arg: (addr,)}, memory={})
776 state.store(addr=addr, value=0xffffffff_ffffffff,
777 size_in_bytes=GPR_SIZE_IN_BYTES)
778 state.store(addr=addr + GPR_SIZE_IN_BYTES, value=0xabcdef01_23456789,
779 size_in_bytes=GPR_SIZE_IN_BYTES)
780 self.assertEqual(
781 repr(state),
782 "PreRASimState(memory={\n"
783 "0x00100: <0xffffffffffffffff>,\n"
784 "0x00108: <0xabcdef0123456789>}, "
785 "ssa_vals={<arg.outputs[0]: <I64>>: (0x100,)})")
786 fn.sim(state)
787 self.assertEqual(
788 repr(state),
789 "PreRASimState(memory={\n"
790 "0x00100: <0x0000000000000000>,\n"
791 "0x00108: <0xabcdef012345678a>,\n"
792 "0x00110: <0x0000000000000000>,\n"
793 "0x00118: <0x0000000000000000>,\n"
794 "0x00120: <0x0000000000000000>,\n"
795 "0x00128: <0x0000000000000000>,\n"
796 "0x00130: <0x0000000000000000>,\n"
797 "0x00138: <0x0000000000000000>,\n"
798 "0x00140: <0x0000000000000000>,\n"
799 "0x00148: <0x0000000000000000>,\n"
800 "0x00150: <0x0000000000000000>,\n"
801 "0x00158: <0x0000000000000000>,\n"
802 "0x00160: <0x0000000000000000>,\n"
803 "0x00168: <0x0000000000000000>,\n"
804 "0x00170: <0x0000000000000000>,\n"
805 "0x00178: <0x0000000000000000>,\n"
806 "0x00180: <0x0000000000000000>,\n"
807 "0x00188: <0x0000000000000000>,\n"
808 "0x00190: <0x0000000000000000>,\n"
809 "0x00198: <0x0000000000000000>,\n"
810 "0x001a0: <0x0000000000000000>,\n"
811 "0x001a8: <0x0000000000000000>,\n"
812 "0x001b0: <0x0000000000000000>,\n"
813 "0x001b8: <0x0000000000000000>,\n"
814 "0x001c0: <0x0000000000000000>,\n"
815 "0x001c8: <0x0000000000000000>,\n"
816 "0x001d0: <0x0000000000000000>,\n"
817 "0x001d8: <0x0000000000000000>,\n"
818 "0x001e0: <0x0000000000000000>,\n"
819 "0x001e8: <0x0000000000000000>,\n"
820 "0x001f0: <0x0000000000000000>,\n"
821 "0x001f8: <0x0000000000000000>}, ssa_vals={\n"
822 "<arg.outputs[0]: <I64>>: (0x100,),\n"
823 "<vl.outputs[0]: <VL_MAXVL>>: (0x20,),\n"
824 "<ld.outputs[0]: <I64*32>>: (\n"
825 " 0xffffffffffffffff, 0xabcdef0123456789, 0x0, 0x0,\n"
826 " 0x0, 0x0, 0x0, 0x0,\n"
827 " 0x0, 0x0, 0x0, 0x0,\n"
828 " 0x0, 0x0, 0x0, 0x0,\n"
829 " 0x0, 0x0, 0x0, 0x0,\n"
830 " 0x0, 0x0, 0x0, 0x0,\n"
831 " 0x0, 0x0, 0x0, 0x0,\n"
832 " 0x0, 0x0, 0x0, 0x0),\n"
833 "<li.outputs[0]: <I64*32>>: (\n"
834 " 0x0, 0x0, 0x0, 0x0,\n"
835 " 0x0, 0x0, 0x0, 0x0,\n"
836 " 0x0, 0x0, 0x0, 0x0,\n"
837 " 0x0, 0x0, 0x0, 0x0,\n"
838 " 0x0, 0x0, 0x0, 0x0,\n"
839 " 0x0, 0x0, 0x0, 0x0,\n"
840 " 0x0, 0x0, 0x0, 0x0,\n"
841 " 0x0, 0x0, 0x0, 0x0),\n"
842 "<ca.outputs[0]: <CA>>: (0x1,),\n"
843 "<add.outputs[0]: <I64*32>>: (\n"
844 " 0x0, 0xabcdef012345678a, 0x0, 0x0,\n"
845 " 0x0, 0x0, 0x0, 0x0,\n"
846 " 0x0, 0x0, 0x0, 0x0,\n"
847 " 0x0, 0x0, 0x0, 0x0,\n"
848 " 0x0, 0x0, 0x0, 0x0,\n"
849 " 0x0, 0x0, 0x0, 0x0,\n"
850 " 0x0, 0x0, 0x0, 0x0,\n"
851 " 0x0, 0x0, 0x0, 0x0),\n"
852 "<add.outputs[1]: <CA>>: (0x0,),\n"
853 "})")
854
855 def test_gen_asm(self):
856 fn, _arg = self.make_add_fn()
857 fn.pre_ra_insert_copies()
858 VL_LOC = Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1)
859 CA_LOC = Loc(kind=LocKind.CA, start=0, reg_len=1)
860 state = GenAsmState(allocated_locs={
861 fn.ops[0].outputs[0]: Loc(kind=LocKind.GPR, start=3, reg_len=1),
862 fn.ops[1].outputs[0]: Loc(kind=LocKind.GPR, start=3, reg_len=1),
863 fn.ops[2].outputs[0]: VL_LOC,
864 fn.ops[3].outputs[0]: Loc(kind=LocKind.GPR, start=3, reg_len=1),
865 fn.ops[4].outputs[0]: VL_LOC,
866 fn.ops[5].outputs[0]: Loc(kind=LocKind.GPR, start=32, reg_len=32),
867 fn.ops[6].outputs[0]: VL_LOC,
868 fn.ops[7].outputs[0]: Loc(kind=LocKind.GPR, start=32, reg_len=32),
869 fn.ops[8].outputs[0]: VL_LOC,
870 fn.ops[9].outputs[0]: Loc(kind=LocKind.GPR, start=64, reg_len=32),
871 fn.ops[10].outputs[0]: VL_LOC,
872 fn.ops[11].outputs[0]: Loc(kind=LocKind.GPR, start=64, reg_len=32),
873 fn.ops[12].outputs[0]: CA_LOC,
874 fn.ops[13].outputs[0]: VL_LOC,
875 fn.ops[14].outputs[0]: Loc(kind=LocKind.GPR, start=32, reg_len=32),
876 fn.ops[15].outputs[0]: VL_LOC,
877 fn.ops[16].outputs[0]: Loc(kind=LocKind.GPR, start=64, reg_len=32),
878 fn.ops[17].outputs[0]: VL_LOC,
879 fn.ops[18].outputs[0]: Loc(kind=LocKind.GPR, start=32, reg_len=32),
880 fn.ops[18].outputs[1]: CA_LOC,
881 fn.ops[19].outputs[0]: VL_LOC,
882 fn.ops[20].outputs[0]: Loc(kind=LocKind.GPR, start=32, reg_len=32),
883 fn.ops[21].outputs[0]: VL_LOC,
884 fn.ops[22].outputs[0]: Loc(kind=LocKind.GPR, start=32, reg_len=32),
885 fn.ops[23].outputs[0]: Loc(kind=LocKind.GPR, start=3, reg_len=1),
886 fn.ops[24].outputs[0]: VL_LOC,
887 })
888 fn.gen_asm(state)
889 self.assertEqual(state.output, [
890 'setvl 0, 0, 32, 0, 1, 1',
891 'setvl 0, 0, 32, 0, 1, 1',
892 'sv.ld *32, 0(3)',
893 'setvl 0, 0, 32, 0, 1, 1',
894 'setvl 0, 0, 32, 0, 1, 1',
895 'sv.addi *64, 0, 0',
896 'setvl 0, 0, 32, 0, 1, 1',
897 'subfc 0, 0, 0',
898 'setvl 0, 0, 32, 0, 1, 1',
899 'setvl 0, 0, 32, 0, 1, 1',
900 'setvl 0, 0, 32, 0, 1, 1',
901 'sv.adde *32, *32, *64',
902 'setvl 0, 0, 32, 0, 1, 1',
903 'setvl 0, 0, 32, 0, 1, 1',
904 'setvl 0, 0, 32, 0, 1, 1',
905 'sv.std *32, 0(3)',
906 ])
907
908 def test_spread(self):
909 fn = Fn()
910 maxvl = 4
911 vl = fn.append_new_op(OpKind.SetVLI, immediates=[maxvl],
912 name="vl", maxvl=maxvl).outputs[0]
913 li = fn.append_new_op(OpKind.SvLI, input_vals=[vl], immediates=[0],
914 name="li", maxvl=maxvl).outputs[0]
915 spread_op = fn.append_new_op(OpKind.Spread, input_vals=[li, vl],
916 name="spread", maxvl=maxvl)
917 self.assertEqual(spread_op.outputs[0].ty_before_spread,
918 Ty(base_ty=BaseTy.I64, reg_len=maxvl))
919 _concat = fn.append_new_op(
920 OpKind.Concat, input_vals=[*spread_op.outputs[::-1], vl],
921 name="concat", maxvl=maxvl)
922 self.assertEqual([repr(op.properties) for op in fn.ops], [
923 "OpProperties(kind=OpKind.SetVLI, inputs=("
924 "), outputs=("
925 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
926 "LocKind.VL_MAXVL: FBitSet([0])}), "
927 "ty=<VL_MAXVL>), tied_input_index=None, spread_index=None, "
928 "write_stage=OpStage.Late),"
929 "), maxvl=4, copy_reg_len=0)",
930 "OpProperties(kind=OpKind.SvLI, inputs=("
931 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
932 "LocKind.VL_MAXVL: FBitSet([0])}), "
933 "ty=<VL_MAXVL>), tied_input_index=None, spread_index=None, "
934 "write_stage=OpStage.Early),"
935 "), outputs=("
936 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
937 "LocKind.GPR: FBitSet([*range(3, 10), *range(14, 125)])}), "
938 "ty=<I64*4>), tied_input_index=None, spread_index=None, "
939 "write_stage=OpStage.Early),"
940 "), maxvl=4, copy_reg_len=0)",
941 "OpProperties(kind=OpKind.Spread, inputs=("
942 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
943 "LocKind.GPR: FBitSet([*range(3, 10), *range(14, 125)])}), "
944 "ty=<I64*4>), tied_input_index=None, spread_index=None, "
945 "write_stage=OpStage.Early), "
946 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
947 "LocKind.VL_MAXVL: FBitSet([0])}), "
948 "ty=<VL_MAXVL>), tied_input_index=None, spread_index=None, "
949 "write_stage=OpStage.Early)"
950 "), outputs=("
951 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
952 "LocKind.GPR: FBitSet([*range(3, 10), *range(14, 125)])}), "
953 "ty=<I64*4>), tied_input_index=None, spread_index=0, "
954 "write_stage=OpStage.Late), "
955 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
956 "LocKind.GPR: FBitSet([*range(3, 10), *range(14, 125)])}), "
957 "ty=<I64*4>), tied_input_index=None, spread_index=1, "
958 "write_stage=OpStage.Late), "
959 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
960 "LocKind.GPR: FBitSet([*range(3, 10), *range(14, 125)])}), "
961 "ty=<I64*4>), tied_input_index=None, spread_index=2, "
962 "write_stage=OpStage.Late), "
963 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
964 "LocKind.GPR: FBitSet([*range(3, 10), *range(14, 125)])}), "
965 "ty=<I64*4>), tied_input_index=None, spread_index=3, "
966 "write_stage=OpStage.Late)"
967 "), maxvl=4, copy_reg_len=4)",
968 "OpProperties(kind=OpKind.Concat, inputs=("
969 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
970 "LocKind.GPR: FBitSet([*range(3, 10), *range(14, 125)])}), "
971 "ty=<I64*4>), tied_input_index=None, spread_index=0, "
972 "write_stage=OpStage.Early), "
973 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
974 "LocKind.GPR: FBitSet([*range(3, 10), *range(14, 125)])}), "
975 "ty=<I64*4>), tied_input_index=None, spread_index=1, "
976 "write_stage=OpStage.Early), "
977 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
978 "LocKind.GPR: FBitSet([*range(3, 10), *range(14, 125)])}), "
979 "ty=<I64*4>), tied_input_index=None, spread_index=2, "
980 "write_stage=OpStage.Early), "
981 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
982 "LocKind.GPR: FBitSet([*range(3, 10), *range(14, 125)])}), "
983 "ty=<I64*4>), tied_input_index=None, spread_index=3, "
984 "write_stage=OpStage.Early), "
985 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
986 "LocKind.VL_MAXVL: FBitSet([0])}), "
987 "ty=<VL_MAXVL>), tied_input_index=None, spread_index=None, "
988 "write_stage=OpStage.Early)"
989 "), outputs=("
990 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
991 "LocKind.GPR: FBitSet([*range(3, 10), *range(14, 125)])}), "
992 "ty=<I64*4>), tied_input_index=None, spread_index=None, "
993 "write_stage=OpStage.Late),"
994 "), maxvl=4, copy_reg_len=4)",
995 ])
996 self.assertEqual(
997 fn.ops_to_str(),
998 "vl:\n"
999 " (<...outputs[0]: <VL_MAXVL>>) <= SetVLI(0x4)\n"
1000 "li:\n"
1001 " (<...outputs[0]: <I64*4>>) <= SvLI(\n"
1002 " <vl.outputs[0]: <VL_MAXVL>>, 0x0)\n"
1003 "spread:\n"
1004 " (<...outputs[0]: <I64>>, <...outputs[1]: <I64>>,\n"
1005 " <...outputs[2]: <I64>>, <...outputs[3]: <I64>>) <= Spread(\n"
1006 " <li.outputs[0]: <I64*4>>, <vl.outputs[0]: <VL_MAXVL>>)\n"
1007 "concat:\n"
1008 " (<...outputs[0]: <I64*4>>) <= Concat(\n"
1009 " <spread.outputs[3]: <I64>>, <spread.outputs[2]: <I64>>,\n"
1010 " <spread.outputs[1]: <I64>>, <spread.outputs[0]: <I64>>,\n"
1011 " <vl.outputs[0]: <VL_MAXVL>>)"
1012 )
1013 fn_analysis = FnAnalysis(fn)
1014 self.assertEqual(
1015 repr(fn_analysis.copies),
1016 "FMap({"
1017 "<spread.outputs[0]: <I64>>[0]: <li.outputs[0]: <I64*4>>[0], "
1018 "<spread.outputs[1]: <I64>>[0]: <li.outputs[0]: <I64*4>>[1], "
1019 "<spread.outputs[2]: <I64>>[0]: <li.outputs[0]: <I64*4>>[2], "
1020 "<spread.outputs[3]: <I64>>[0]: <li.outputs[0]: <I64*4>>[3], "
1021 "<concat.outputs[0]: <I64*4>>[0]: <li.outputs[0]: <I64*4>>[3], "
1022 "<concat.outputs[0]: <I64*4>>[1]: <li.outputs[0]: <I64*4>>[2], "
1023 "<concat.outputs[0]: <I64*4>>[2]: <li.outputs[0]: <I64*4>>[1], "
1024 "<concat.outputs[0]: <I64*4>>[3]: <li.outputs[0]: <I64*4>>[0]})"
1025 )
1026 self.assertEqual(
1027 repr(fn_analysis.const_ssa_val_sub_regs),
1028 "FMap({"
1029 "<vl.outputs[0]: <VL_MAXVL>>[0]: 4, "
1030 "<li.outputs[0]: <I64*4>>[0]: 0, "
1031 "<li.outputs[0]: <I64*4>>[1]: 0, "
1032 "<li.outputs[0]: <I64*4>>[2]: 0, "
1033 "<li.outputs[0]: <I64*4>>[3]: 0, "
1034 "<spread.outputs[0]: <I64>>[0]: 0, "
1035 "<spread.outputs[1]: <I64>>[0]: 0, "
1036 "<spread.outputs[2]: <I64>>[0]: 0, "
1037 "<spread.outputs[3]: <I64>>[0]: 0, "
1038 "<concat.outputs[0]: <I64*4>>[0]: 0, "
1039 "<concat.outputs[0]: <I64*4>>[1]: 0, "
1040 "<concat.outputs[0]: <I64*4>>[2]: 0, "
1041 "<concat.outputs[0]: <I64*4>>[3]: 0})"
1042 )
1043
1044
1045 if __name__ == "__main__":
1046 _ = unittest.main()