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[bigint-presentation-code.git] / src / bigint_presentation_code / _tests / test_compiler_ir.py
1 import unittest
2
3 from bigint_presentation_code.compiler_ir import (GPR_SIZE_IN_BYTES, BaseTy,
4 Fn, FnAnalysis, GenAsmState,
5 Loc, LocKind, LocSet, OpKind,
6 OpStage, PreRASimState,
7 ProgramPoint, SSAVal, Ty)
8 from bigint_presentation_code.util import OFSet
9
10
11 class TestCompilerIR(unittest.TestCase):
12 maxDiff = None
13
14 def test_program_point(self):
15 # type: () -> None
16 expected = [] # type: list[ProgramPoint]
17 for op_index in range(5):
18 for stage in OpStage:
19 expected.append(ProgramPoint(op_index=op_index, stage=stage))
20
21 for idx, pp in enumerate(expected):
22 if idx + 1 < len(expected):
23 self.assertEqual(pp.next(), expected[idx + 1])
24
25 self.assertEqual(sorted(expected), expected)
26
27 def test_loc_set_hash_intern(self):
28 # type: () -> None
29 # hashes should match all other collections.abc.Set types, which are
30 # supposed to match frozenset but don't until Python 3.11 because of a
31 # bug fixed in:
32 # https://github.com/python/cpython/commit/c878f5d81772dc6f718d6608c78baa4be9a4f176
33 a = LocSet([])
34 self.assertEqual(hash(a), hash(OFSet()))
35 starts = 0, 1, 0, 1, 2
36 GPR = LocKind.GPR
37 expected = OFSet(Loc(kind=GPR, start=i, reg_len=1) for i in starts)
38 b = LocSet(expected)
39 c = LocSet(Loc(kind=GPR, start=i, reg_len=1) for i in starts)
40 d = LocSet(Loc(kind=GPR, start=i, reg_len=1) for i in starts)
41 # hashes should be equal to OFSet's hash
42 self.assertEqual(hash(b), hash(expected))
43 self.assertEqual(hash(c), hash(expected))
44 self.assertEqual(hash(d), hash(expected))
45 # they should intern to the same object
46 self.assertIs(b, d)
47 self.assertIs(c, d)
48
49 def make_add_fn(self):
50 # type: () -> tuple[Fn, SSAVal]
51 fn = Fn()
52 op0 = fn.append_new_op(OpKind.FuncArgR3, name="arg")
53 arg = op0.outputs[0]
54 MAXVL = 32
55 op1 = fn.append_new_op(OpKind.SetVLI, immediates=[MAXVL], name="vl")
56 vl = op1.outputs[0]
57 op2 = fn.append_new_op(
58 OpKind.SvLd, input_vals=[arg, vl], immediates=[0], maxvl=MAXVL,
59 name="ld")
60 a = op2.outputs[0]
61 op3 = fn.append_new_op(OpKind.SvLI, input_vals=[vl], immediates=[0],
62 maxvl=MAXVL, name="li")
63 b = op3.outputs[0]
64 op4 = fn.append_new_op(OpKind.SetCA, name="ca")
65 ca = op4.outputs[0]
66 op5 = fn.append_new_op(
67 OpKind.SvAddE, input_vals=[a, b, ca, vl], maxvl=MAXVL, name="add")
68 s = op5.outputs[0]
69 _ = fn.append_new_op(OpKind.SvStd, input_vals=[s, arg, vl],
70 immediates=[0], maxvl=MAXVL, name="st")
71 return fn, arg
72
73 def test_fn_analysis(self):
74 fn, _arg = self.make_add_fn()
75 fn_analysis = FnAnalysis(fn)
76 self.assertEqual(
77 repr(fn_analysis.uses),
78 "FMap({"
79 "<arg.outputs[0]: <I64>>: OFSet(["
80 "<ld.input_uses[0]: <I64>>, <st.input_uses[1]: <I64>>]), "
81 "<vl.outputs[0]: <VL_MAXVL>>: OFSet(["
82 "<ld.input_uses[1]: <VL_MAXVL>>, <li.input_uses[0]: <VL_MAXVL>>, "
83 "<add.input_uses[3]: <VL_MAXVL>>, "
84 "<st.input_uses[2]: <VL_MAXVL>>]), "
85 "<ld.outputs[0]: <I64*32>>: OFSet(["
86 "<add.input_uses[0]: <I64*32>>]), "
87 "<li.outputs[0]: <I64*32>>: OFSet(["
88 "<add.input_uses[1]: <I64*32>>]), "
89 "<ca.outputs[0]: <CA>>: OFSet([<add.input_uses[2]: <CA>>]), "
90 "<add.outputs[0]: <I64*32>>: OFSet(["
91 "<st.input_uses[0]: <I64*32>>]), "
92 "<add.outputs[1]: <CA>>: OFSet()})"
93 )
94 self.assertEqual(
95 repr(fn_analysis.op_indexes),
96 "FMap({"
97 "Op(kind=OpKind.FuncArgR3, input_vals=[], input_uses=(), "
98 "immediates=[], outputs=(<arg.outputs[0]: <I64>>,), "
99 "name='arg'): 0, "
100 "Op(kind=OpKind.SetVLI, input_vals=[], input_uses=(), "
101 "immediates=[32], outputs=(<vl.outputs[0]: <VL_MAXVL>>,), "
102 "name='vl'): 1, "
103 "Op(kind=OpKind.SvLd, input_vals=["
104 "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>], "
105 "input_uses=(<ld.input_uses[0]: <I64>>, "
106 "<ld.input_uses[1]: <VL_MAXVL>>), immediates=[0], "
107 "outputs=(<ld.outputs[0]: <I64*32>>,), name='ld'): 2, "
108 "Op(kind=OpKind.SvLI, input_vals=[<vl.outputs[0]: <VL_MAXVL>>], "
109 "input_uses=(<li.input_uses[0]: <VL_MAXVL>>,), immediates=[0], "
110 "outputs=(<li.outputs[0]: <I64*32>>,), name='li'): 3, "
111 "Op(kind=OpKind.SetCA, input_vals=[], input_uses=(), "
112 "immediates=[], outputs=(<ca.outputs[0]: <CA>>,), name='ca'): 4, "
113 "Op(kind=OpKind.SvAddE, input_vals=["
114 "<ld.outputs[0]: <I64*32>>, <li.outputs[0]: <I64*32>>, "
115 "<ca.outputs[0]: <CA>>, <vl.outputs[0]: <VL_MAXVL>>], "
116 "input_uses=(<add.input_uses[0]: <I64*32>>, "
117 "<add.input_uses[1]: <I64*32>>, <add.input_uses[2]: <CA>>, "
118 "<add.input_uses[3]: <VL_MAXVL>>), immediates=[], outputs=("
119 "<add.outputs[0]: <I64*32>>, <add.outputs[1]: <CA>>), "
120 "name='add'): 5, "
121 "Op(kind=OpKind.SvStd, input_vals=["
122 "<add.outputs[0]: <I64*32>>, <arg.outputs[0]: <I64>>, "
123 "<vl.outputs[0]: <VL_MAXVL>>], "
124 "input_uses=(<st.input_uses[0]: <I64*32>>, "
125 "<st.input_uses[1]: <I64>>, <st.input_uses[2]: <VL_MAXVL>>), "
126 "immediates=[0], outputs=(), name='st'): 6})"
127 )
128 self.assertEqual(
129 repr(fn_analysis.live_ranges),
130 "FMap({"
131 "<arg.outputs[0]: <I64>>: <range:ops[0]:Early..ops[6]:Late>, "
132 "<vl.outputs[0]: <VL_MAXVL>>: <range:ops[1]:Late..ops[6]:Late>, "
133 "<ld.outputs[0]: <I64*32>>: <range:ops[2]:Early..ops[5]:Late>, "
134 "<li.outputs[0]: <I64*32>>: <range:ops[3]:Early..ops[5]:Late>, "
135 "<ca.outputs[0]: <CA>>: <range:ops[4]:Late..ops[5]:Late>, "
136 "<add.outputs[0]: <I64*32>>: <range:ops[5]:Early..ops[6]:Late>, "
137 "<add.outputs[1]: <CA>>: <range:ops[5]:Early..ops[6]:Early>})"
138 )
139 self.assertEqual(
140 repr(fn_analysis.live_at),
141 "FMap({"
142 "<ops[0]:Early>: OFSet([<arg.outputs[0]: <I64>>]), "
143 "<ops[0]:Late>: OFSet([<arg.outputs[0]: <I64>>]), "
144 "<ops[1]:Early>: OFSet([<arg.outputs[0]: <I64>>]), "
145 "<ops[1]:Late>: OFSet(["
146 "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>]), "
147 "<ops[2]:Early>: OFSet(["
148 "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, "
149 "<ld.outputs[0]: <I64*32>>]), "
150 "<ops[2]:Late>: OFSet(["
151 "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, "
152 "<ld.outputs[0]: <I64*32>>]), "
153 "<ops[3]:Early>: OFSet(["
154 "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, "
155 "<ld.outputs[0]: <I64*32>>, <li.outputs[0]: <I64*32>>]), "
156 "<ops[3]:Late>: OFSet(["
157 "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, "
158 "<ld.outputs[0]: <I64*32>>, <li.outputs[0]: <I64*32>>]), "
159 "<ops[4]:Early>: OFSet(["
160 "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, "
161 "<ld.outputs[0]: <I64*32>>, <li.outputs[0]: <I64*32>>]), "
162 "<ops[4]:Late>: OFSet(["
163 "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, "
164 "<ld.outputs[0]: <I64*32>>, <li.outputs[0]: <I64*32>>, "
165 "<ca.outputs[0]: <CA>>]), "
166 "<ops[5]:Early>: OFSet(["
167 "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, "
168 "<ld.outputs[0]: <I64*32>>, <li.outputs[0]: <I64*32>>, "
169 "<ca.outputs[0]: <CA>>, <add.outputs[0]: <I64*32>>, "
170 "<add.outputs[1]: <CA>>]), "
171 "<ops[5]:Late>: OFSet(["
172 "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, "
173 "<add.outputs[0]: <I64*32>>, <add.outputs[1]: <CA>>]), "
174 "<ops[6]:Early>: OFSet(["
175 "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, "
176 "<add.outputs[0]: <I64*32>>]), "
177 "<ops[6]:Late>: OFSet()})"
178 )
179 self.assertEqual(
180 repr(fn_analysis.def_program_ranges),
181 "FMap({"
182 "<arg.outputs[0]: <I64>>: <range:ops[0]:Early..ops[1]:Early>, "
183 "<vl.outputs[0]: <VL_MAXVL>>: <range:ops[1]:Late..ops[2]:Early>, "
184 "<ld.outputs[0]: <I64*32>>: <range:ops[2]:Early..ops[3]:Early>, "
185 "<li.outputs[0]: <I64*32>>: <range:ops[3]:Early..ops[4]:Early>, "
186 "<ca.outputs[0]: <CA>>: <range:ops[4]:Late..ops[5]:Early>, "
187 "<add.outputs[0]: <I64*32>>: <range:ops[5]:Early..ops[6]:Early>, "
188 "<add.outputs[1]: <CA>>: <range:ops[5]:Early..ops[6]:Early>})"
189 )
190 self.assertEqual(
191 repr(fn_analysis.use_program_points),
192 "FMap({"
193 "<ld.input_uses[0]: <I64>>: <ops[2]:Early>, "
194 "<ld.input_uses[1]: <VL_MAXVL>>: <ops[2]:Early>, "
195 "<li.input_uses[0]: <VL_MAXVL>>: <ops[3]:Early>, "
196 "<add.input_uses[0]: <I64*32>>: <ops[5]:Early>, "
197 "<add.input_uses[1]: <I64*32>>: <ops[5]:Early>, "
198 "<add.input_uses[2]: <CA>>: <ops[5]:Early>, "
199 "<add.input_uses[3]: <VL_MAXVL>>: <ops[5]:Early>, "
200 "<st.input_uses[0]: <I64*32>>: <ops[6]:Early>, "
201 "<st.input_uses[1]: <I64>>: <ops[6]:Early>, "
202 "<st.input_uses[2]: <VL_MAXVL>>: <ops[6]:Early>})"
203 )
204 self.assertEqual(
205 repr(fn_analysis.all_program_points),
206 "<range:ops[0]:Early..ops[7]:Early>")
207
208 def test_repr(self):
209 fn, _arg = self.make_add_fn()
210 self.assertEqual([repr(i) for i in fn.ops], [
211 "Op(kind=OpKind.FuncArgR3, "
212 "input_vals=[], "
213 "input_uses=(), "
214 "immediates=[], "
215 "outputs=(<arg.outputs[0]: <I64>>,), name='arg')",
216 "Op(kind=OpKind.SetVLI, "
217 "input_vals=[], "
218 "input_uses=(), "
219 "immediates=[32], "
220 "outputs=(<vl.outputs[0]: <VL_MAXVL>>,), name='vl')",
221 "Op(kind=OpKind.SvLd, "
222 "input_vals=[<arg.outputs[0]: <I64>>, "
223 "<vl.outputs[0]: <VL_MAXVL>>], "
224 "input_uses=(<ld.input_uses[0]: <I64>>, "
225 "<ld.input_uses[1]: <VL_MAXVL>>), "
226 "immediates=[0], "
227 "outputs=(<ld.outputs[0]: <I64*32>>,), name='ld')",
228 "Op(kind=OpKind.SvLI, "
229 "input_vals=[<vl.outputs[0]: <VL_MAXVL>>], "
230 "input_uses=(<li.input_uses[0]: <VL_MAXVL>>,), "
231 "immediates=[0], "
232 "outputs=(<li.outputs[0]: <I64*32>>,), name='li')",
233 "Op(kind=OpKind.SetCA, "
234 "input_vals=[], "
235 "input_uses=(), "
236 "immediates=[], "
237 "outputs=(<ca.outputs[0]: <CA>>,), name='ca')",
238 "Op(kind=OpKind.SvAddE, "
239 "input_vals=[<ld.outputs[0]: <I64*32>>, "
240 "<li.outputs[0]: <I64*32>>, <ca.outputs[0]: <CA>>, "
241 "<vl.outputs[0]: <VL_MAXVL>>], "
242 "input_uses=(<add.input_uses[0]: <I64*32>>, "
243 "<add.input_uses[1]: <I64*32>>, <add.input_uses[2]: <CA>>, "
244 "<add.input_uses[3]: <VL_MAXVL>>), "
245 "immediates=[], "
246 "outputs=(<add.outputs[0]: <I64*32>>, <add.outputs[1]: <CA>>), "
247 "name='add')",
248 "Op(kind=OpKind.SvStd, "
249 "input_vals=[<add.outputs[0]: <I64*32>>, <arg.outputs[0]: <I64>>, "
250 "<vl.outputs[0]: <VL_MAXVL>>], "
251 "input_uses=(<st.input_uses[0]: <I64*32>>, "
252 "<st.input_uses[1]: <I64>>, <st.input_uses[2]: <VL_MAXVL>>), "
253 "immediates=[0], "
254 "outputs=(), name='st')",
255 ])
256 self.assertEqual([repr(op.properties) for op in fn.ops], [
257 "OpProperties(kind=OpKind.FuncArgR3, "
258 "inputs=(), "
259 "outputs=("
260 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
261 "LocKind.GPR: FBitSet([3])}), ty=<I64>), "
262 "tied_input_index=None, spread_index=None, "
263 "write_stage=OpStage.Early),), maxvl=1)",
264 "OpProperties(kind=OpKind.SetVLI, "
265 "inputs=(), "
266 "outputs=("
267 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
268 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
269 "tied_input_index=None, spread_index=None, "
270 "write_stage=OpStage.Late),), maxvl=1)",
271 "OpProperties(kind=OpKind.SvLd, "
272 "inputs=("
273 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
274 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
275 "ty=<I64>), "
276 "tied_input_index=None, spread_index=None, "
277 "write_stage=OpStage.Early), "
278 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
279 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
280 "tied_input_index=None, spread_index=None, "
281 "write_stage=OpStage.Early)), "
282 "outputs=("
283 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
284 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
285 "tied_input_index=None, spread_index=None, "
286 "write_stage=OpStage.Early),), maxvl=32)",
287 "OpProperties(kind=OpKind.SvLI, "
288 "inputs=("
289 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
290 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
291 "tied_input_index=None, spread_index=None, "
292 "write_stage=OpStage.Early),), "
293 "outputs=("
294 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
295 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
296 "tied_input_index=None, spread_index=None, "
297 "write_stage=OpStage.Early),), maxvl=32)",
298 "OpProperties(kind=OpKind.SetCA, "
299 "inputs=(), "
300 "outputs=("
301 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
302 "LocKind.CA: FBitSet([0])}), ty=<CA>), "
303 "tied_input_index=None, spread_index=None, "
304 "write_stage=OpStage.Late),), maxvl=1)",
305 "OpProperties(kind=OpKind.SvAddE, "
306 "inputs=("
307 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
308 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
309 "tied_input_index=None, spread_index=None, "
310 "write_stage=OpStage.Early), "
311 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
312 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
313 "tied_input_index=None, spread_index=None, "
314 "write_stage=OpStage.Early), "
315 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
316 "LocKind.CA: FBitSet([0])}), ty=<CA>), "
317 "tied_input_index=None, spread_index=None, "
318 "write_stage=OpStage.Early), "
319 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
320 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
321 "tied_input_index=None, spread_index=None, "
322 "write_stage=OpStage.Early)), "
323 "outputs=("
324 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
325 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
326 "tied_input_index=None, spread_index=None, "
327 "write_stage=OpStage.Early), "
328 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
329 "LocKind.CA: FBitSet([0])}), ty=<CA>), "
330 "tied_input_index=2, spread_index=None, "
331 "write_stage=OpStage.Early)), maxvl=32)",
332 "OpProperties(kind=OpKind.SvStd, "
333 "inputs=("
334 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
335 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
336 "tied_input_index=None, spread_index=None, "
337 "write_stage=OpStage.Early), "
338 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
339 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
340 "ty=<I64>), "
341 "tied_input_index=None, spread_index=None, "
342 "write_stage=OpStage.Early), "
343 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
344 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
345 "tied_input_index=None, spread_index=None, "
346 "write_stage=OpStage.Early)), "
347 "outputs=(), maxvl=32)",
348 ])
349
350 def test_pre_ra_insert_copies(self):
351 fn, _arg = self.make_add_fn()
352 fn.pre_ra_insert_copies()
353 self.assertEqual([repr(i) for i in fn.ops], [
354 "Op(kind=OpKind.FuncArgR3, "
355 "input_vals=[], "
356 "input_uses=(), "
357 "immediates=[], "
358 "outputs=(<arg.outputs[0]: <I64>>,), name='arg')",
359 "Op(kind=OpKind.CopyFromReg, "
360 "input_vals=[<arg.outputs[0]: <I64>>], "
361 "input_uses=(<arg.out0.copy.input_uses[0]: <I64>>,), "
362 "immediates=[], "
363 "outputs=(<arg.out0.copy.outputs[0]: <I64>>,), "
364 "name='arg.out0.copy')",
365 "Op(kind=OpKind.SetVLI, "
366 "input_vals=[], "
367 "input_uses=(), "
368 "immediates=[32], "
369 "outputs=(<vl.outputs[0]: <VL_MAXVL>>,), name='vl')",
370 "Op(kind=OpKind.CopyToReg, "
371 "input_vals=[<arg.out0.copy.outputs[0]: <I64>>], "
372 "input_uses=(<ld.inp0.copy.input_uses[0]: <I64>>,), "
373 "immediates=[], "
374 "outputs=(<ld.inp0.copy.outputs[0]: <I64>>,), name='ld.inp0.copy')",
375 "Op(kind=OpKind.SetVLI, "
376 "input_vals=[], "
377 "input_uses=(), "
378 "immediates=[32], "
379 "outputs=(<ld.inp1.setvl.outputs[0]: <VL_MAXVL>>,), "
380 "name='ld.inp1.setvl')",
381 "Op(kind=OpKind.SvLd, "
382 "input_vals=[<ld.inp0.copy.outputs[0]: <I64>>, "
383 "<ld.inp1.setvl.outputs[0]: <VL_MAXVL>>], "
384 "input_uses=(<ld.input_uses[0]: <I64>>, "
385 "<ld.input_uses[1]: <VL_MAXVL>>), "
386 "immediates=[0], "
387 "outputs=(<ld.outputs[0]: <I64*32>>,), name='ld')",
388 "Op(kind=OpKind.SetVLI, "
389 "input_vals=[], "
390 "input_uses=(), "
391 "immediates=[32], "
392 "outputs=(<ld.out0.setvl.outputs[0]: <VL_MAXVL>>,), "
393 "name='ld.out0.setvl')",
394 "Op(kind=OpKind.VecCopyFromReg, "
395 "input_vals=[<ld.outputs[0]: <I64*32>>, "
396 "<ld.out0.setvl.outputs[0]: <VL_MAXVL>>], "
397 "input_uses=(<ld.out0.copy.input_uses[0]: <I64*32>>, "
398 "<ld.out0.copy.input_uses[1]: <VL_MAXVL>>), "
399 "immediates=[], "
400 "outputs=(<ld.out0.copy.outputs[0]: <I64*32>>,), "
401 "name='ld.out0.copy')",
402 "Op(kind=OpKind.SetVLI, "
403 "input_vals=[], "
404 "input_uses=(), "
405 "immediates=[32], "
406 "outputs=(<li.inp0.setvl.outputs[0]: <VL_MAXVL>>,), "
407 "name='li.inp0.setvl')",
408 "Op(kind=OpKind.SvLI, "
409 "input_vals=[<li.inp0.setvl.outputs[0]: <VL_MAXVL>>], "
410 "input_uses=(<li.input_uses[0]: <VL_MAXVL>>,), "
411 "immediates=[0], "
412 "outputs=(<li.outputs[0]: <I64*32>>,), name='li')",
413 "Op(kind=OpKind.SetVLI, "
414 "input_vals=[], "
415 "input_uses=(), "
416 "immediates=[32], "
417 "outputs=(<li.out0.setvl.outputs[0]: <VL_MAXVL>>,), "
418 "name='li.out0.setvl')",
419 "Op(kind=OpKind.VecCopyFromReg, "
420 "input_vals=[<li.outputs[0]: <I64*32>>, "
421 "<li.out0.setvl.outputs[0]: <VL_MAXVL>>], "
422 "input_uses=(<li.out0.copy.input_uses[0]: <I64*32>>, "
423 "<li.out0.copy.input_uses[1]: <VL_MAXVL>>), "
424 "immediates=[], "
425 "outputs=(<li.out0.copy.outputs[0]: <I64*32>>,), "
426 "name='li.out0.copy')",
427 "Op(kind=OpKind.SetCA, "
428 "input_vals=[], "
429 "input_uses=(), "
430 "immediates=[], "
431 "outputs=(<ca.outputs[0]: <CA>>,), name='ca')",
432 "Op(kind=OpKind.SetVLI, "
433 "input_vals=[], "
434 "input_uses=(), "
435 "immediates=[32], "
436 "outputs=(<add.inp0.setvl.outputs[0]: <VL_MAXVL>>,), "
437 "name='add.inp0.setvl')",
438 "Op(kind=OpKind.VecCopyToReg, "
439 "input_vals=[<ld.out0.copy.outputs[0]: <I64*32>>, "
440 "<add.inp0.setvl.outputs[0]: <VL_MAXVL>>], "
441 "input_uses=(<add.inp0.copy.input_uses[0]: <I64*32>>, "
442 "<add.inp0.copy.input_uses[1]: <VL_MAXVL>>), "
443 "immediates=[], "
444 "outputs=(<add.inp0.copy.outputs[0]: <I64*32>>,), "
445 "name='add.inp0.copy')",
446 "Op(kind=OpKind.SetVLI, "
447 "input_vals=[], "
448 "input_uses=(), "
449 "immediates=[32], "
450 "outputs=(<add.inp1.setvl.outputs[0]: <VL_MAXVL>>,), "
451 "name='add.inp1.setvl')",
452 "Op(kind=OpKind.VecCopyToReg, "
453 "input_vals=[<li.out0.copy.outputs[0]: <I64*32>>, "
454 "<add.inp1.setvl.outputs[0]: <VL_MAXVL>>], "
455 "input_uses=(<add.inp1.copy.input_uses[0]: <I64*32>>, "
456 "<add.inp1.copy.input_uses[1]: <VL_MAXVL>>), "
457 "immediates=[], "
458 "outputs=(<add.inp1.copy.outputs[0]: <I64*32>>,), "
459 "name='add.inp1.copy')",
460 "Op(kind=OpKind.SetVLI, "
461 "input_vals=[], "
462 "input_uses=(), "
463 "immediates=[32], "
464 "outputs=(<add.inp3.setvl.outputs[0]: <VL_MAXVL>>,), "
465 "name='add.inp3.setvl')",
466 "Op(kind=OpKind.SvAddE, "
467 "input_vals=[<add.inp0.copy.outputs[0]: <I64*32>>, "
468 "<add.inp1.copy.outputs[0]: <I64*32>>, <ca.outputs[0]: <CA>>, "
469 "<add.inp3.setvl.outputs[0]: <VL_MAXVL>>], "
470 "input_uses=(<add.input_uses[0]: <I64*32>>, "
471 "<add.input_uses[1]: <I64*32>>, <add.input_uses[2]: <CA>>, "
472 "<add.input_uses[3]: <VL_MAXVL>>), "
473 "immediates=[], "
474 "outputs=(<add.outputs[0]: <I64*32>>, <add.outputs[1]: <CA>>), "
475 "name='add')",
476 "Op(kind=OpKind.SetVLI, "
477 "input_vals=[], "
478 "input_uses=(), "
479 "immediates=[32], "
480 "outputs=(<add.out0.setvl.outputs[0]: <VL_MAXVL>>,), "
481 "name='add.out0.setvl')",
482 "Op(kind=OpKind.VecCopyFromReg, "
483 "input_vals=[<add.outputs[0]: <I64*32>>, "
484 "<add.out0.setvl.outputs[0]: <VL_MAXVL>>], "
485 "input_uses=(<add.out0.copy.input_uses[0]: <I64*32>>, "
486 "<add.out0.copy.input_uses[1]: <VL_MAXVL>>), "
487 "immediates=[], "
488 "outputs=(<add.out0.copy.outputs[0]: <I64*32>>,), "
489 "name='add.out0.copy')",
490 "Op(kind=OpKind.SetVLI, "
491 "input_vals=[], "
492 "input_uses=(), "
493 "immediates=[32], "
494 "outputs=(<st.inp0.setvl.outputs[0]: <VL_MAXVL>>,), "
495 "name='st.inp0.setvl')",
496 "Op(kind=OpKind.VecCopyToReg, "
497 "input_vals=[<add.out0.copy.outputs[0]: <I64*32>>, "
498 "<st.inp0.setvl.outputs[0]: <VL_MAXVL>>], "
499 "input_uses=(<st.inp0.copy.input_uses[0]: <I64*32>>, "
500 "<st.inp0.copy.input_uses[1]: <VL_MAXVL>>), "
501 "immediates=[], "
502 "outputs=(<st.inp0.copy.outputs[0]: <I64*32>>,), "
503 "name='st.inp0.copy')",
504 "Op(kind=OpKind.CopyToReg, "
505 "input_vals=[<arg.out0.copy.outputs[0]: <I64>>], "
506 "input_uses=(<st.inp1.copy.input_uses[0]: <I64>>,), "
507 "immediates=[], "
508 "outputs=(<st.inp1.copy.outputs[0]: <I64>>,), "
509 "name='st.inp1.copy')",
510 "Op(kind=OpKind.SetVLI, "
511 "input_vals=[], "
512 "input_uses=(), "
513 "immediates=[32], "
514 "outputs=(<st.inp2.setvl.outputs[0]: <VL_MAXVL>>,), "
515 "name='st.inp2.setvl')",
516 "Op(kind=OpKind.SvStd, "
517 "input_vals=[<st.inp0.copy.outputs[0]: <I64*32>>, "
518 "<st.inp1.copy.outputs[0]: <I64>>, "
519 "<st.inp2.setvl.outputs[0]: <VL_MAXVL>>], "
520 "input_uses=(<st.input_uses[0]: <I64*32>>, "
521 "<st.input_uses[1]: <I64>>, <st.input_uses[2]: <VL_MAXVL>>), "
522 "immediates=[0], "
523 "outputs=(), name='st')",
524 ])
525 self.assertEqual([repr(op.properties) for op in fn.ops], [
526 "OpProperties(kind=OpKind.FuncArgR3, "
527 "inputs=(), "
528 "outputs=("
529 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
530 "LocKind.GPR: FBitSet([3])}), ty=<I64>), "
531 "tied_input_index=None, spread_index=None, "
532 "write_stage=OpStage.Early),), maxvl=1)",
533 "OpProperties(kind=OpKind.CopyFromReg, "
534 "inputs=("
535 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
536 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
537 "ty=<I64>), "
538 "tied_input_index=None, spread_index=None, "
539 "write_stage=OpStage.Early),), "
540 "outputs=("
541 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
542 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)]), "
543 "LocKind.StackI64: FBitSet(range(0, 512))}), ty=<I64>), "
544 "tied_input_index=None, spread_index=None, "
545 "write_stage=OpStage.Late),), maxvl=1)",
546 "OpProperties(kind=OpKind.SetVLI, "
547 "inputs=(), "
548 "outputs=("
549 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
550 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
551 "tied_input_index=None, spread_index=None, "
552 "write_stage=OpStage.Late),), maxvl=1)",
553 "OpProperties(kind=OpKind.CopyToReg, "
554 "inputs=("
555 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
556 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)]), "
557 "LocKind.StackI64: FBitSet(range(0, 512))}), ty=<I64>), "
558 "tied_input_index=None, spread_index=None, "
559 "write_stage=OpStage.Early),), "
560 "outputs=("
561 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
562 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
563 "ty=<I64>), "
564 "tied_input_index=None, spread_index=None, "
565 "write_stage=OpStage.Late),), maxvl=1)",
566 "OpProperties(kind=OpKind.SetVLI, "
567 "inputs=(), "
568 "outputs=("
569 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
570 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
571 "tied_input_index=None, spread_index=None, "
572 "write_stage=OpStage.Late),), maxvl=1)",
573 "OpProperties(kind=OpKind.SvLd, "
574 "inputs=("
575 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
576 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
577 "ty=<I64>), "
578 "tied_input_index=None, spread_index=None, "
579 "write_stage=OpStage.Early), "
580 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
581 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
582 "tied_input_index=None, spread_index=None, "
583 "write_stage=OpStage.Early)), "
584 "outputs=("
585 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
586 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
587 "tied_input_index=None, spread_index=None, "
588 "write_stage=OpStage.Early),), maxvl=32)",
589 "OpProperties(kind=OpKind.SetVLI, "
590 "inputs=(), "
591 "outputs=("
592 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
593 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
594 "tied_input_index=None, spread_index=None, "
595 "write_stage=OpStage.Late),), maxvl=1)",
596 "OpProperties(kind=OpKind.VecCopyFromReg, "
597 "inputs=("
598 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
599 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
600 "tied_input_index=None, spread_index=None, "
601 "write_stage=OpStage.Early), "
602 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
603 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
604 "tied_input_index=None, spread_index=None, "
605 "write_stage=OpStage.Early)), "
606 "outputs=("
607 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
608 "LocKind.GPR: FBitSet(range(14, 97)), "
609 "LocKind.StackI64: FBitSet(range(0, 481))}), ty=<I64*32>), "
610 "tied_input_index=None, spread_index=None, "
611 "write_stage=OpStage.Late),), maxvl=32)",
612 "OpProperties(kind=OpKind.SetVLI, "
613 "inputs=(), "
614 "outputs=("
615 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
616 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
617 "tied_input_index=None, spread_index=None, "
618 "write_stage=OpStage.Late),), maxvl=1)",
619 "OpProperties(kind=OpKind.SvLI, "
620 "inputs=("
621 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
622 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
623 "tied_input_index=None, spread_index=None, "
624 "write_stage=OpStage.Early),), "
625 "outputs=("
626 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
627 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
628 "tied_input_index=None, spread_index=None, "
629 "write_stage=OpStage.Early),), maxvl=32)",
630 "OpProperties(kind=OpKind.SetVLI, "
631 "inputs=(), "
632 "outputs=("
633 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
634 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
635 "tied_input_index=None, spread_index=None, "
636 "write_stage=OpStage.Late),), maxvl=1)",
637 "OpProperties(kind=OpKind.VecCopyFromReg, "
638 "inputs=("
639 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
640 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
641 "tied_input_index=None, spread_index=None, "
642 "write_stage=OpStage.Early), "
643 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
644 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
645 "tied_input_index=None, spread_index=None, "
646 "write_stage=OpStage.Early)), "
647 "outputs=("
648 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
649 "LocKind.GPR: FBitSet(range(14, 97)), "
650 "LocKind.StackI64: FBitSet(range(0, 481))}), ty=<I64*32>), "
651 "tied_input_index=None, spread_index=None, "
652 "write_stage=OpStage.Late),), maxvl=32)",
653 "OpProperties(kind=OpKind.SetCA, "
654 "inputs=(), "
655 "outputs=("
656 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
657 "LocKind.CA: FBitSet([0])}), ty=<CA>), "
658 "tied_input_index=None, spread_index=None, "
659 "write_stage=OpStage.Late),), maxvl=1)",
660 "OpProperties(kind=OpKind.SetVLI, "
661 "inputs=(), "
662 "outputs=("
663 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
664 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
665 "tied_input_index=None, spread_index=None, "
666 "write_stage=OpStage.Late),), maxvl=1)",
667 "OpProperties(kind=OpKind.VecCopyToReg, "
668 "inputs=("
669 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
670 "LocKind.GPR: FBitSet(range(14, 97)), "
671 "LocKind.StackI64: FBitSet(range(0, 481))}), ty=<I64*32>), "
672 "tied_input_index=None, spread_index=None, "
673 "write_stage=OpStage.Early), "
674 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
675 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
676 "tied_input_index=None, spread_index=None, "
677 "write_stage=OpStage.Early)), "
678 "outputs=("
679 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
680 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
681 "tied_input_index=None, spread_index=None, "
682 "write_stage=OpStage.Late),), maxvl=32)",
683 "OpProperties(kind=OpKind.SetVLI, "
684 "inputs=(), "
685 "outputs=("
686 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
687 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
688 "tied_input_index=None, spread_index=None, "
689 "write_stage=OpStage.Late),), maxvl=1)",
690 "OpProperties(kind=OpKind.VecCopyToReg, "
691 "inputs=("
692 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
693 "LocKind.GPR: FBitSet(range(14, 97)), "
694 "LocKind.StackI64: FBitSet(range(0, 481))}), ty=<I64*32>), "
695 "tied_input_index=None, spread_index=None, "
696 "write_stage=OpStage.Early), "
697 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
698 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
699 "tied_input_index=None, spread_index=None, "
700 "write_stage=OpStage.Early)), "
701 "outputs=("
702 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
703 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
704 "tied_input_index=None, spread_index=None, "
705 "write_stage=OpStage.Late),), maxvl=32)",
706 "OpProperties(kind=OpKind.SetVLI, "
707 "inputs=(), "
708 "outputs=("
709 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
710 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
711 "tied_input_index=None, spread_index=None, "
712 "write_stage=OpStage.Late),), maxvl=1)",
713 "OpProperties(kind=OpKind.SvAddE, "
714 "inputs=("
715 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
716 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
717 "tied_input_index=None, spread_index=None, "
718 "write_stage=OpStage.Early), "
719 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
720 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
721 "tied_input_index=None, spread_index=None, "
722 "write_stage=OpStage.Early), "
723 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
724 "LocKind.CA: FBitSet([0])}), ty=<CA>), "
725 "tied_input_index=None, spread_index=None, "
726 "write_stage=OpStage.Early), "
727 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
728 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
729 "tied_input_index=None, spread_index=None, "
730 "write_stage=OpStage.Early)), "
731 "outputs=("
732 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
733 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
734 "tied_input_index=None, spread_index=None, "
735 "write_stage=OpStage.Early), "
736 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
737 "LocKind.CA: FBitSet([0])}), ty=<CA>), "
738 "tied_input_index=2, spread_index=None, "
739 "write_stage=OpStage.Early)), maxvl=32)",
740 "OpProperties(kind=OpKind.SetVLI, "
741 "inputs=(), "
742 "outputs=("
743 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
744 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
745 "tied_input_index=None, spread_index=None, "
746 "write_stage=OpStage.Late),), maxvl=1)",
747 "OpProperties(kind=OpKind.VecCopyFromReg, "
748 "inputs=("
749 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
750 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
751 "tied_input_index=None, spread_index=None, "
752 "write_stage=OpStage.Early), "
753 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
754 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
755 "tied_input_index=None, spread_index=None, "
756 "write_stage=OpStage.Early)), "
757 "outputs=("
758 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
759 "LocKind.GPR: FBitSet(range(14, 97)), "
760 "LocKind.StackI64: FBitSet(range(0, 481))}), ty=<I64*32>), "
761 "tied_input_index=None, spread_index=None, "
762 "write_stage=OpStage.Late),), maxvl=32)",
763 "OpProperties(kind=OpKind.SetVLI, "
764 "inputs=(), "
765 "outputs=("
766 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
767 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
768 "tied_input_index=None, spread_index=None, "
769 "write_stage=OpStage.Late),), maxvl=1)",
770 "OpProperties(kind=OpKind.VecCopyToReg, "
771 "inputs=("
772 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
773 "LocKind.GPR: FBitSet(range(14, 97)), "
774 "LocKind.StackI64: FBitSet(range(0, 481))}), ty=<I64*32>), "
775 "tied_input_index=None, spread_index=None, "
776 "write_stage=OpStage.Early), "
777 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
778 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
779 "tied_input_index=None, spread_index=None, "
780 "write_stage=OpStage.Early)), "
781 "outputs=("
782 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
783 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
784 "tied_input_index=None, spread_index=None, "
785 "write_stage=OpStage.Late),), maxvl=32)",
786 "OpProperties(kind=OpKind.CopyToReg, "
787 "inputs=("
788 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
789 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)]), "
790 "LocKind.StackI64: FBitSet(range(0, 512))}), ty=<I64>), "
791 "tied_input_index=None, spread_index=None, "
792 "write_stage=OpStage.Early),), "
793 "outputs=("
794 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
795 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
796 "ty=<I64>), "
797 "tied_input_index=None, spread_index=None, "
798 "write_stage=OpStage.Late),), maxvl=1)",
799 "OpProperties(kind=OpKind.SetVLI, "
800 "inputs=(), "
801 "outputs=("
802 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
803 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
804 "tied_input_index=None, spread_index=None, "
805 "write_stage=OpStage.Late),), maxvl=1)",
806 "OpProperties(kind=OpKind.SvStd, "
807 "inputs=("
808 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
809 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
810 "tied_input_index=None, spread_index=None, "
811 "write_stage=OpStage.Early), "
812 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
813 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
814 "ty=<I64>), "
815 "tied_input_index=None, spread_index=None, "
816 "write_stage=OpStage.Early), "
817 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
818 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
819 "tied_input_index=None, spread_index=None, "
820 "write_stage=OpStage.Early)), "
821 "outputs=(), maxvl=32)",
822 ])
823
824 def test_sim(self):
825 fn, arg = self.make_add_fn()
826 addr = 0x100
827 state = PreRASimState(ssa_vals={arg: (addr,)}, memory={})
828 state.store(addr=addr, value=0xffffffff_ffffffff,
829 size_in_bytes=GPR_SIZE_IN_BYTES)
830 state.store(addr=addr + GPR_SIZE_IN_BYTES, value=0xabcdef01_23456789,
831 size_in_bytes=GPR_SIZE_IN_BYTES)
832 self.assertEqual(
833 repr(state),
834 "PreRASimState(memory={\n"
835 "0x00100: <0xffffffffffffffff>,\n"
836 "0x00108: <0xabcdef0123456789>}, "
837 "ssa_vals={<arg.outputs[0]: <I64>>: (0x100,)})")
838 fn.sim(state)
839 self.assertEqual(
840 repr(state),
841 "PreRASimState(memory={\n"
842 "0x00100: <0x0000000000000000>,\n"
843 "0x00108: <0xabcdef012345678a>,\n"
844 "0x00110: <0x0000000000000000>,\n"
845 "0x00118: <0x0000000000000000>,\n"
846 "0x00120: <0x0000000000000000>,\n"
847 "0x00128: <0x0000000000000000>,\n"
848 "0x00130: <0x0000000000000000>,\n"
849 "0x00138: <0x0000000000000000>,\n"
850 "0x00140: <0x0000000000000000>,\n"
851 "0x00148: <0x0000000000000000>,\n"
852 "0x00150: <0x0000000000000000>,\n"
853 "0x00158: <0x0000000000000000>,\n"
854 "0x00160: <0x0000000000000000>,\n"
855 "0x00168: <0x0000000000000000>,\n"
856 "0x00170: <0x0000000000000000>,\n"
857 "0x00178: <0x0000000000000000>,\n"
858 "0x00180: <0x0000000000000000>,\n"
859 "0x00188: <0x0000000000000000>,\n"
860 "0x00190: <0x0000000000000000>,\n"
861 "0x00198: <0x0000000000000000>,\n"
862 "0x001a0: <0x0000000000000000>,\n"
863 "0x001a8: <0x0000000000000000>,\n"
864 "0x001b0: <0x0000000000000000>,\n"
865 "0x001b8: <0x0000000000000000>,\n"
866 "0x001c0: <0x0000000000000000>,\n"
867 "0x001c8: <0x0000000000000000>,\n"
868 "0x001d0: <0x0000000000000000>,\n"
869 "0x001d8: <0x0000000000000000>,\n"
870 "0x001e0: <0x0000000000000000>,\n"
871 "0x001e8: <0x0000000000000000>,\n"
872 "0x001f0: <0x0000000000000000>,\n"
873 "0x001f8: <0x0000000000000000>}, ssa_vals={\n"
874 "<arg.outputs[0]: <I64>>: (0x100,),\n"
875 "<vl.outputs[0]: <VL_MAXVL>>: (0x20,),\n"
876 "<ld.outputs[0]: <I64*32>>: (\n"
877 " 0xffffffffffffffff, 0xabcdef0123456789, 0x0, 0x0,\n"
878 " 0x0, 0x0, 0x0, 0x0,\n"
879 " 0x0, 0x0, 0x0, 0x0,\n"
880 " 0x0, 0x0, 0x0, 0x0,\n"
881 " 0x0, 0x0, 0x0, 0x0,\n"
882 " 0x0, 0x0, 0x0, 0x0,\n"
883 " 0x0, 0x0, 0x0, 0x0,\n"
884 " 0x0, 0x0, 0x0, 0x0),\n"
885 "<li.outputs[0]: <I64*32>>: (\n"
886 " 0x0, 0x0, 0x0, 0x0,\n"
887 " 0x0, 0x0, 0x0, 0x0,\n"
888 " 0x0, 0x0, 0x0, 0x0,\n"
889 " 0x0, 0x0, 0x0, 0x0,\n"
890 " 0x0, 0x0, 0x0, 0x0,\n"
891 " 0x0, 0x0, 0x0, 0x0,\n"
892 " 0x0, 0x0, 0x0, 0x0,\n"
893 " 0x0, 0x0, 0x0, 0x0),\n"
894 "<ca.outputs[0]: <CA>>: (0x1,),\n"
895 "<add.outputs[0]: <I64*32>>: (\n"
896 " 0x0, 0xabcdef012345678a, 0x0, 0x0,\n"
897 " 0x0, 0x0, 0x0, 0x0,\n"
898 " 0x0, 0x0, 0x0, 0x0,\n"
899 " 0x0, 0x0, 0x0, 0x0,\n"
900 " 0x0, 0x0, 0x0, 0x0,\n"
901 " 0x0, 0x0, 0x0, 0x0,\n"
902 " 0x0, 0x0, 0x0, 0x0,\n"
903 " 0x0, 0x0, 0x0, 0x0),\n"
904 "<add.outputs[1]: <CA>>: (0x0,),\n"
905 "})")
906
907 def test_gen_asm(self):
908 fn, _arg = self.make_add_fn()
909 fn.pre_ra_insert_copies()
910 VL_LOC = Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1)
911 CA_LOC = Loc(kind=LocKind.CA, start=0, reg_len=1)
912 state = GenAsmState(allocated_locs={
913 fn.ops[0].outputs[0]: Loc(kind=LocKind.GPR, start=3, reg_len=1),
914 fn.ops[1].outputs[0]: Loc(kind=LocKind.GPR, start=3, reg_len=1),
915 fn.ops[2].outputs[0]: VL_LOC,
916 fn.ops[3].outputs[0]: Loc(kind=LocKind.GPR, start=3, reg_len=1),
917 fn.ops[4].outputs[0]: VL_LOC,
918 fn.ops[5].outputs[0]: Loc(kind=LocKind.GPR, start=32, reg_len=32),
919 fn.ops[6].outputs[0]: VL_LOC,
920 fn.ops[7].outputs[0]: Loc(kind=LocKind.GPR, start=32, reg_len=32),
921 fn.ops[8].outputs[0]: VL_LOC,
922 fn.ops[9].outputs[0]: Loc(kind=LocKind.GPR, start=64, reg_len=32),
923 fn.ops[10].outputs[0]: VL_LOC,
924 fn.ops[11].outputs[0]: Loc(kind=LocKind.GPR, start=64, reg_len=32),
925 fn.ops[12].outputs[0]: CA_LOC,
926 fn.ops[13].outputs[0]: VL_LOC,
927 fn.ops[14].outputs[0]: Loc(kind=LocKind.GPR, start=32, reg_len=32),
928 fn.ops[15].outputs[0]: VL_LOC,
929 fn.ops[16].outputs[0]: Loc(kind=LocKind.GPR, start=64, reg_len=32),
930 fn.ops[17].outputs[0]: VL_LOC,
931 fn.ops[18].outputs[0]: Loc(kind=LocKind.GPR, start=32, reg_len=32),
932 fn.ops[18].outputs[1]: CA_LOC,
933 fn.ops[19].outputs[0]: VL_LOC,
934 fn.ops[20].outputs[0]: Loc(kind=LocKind.GPR, start=32, reg_len=32),
935 fn.ops[21].outputs[0]: VL_LOC,
936 fn.ops[22].outputs[0]: Loc(kind=LocKind.GPR, start=32, reg_len=32),
937 fn.ops[23].outputs[0]: Loc(kind=LocKind.GPR, start=3, reg_len=1),
938 fn.ops[24].outputs[0]: VL_LOC,
939 })
940 fn.gen_asm(state)
941 self.assertEqual(state.output, [
942 'setvl 0, 0, 32, 0, 1, 1',
943 'setvl 0, 0, 32, 0, 1, 1',
944 'sv.ld *32, 0(3)',
945 'setvl 0, 0, 32, 0, 1, 1',
946 'setvl 0, 0, 32, 0, 1, 1',
947 'sv.addi *64, 0, 0',
948 'setvl 0, 0, 32, 0, 1, 1',
949 'subfc 0, 0, 0',
950 'setvl 0, 0, 32, 0, 1, 1',
951 'setvl 0, 0, 32, 0, 1, 1',
952 'setvl 0, 0, 32, 0, 1, 1',
953 'sv.adde *32, *32, *64',
954 'setvl 0, 0, 32, 0, 1, 1',
955 'setvl 0, 0, 32, 0, 1, 1',
956 'setvl 0, 0, 32, 0, 1, 1',
957 'sv.std *32, 0(3)',
958 ])
959
960 def test_spread(self):
961 fn = Fn()
962 maxvl = 4
963 vl = fn.append_new_op(OpKind.SetVLI, immediates=[maxvl],
964 name="vl", maxvl=maxvl).outputs[0]
965 li = fn.append_new_op(OpKind.SvLI, input_vals=[vl], immediates=[0],
966 name="li", maxvl=maxvl).outputs[0]
967 spread_op = fn.append_new_op(OpKind.Spread, input_vals=[li, vl],
968 name="spread", maxvl=maxvl)
969 self.assertEqual(spread_op.outputs[0].ty_before_spread,
970 Ty(base_ty=BaseTy.I64, reg_len=maxvl))
971 _concat = fn.append_new_op(
972 OpKind.Concat, input_vals=[*spread_op.outputs[::-1], vl],
973 name="concat", maxvl=maxvl)
974 self.assertEqual([repr(op.properties) for op in fn.ops], [
975 "OpProperties(kind=OpKind.SetVLI, inputs=("
976 "), outputs=("
977 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
978 "LocKind.VL_MAXVL: FBitSet([0])}), "
979 "ty=<VL_MAXVL>), tied_input_index=None, spread_index=None, "
980 "write_stage=OpStage.Late),"
981 "), maxvl=4)",
982 "OpProperties(kind=OpKind.SvLI, inputs=("
983 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
984 "LocKind.VL_MAXVL: FBitSet([0])}), "
985 "ty=<VL_MAXVL>), tied_input_index=None, spread_index=None, "
986 "write_stage=OpStage.Early),"
987 "), outputs=("
988 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
989 "LocKind.GPR: FBitSet([*range(3, 10), *range(14, 125)])}), "
990 "ty=<I64*4>), tied_input_index=None, spread_index=None, "
991 "write_stage=OpStage.Early),"
992 "), maxvl=4)",
993 "OpProperties(kind=OpKind.Spread, inputs=("
994 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
995 "LocKind.GPR: FBitSet([*range(3, 10), *range(14, 125)])}), "
996 "ty=<I64*4>), tied_input_index=None, spread_index=None, "
997 "write_stage=OpStage.Early), "
998 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
999 "LocKind.VL_MAXVL: FBitSet([0])}), "
1000 "ty=<VL_MAXVL>), tied_input_index=None, spread_index=None, "
1001 "write_stage=OpStage.Early)"
1002 "), outputs=("
1003 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
1004 "LocKind.GPR: FBitSet([*range(3, 10), *range(14, 125)])}), "
1005 "ty=<I64*4>), tied_input_index=None, spread_index=0, "
1006 "write_stage=OpStage.Late), "
1007 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
1008 "LocKind.GPR: FBitSet([*range(3, 10), *range(14, 125)])}), "
1009 "ty=<I64*4>), tied_input_index=None, spread_index=1, "
1010 "write_stage=OpStage.Late), "
1011 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
1012 "LocKind.GPR: FBitSet([*range(3, 10), *range(14, 125)])}), "
1013 "ty=<I64*4>), tied_input_index=None, spread_index=2, "
1014 "write_stage=OpStage.Late), "
1015 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
1016 "LocKind.GPR: FBitSet([*range(3, 10), *range(14, 125)])}), "
1017 "ty=<I64*4>), tied_input_index=None, spread_index=3, "
1018 "write_stage=OpStage.Late)"
1019 "), maxvl=4)",
1020 "OpProperties(kind=OpKind.Concat, inputs=("
1021 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
1022 "LocKind.GPR: FBitSet([*range(3, 10), *range(14, 125)])}), "
1023 "ty=<I64*4>), tied_input_index=None, spread_index=0, "
1024 "write_stage=OpStage.Early), "
1025 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
1026 "LocKind.GPR: FBitSet([*range(3, 10), *range(14, 125)])}), "
1027 "ty=<I64*4>), tied_input_index=None, spread_index=1, "
1028 "write_stage=OpStage.Early), "
1029 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
1030 "LocKind.GPR: FBitSet([*range(3, 10), *range(14, 125)])}), "
1031 "ty=<I64*4>), tied_input_index=None, spread_index=2, "
1032 "write_stage=OpStage.Early), "
1033 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
1034 "LocKind.GPR: FBitSet([*range(3, 10), *range(14, 125)])}), "
1035 "ty=<I64*4>), tied_input_index=None, spread_index=3, "
1036 "write_stage=OpStage.Early), "
1037 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
1038 "LocKind.VL_MAXVL: FBitSet([0])}), "
1039 "ty=<VL_MAXVL>), tied_input_index=None, spread_index=None, "
1040 "write_stage=OpStage.Early)"
1041 "), outputs=("
1042 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
1043 "LocKind.GPR: FBitSet([*range(3, 10), *range(14, 125)])}), "
1044 "ty=<I64*4>), tied_input_index=None, spread_index=None, "
1045 "write_stage=OpStage.Late),"
1046 "), maxvl=4)",
1047 ])
1048 self.assertEqual([repr(op) for op in fn.ops], [
1049 "Op(kind=OpKind.SetVLI, input_vals=["
1050 "], input_uses=("
1051 "), immediates=[4], outputs=("
1052 "<vl.outputs[0]: <VL_MAXVL>>,"
1053 "), name='vl')",
1054 "Op(kind=OpKind.SvLI, input_vals=["
1055 "<vl.outputs[0]: <VL_MAXVL>>"
1056 "], input_uses=("
1057 "<li.input_uses[0]: <VL_MAXVL>>,"
1058 "), immediates=[0], outputs=("
1059 "<li.outputs[0]: <I64*4>>,"
1060 "), name='li')",
1061 "Op(kind=OpKind.Spread, input_vals=["
1062 "<li.outputs[0]: <I64*4>>, "
1063 "<vl.outputs[0]: <VL_MAXVL>>"
1064 "], input_uses=("
1065 "<spread.input_uses[0]: <I64*4>>, "
1066 "<spread.input_uses[1]: <VL_MAXVL>>"
1067 "), immediates=[], outputs=("
1068 "<spread.outputs[0]: <I64>>, "
1069 "<spread.outputs[1]: <I64>>, "
1070 "<spread.outputs[2]: <I64>>, "
1071 "<spread.outputs[3]: <I64>>"
1072 "), name='spread')",
1073 "Op(kind=OpKind.Concat, input_vals=["
1074 "<spread.outputs[3]: <I64>>, "
1075 "<spread.outputs[2]: <I64>>, "
1076 "<spread.outputs[1]: <I64>>, "
1077 "<spread.outputs[0]: <I64>>, "
1078 "<vl.outputs[0]: <VL_MAXVL>>"
1079 "], input_uses=("
1080 "<concat.input_uses[0]: <I64>>, "
1081 "<concat.input_uses[1]: <I64>>, "
1082 "<concat.input_uses[2]: <I64>>, "
1083 "<concat.input_uses[3]: <I64>>, "
1084 "<concat.input_uses[4]: <VL_MAXVL>>"
1085 "), immediates=[], outputs=("
1086 "<concat.outputs[0]: <I64*4>>,"
1087 "), name='concat')",
1088 ])
1089
1090
1091 if __name__ == "__main__":
1092 _ = unittest.main()