src/bigint_presentation_code/_tests/test_compiler_ir2.py

   1 import unittest
   2
   3 from bigint_presentation_code.compiler_ir2 import (GPR_SIZE_IN_BYTES, Fn,
   4                                                    FnAnalysis, OpKind, OpStage,
   5                                                    PreRASimState, ProgramPoint,
   6                                                    SSAVal)
   7
   8
   9 class TestCompilerIR(unittest.TestCase):
  10     maxDiff = None
  11
  12     def test_program_point(self):
  13         # type: () -> None
  14         expected = []  # type: list[ProgramPoint]
  15         for op_index in range(5):
  16             for stage in OpStage:
  17                 expected.append(ProgramPoint(op_index=op_index, stage=stage))
  18
  19         for idx, pp in enumerate(expected):
  20             if idx + 1 < len(expected):
  21                 self.assertEqual(pp.next(), expected[idx + 1])
  22
  23         self.assertEqual(sorted(expected), expected)
  24
  25     def make_add_fn(self):
  26         # type: () -> tuple[Fn, SSAVal]
  27         fn = Fn()
  28         op0 = fn.append_new_op(OpKind.FuncArgR3, name="arg")
  29         arg = op0.outputs[0]
  30         MAXVL = 32
  31         op1 = fn.append_new_op(OpKind.SetVLI, immediates=[MAXVL], name="vl")
  32         vl = op1.outputs[0]
  33         op2 = fn.append_new_op(
  34             OpKind.SvLd, input_vals=[arg, vl], immediates=[0], maxvl=MAXVL,
  35             name="ld")
  36         a = op2.outputs[0]
  37         op3 = fn.append_new_op(OpKind.SvLI, input_vals=[vl], immediates=[0],
  38                                maxvl=MAXVL, name="li")
  39         b = op3.outputs[0]
  40         op4 = fn.append_new_op(OpKind.SetCA, name="ca")
  41         ca = op4.outputs[0]
  42         op5 = fn.append_new_op(
  43             OpKind.SvAddE, input_vals=[a, b, ca, vl], maxvl=MAXVL, name="add")
  44         s = op5.outputs[0]
  45         _ = fn.append_new_op(OpKind.SvStd, input_vals=[s, arg, vl],
  46                              immediates=[0], maxvl=MAXVL, name="st")
  47         return fn, arg
  48
  49     def test_fn_analysis(self):
  50         fn, _arg = self.make_add_fn()
  51         fn_analysis = FnAnalysis(fn)
  52         print(repr(fn_analysis))
  53         self.assertEqual(
  54             repr(fn_analysis),
  55             "FnAnalysis(fn=<Fn>, uses=FMap({"
  56             "<arg.outputs[0]: <I64>>: OFSet(["
  57             "<ld.input_uses[0]: <I64>>, <st.input_uses[1]: <I64>>]), "
  58             "<vl.outputs[0]: <VL_MAXVL>>: OFSet(["
  59             "<ld.input_uses[1]: <VL_MAXVL>>, <li.input_uses[0]: <VL_MAXVL>>, "
  60             "<add.input_uses[3]: <VL_MAXVL>>, "
  61             "<st.input_uses[2]: <VL_MAXVL>>]), "
  62             "<ld.outputs[0]: <I64*32>>: OFSet(["
  63             "<add.input_uses[0]: <I64*32>>]), "
  64             "<li.outputs[0]: <I64*32>>: OFSet(["
  65             "<add.input_uses[1]: <I64*32>>]), "
  66             "<ca.outputs[0]: <CA>>: OFSet([<add.input_uses[2]: <CA>>]), "
  67             "<add.outputs[0]: <I64*32>>: OFSet(["
  68             "<st.input_uses[0]: <I64*32>>]), "
  69             "<add.outputs[1]: <CA>>: OFSet()}), "
  70             "op_indexes=FMap({"
  71             "Op(kind=OpKind.FuncArgR3, input_vals=[], input_uses=(), "
  72             "immediates=[], outputs=(<arg.outputs[0]: <I64>>,), "
  73             "name='arg'): 0, "
  74             "Op(kind=OpKind.SetVLI, input_vals=[], input_uses=(), "
  75             "immediates=[32], outputs=(<vl.outputs[0]: <VL_MAXVL>>,), "
  76             "name='vl'): 1, "
  77             "Op(kind=OpKind.SvLd, input_vals=["
  78             "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>], "
  79             "input_uses=(<ld.input_uses[0]: <I64>>, "
  80             "<ld.input_uses[1]: <VL_MAXVL>>), immediates=[0], "
  81             "outputs=(<ld.outputs[0]: <I64*32>>,), name='ld'): 2, "
  82             "Op(kind=OpKind.SvLI, input_vals=[<vl.outputs[0]: <VL_MAXVL>>], "
  83             "input_uses=(<li.input_uses[0]: <VL_MAXVL>>,), immediates=[0], "
  84             "outputs=(<li.outputs[0]: <I64*32>>,), name='li'): 3, "
  85             "Op(kind=OpKind.SetCA, input_vals=[], input_uses=(), "
  86             "immediates=[], outputs=(<ca.outputs[0]: <CA>>,), name='ca'): 4, "
  87             "Op(kind=OpKind.SvAddE, input_vals=["
  88             "<ld.outputs[0]: <I64*32>>, <li.outputs[0]: <I64*32>>, "
  89             "<ca.outputs[0]: <CA>>, <vl.outputs[0]: <VL_MAXVL>>], "
  90             "input_uses=(<add.input_uses[0]: <I64*32>>, "
  91             "<add.input_uses[1]: <I64*32>>, <add.input_uses[2]: <CA>>, "
  92             "<add.input_uses[3]: <VL_MAXVL>>), immediates=[], outputs=("
  93             "<add.outputs[0]: <I64*32>>, <add.outputs[1]: <CA>>), "
  94             "name='add'): 5, "
  95             "Op(kind=OpKind.SvStd, input_vals=["
  96             "<add.outputs[0]: <I64*32>>, <arg.outputs[0]: <I64>>, "
  97             "<vl.outputs[0]: <VL_MAXVL>>], "
  98             "input_uses=(<st.input_uses[0]: <I64*32>>, "
  99             "<st.input_uses[1]: <I64>>, <st.input_uses[2]: <VL_MAXVL>>), "
 100             "immediates=[0], outputs=(), name='st'): 6}), "
 101             "live_ranges=FMap({"
 102             "<arg.outputs[0]: <I64>>: <range:ops[0]:Early..ops[6]:Late>, "
 103             "<vl.outputs[0]: <VL_MAXVL>>: <range:ops[1]:Late..ops[6]:Late>, "
 104             "<ld.outputs[0]: <I64*32>>: <range:ops[2]:Early..ops[5]:Late>, "
 105             "<li.outputs[0]: <I64*32>>: <range:ops[3]:Early..ops[5]:Late>, "
 106             "<ca.outputs[0]: <CA>>: <range:ops[4]:Late..ops[5]:Late>, "
 107             "<add.outputs[0]: <I64*32>>: <range:ops[5]:Early..ops[6]:Late>, "
 108             "<add.outputs[1]: <CA>>: <range:ops[5]:Early..ops[6]:Early>}), "
 109             "live_at=FMap({"
 110             "<ops[0]:Early>: OFSet([<arg.outputs[0]: <I64>>]), "
 111             "<ops[0]:Late>: OFSet([<arg.outputs[0]: <I64>>]), "
 112             "<ops[1]:Early>: OFSet([<arg.outputs[0]: <I64>>]), "
 113             "<ops[1]:Late>: OFSet(["
 114             "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>]), "
 115             "<ops[2]:Early>: OFSet(["
 116             "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, "
 117             "<ld.outputs[0]: <I64*32>>]), "
 118             "<ops[2]:Late>: OFSet(["
 119             "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, "
 120             "<ld.outputs[0]: <I64*32>>]), "
 121             "<ops[3]:Early>: OFSet(["
 122             "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, "
 123             "<ld.outputs[0]: <I64*32>>, <li.outputs[0]: <I64*32>>]), "
 124             "<ops[3]:Late>: OFSet(["
 125             "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, "
 126             "<ld.outputs[0]: <I64*32>>, <li.outputs[0]: <I64*32>>]), "
 127             "<ops[4]:Early>: OFSet(["
 128             "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, "
 129             "<ld.outputs[0]: <I64*32>>, <li.outputs[0]: <I64*32>>]), "
 130             "<ops[4]:Late>: OFSet(["
 131             "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, "
 132             "<ld.outputs[0]: <I64*32>>, <li.outputs[0]: <I64*32>>, "
 133             "<ca.outputs[0]: <CA>>]), "
 134             "<ops[5]:Early>: OFSet(["
 135             "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, "
 136             "<ld.outputs[0]: <I64*32>>, <li.outputs[0]: <I64*32>>, "
 137             "<ca.outputs[0]: <CA>>, <add.outputs[0]: <I64*32>>, "
 138             "<add.outputs[1]: <CA>>]), "
 139             "<ops[5]:Late>: OFSet(["
 140             "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, "
 141             "<add.outputs[0]: <I64*32>>, <add.outputs[1]: <CA>>]), "
 142             "<ops[6]:Early>: OFSet(["
 143             "<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>, "
 144             "<add.outputs[0]: <I64*32>>]), "
 145             "<ops[6]:Late>: OFSet()}), "
 146             "def_program_ranges=FMap({"
 147             "<arg.outputs[0]: <I64>>: <range:ops[0]:Early..ops[1]:Early>, "
 148             "<vl.outputs[0]: <VL_MAXVL>>: <range:ops[1]:Late..ops[2]:Early>, "
 149             "<ld.outputs[0]: <I64*32>>: <range:ops[2]:Early..ops[3]:Early>, "
 150             "<li.outputs[0]: <I64*32>>: <range:ops[3]:Early..ops[4]:Early>, "
 151             "<ca.outputs[0]: <CA>>: <range:ops[4]:Late..ops[5]:Early>, "
 152             "<add.outputs[0]: <I64*32>>: <range:ops[5]:Early..ops[6]:Early>, "
 153             "<add.outputs[1]: <CA>>: <range:ops[5]:Early..ops[6]:Early>}), "
 154             "use_program_points=FMap({"
 155             "<ld.input_uses[0]: <I64>>: <ops[2]:Early>, "
 156             "<ld.input_uses[1]: <VL_MAXVL>>: <ops[2]:Early>, "
 157             "<li.input_uses[0]: <VL_MAXVL>>: <ops[3]:Early>, "
 158             "<add.input_uses[0]: <I64*32>>: <ops[5]:Early>, "
 159             "<add.input_uses[1]: <I64*32>>: <ops[5]:Early>, "
 160             "<add.input_uses[2]: <CA>>: <ops[5]:Early>, "
 161             "<add.input_uses[3]: <VL_MAXVL>>: <ops[5]:Early>, "
 162             "<st.input_uses[0]: <I64*32>>: <ops[6]:Early>, "
 163             "<st.input_uses[1]: <I64>>: <ops[6]:Early>, "
 164             "<st.input_uses[2]: <VL_MAXVL>>: <ops[6]:Early>}), "
 165             "all_program_points=<range:ops[0]:Early..ops[7]:Early>)")
 166
 167     def test_repr(self):
 168         fn, _arg = self.make_add_fn()
 169         self.assertEqual([repr(i) for i in fn.ops], [
 170             "Op(kind=OpKind.FuncArgR3, "
 171             "input_vals=[], "
 172             "input_uses=(), "
 173             "immediates=[], "
 174             "outputs=(<arg.outputs[0]: <I64>>,), name='arg')",
 175             "Op(kind=OpKind.SetVLI, "
 176             "input_vals=[], "
 177             "input_uses=(), "
 178             "immediates=[32], "
 179             "outputs=(<vl.outputs[0]: <VL_MAXVL>>,), name='vl')",
 180             "Op(kind=OpKind.SvLd, "
 181             "input_vals=[<arg.outputs[0]: <I64>>, "
 182             "<vl.outputs[0]: <VL_MAXVL>>], "
 183             "input_uses=(<ld.input_uses[0]: <I64>>, "
 184             "<ld.input_uses[1]: <VL_MAXVL>>), "
 185             "immediates=[0], "
 186             "outputs=(<ld.outputs[0]: <I64*32>>,), name='ld')",
 187             "Op(kind=OpKind.SvLI, "
 188             "input_vals=[<vl.outputs[0]: <VL_MAXVL>>], "
 189             "input_uses=(<li.input_uses[0]: <VL_MAXVL>>,), "
 190             "immediates=[0], "
 191             "outputs=(<li.outputs[0]: <I64*32>>,), name='li')",
 192             "Op(kind=OpKind.SetCA, "
 193             "input_vals=[], "
 194             "input_uses=(), "
 195             "immediates=[], "
 196             "outputs=(<ca.outputs[0]: <CA>>,), name='ca')",
 197             "Op(kind=OpKind.SvAddE, "
 198             "input_vals=[<ld.outputs[0]: <I64*32>>, "
 199             "<li.outputs[0]: <I64*32>>, <ca.outputs[0]: <CA>>, "
 200             "<vl.outputs[0]: <VL_MAXVL>>], "
 201             "input_uses=(<add.input_uses[0]: <I64*32>>, "
 202             "<add.input_uses[1]: <I64*32>>, <add.input_uses[2]: <CA>>, "
 203             "<add.input_uses[3]: <VL_MAXVL>>), "
 204             "immediates=[], "
 205             "outputs=(<add.outputs[0]: <I64*32>>, <add.outputs[1]: <CA>>), "
 206             "name='add')",
 207             "Op(kind=OpKind.SvStd, "
 208             "input_vals=[<add.outputs[0]: <I64*32>>, <arg.outputs[0]: <I64>>, "
 209             "<vl.outputs[0]: <VL_MAXVL>>], "
 210             "input_uses=(<st.input_uses[0]: <I64*32>>, "
 211             "<st.input_uses[1]: <I64>>, <st.input_uses[2]: <VL_MAXVL>>), "
 212             "immediates=[0], "
 213             "outputs=(), name='st')",
 214         ])
 215         self.assertEqual([repr(op.properties) for op in fn.ops], [
 216             "OpProperties(kind=OpKind.FuncArgR3, "
 217             "inputs=(), "
 218             "outputs=("
 219             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 220             "LocKind.GPR: FBitSet([3])}), ty=<I64>), "
 221             "tied_input_index=None, spread_index=None, "
 222             "write_stage=OpStage.Early),), maxvl=1)",
 223             "OpProperties(kind=OpKind.SetVLI, "
 224             "inputs=(), "
 225             "outputs=("
 226             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 227             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 228             "tied_input_index=None, spread_index=None, "
 229             "write_stage=OpStage.Late),), maxvl=1)",
 230             "OpProperties(kind=OpKind.SvLd, "
 231             "inputs=("
 232             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 233             "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
 234             "ty=<I64>), "
 235             "tied_input_index=None, spread_index=None, "
 236             "write_stage=OpStage.Early), "
 237             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 238             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 239             "tied_input_index=None, spread_index=None, "
 240             "write_stage=OpStage.Early)), "
 241             "outputs=("
 242             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 243             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 244             "tied_input_index=None, spread_index=None, "
 245             "write_stage=OpStage.Early),), maxvl=32)",
 246             "OpProperties(kind=OpKind.SvLI, "
 247             "inputs=("
 248             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 249             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 250             "tied_input_index=None, spread_index=None, "
 251             "write_stage=OpStage.Early),), "
 252             "outputs=("
 253             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 254             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 255             "tied_input_index=None, spread_index=None, "
 256             "write_stage=OpStage.Early),), maxvl=32)",
 257             "OpProperties(kind=OpKind.SetCA, "
 258             "inputs=(), "
 259             "outputs=("
 260             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 261             "LocKind.CA: FBitSet([0])}), ty=<CA>), "
 262             "tied_input_index=None, spread_index=None, "
 263             "write_stage=OpStage.Late),), maxvl=1)",
 264             "OpProperties(kind=OpKind.SvAddE, "
 265             "inputs=("
 266             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 267             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 268             "tied_input_index=None, spread_index=None, "
 269             "write_stage=OpStage.Early), "
 270             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 271             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 272             "tied_input_index=None, spread_index=None, "
 273             "write_stage=OpStage.Early), "
 274             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 275             "LocKind.CA: FBitSet([0])}), ty=<CA>), "
 276             "tied_input_index=None, spread_index=None, "
 277             "write_stage=OpStage.Early), "
 278             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 279             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 280             "tied_input_index=None, spread_index=None, "
 281             "write_stage=OpStage.Early)), "
 282             "outputs=("
 283             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 284             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 285             "tied_input_index=None, spread_index=None, "
 286             "write_stage=OpStage.Early), "
 287             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 288             "LocKind.CA: FBitSet([0])}), ty=<CA>), "
 289             "tied_input_index=None, spread_index=None, "
 290             "write_stage=OpStage.Early)), maxvl=32)",
 291             "OpProperties(kind=OpKind.SvStd, "
 292             "inputs=("
 293             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 294             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 295             "tied_input_index=None, spread_index=None, "
 296             "write_stage=OpStage.Early), "
 297             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 298             "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
 299             "ty=<I64>), "
 300             "tied_input_index=None, spread_index=None, "
 301             "write_stage=OpStage.Early), "
 302             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 303             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 304             "tied_input_index=None, spread_index=None, "
 305             "write_stage=OpStage.Early)), "
 306             "outputs=(), maxvl=32)",
 307         ])
 308
 309     def test_pre_ra_insert_copies(self):
 310         fn, _arg = self.make_add_fn()
 311         fn.pre_ra_insert_copies()
 312         self.assertEqual([repr(i) for i in fn.ops], [
 313             "Op(kind=OpKind.FuncArgR3, "
 314             "input_vals=[], "
 315             "input_uses=(), "
 316             "immediates=[], "
 317             "outputs=(<arg.outputs[0]: <I64>>,), name='arg')",
 318             "Op(kind=OpKind.CopyFromReg, "
 319             "input_vals=[<arg.outputs[0]: <I64>>], "
 320             "input_uses=(<arg.out0.copy.input_uses[0]: <I64>>,), "
 321             "immediates=[], "
 322             "outputs=(<arg.out0.copy.outputs[0]: <I64>>,), "
 323             "name='arg.out0.copy')",
 324             "Op(kind=OpKind.SetVLI, "
 325             "input_vals=[], "
 326             "input_uses=(), "
 327             "immediates=[32], "
 328             "outputs=(<vl.outputs[0]: <VL_MAXVL>>,), name='vl')",
 329             "Op(kind=OpKind.CopyToReg, "
 330             "input_vals=[<arg.out0.copy.outputs[0]: <I64>>], "
 331             "input_uses=(<ld.inp0.copy.input_uses[0]: <I64>>,), "
 332             "immediates=[], "
 333             "outputs=(<ld.inp0.copy.outputs[0]: <I64>>,), name='ld.inp0.copy')",
 334             "Op(kind=OpKind.SvLd, "
 335             "input_vals=[<ld.inp0.copy.outputs[0]: <I64>>, "
 336             "<vl.outputs[0]: <VL_MAXVL>>], "
 337             "input_uses=(<ld.input_uses[0]: <I64>>, "
 338             "<ld.input_uses[1]: <VL_MAXVL>>), "
 339             "immediates=[0], "
 340             "outputs=(<ld.outputs[0]: <I64*32>>,), name='ld')",
 341             "Op(kind=OpKind.SetVLI, "
 342             "input_vals=[], "
 343             "input_uses=(), "
 344             "immediates=[32], "
 345             "outputs=(<ld.out0.setvl.outputs[0]: <VL_MAXVL>>,), "
 346             "name='ld.out0.setvl')",
 347             "Op(kind=OpKind.VecCopyFromReg, "
 348             "input_vals=[<ld.outputs[0]: <I64*32>>, "
 349             "<ld.out0.setvl.outputs[0]: <VL_MAXVL>>], "
 350             "input_uses=(<ld.out0.copy.input_uses[0]: <I64*32>>, "
 351             "<ld.out0.copy.input_uses[1]: <VL_MAXVL>>), "
 352             "immediates=[], "
 353             "outputs=(<ld.out0.copy.outputs[0]: <I64*32>>,), "
 354             "name='ld.out0.copy')",
 355             "Op(kind=OpKind.SvLI, "
 356             "input_vals=[<vl.outputs[0]: <VL_MAXVL>>], "
 357             "input_uses=(<li.input_uses[0]: <VL_MAXVL>>,), "
 358             "immediates=[0], "
 359             "outputs=(<li.outputs[0]: <I64*32>>,), name='li')",
 360             "Op(kind=OpKind.SetVLI, "
 361             "input_vals=[], "
 362             "input_uses=(), "
 363             "immediates=[32], "
 364             "outputs=(<li.out0.setvl.outputs[0]: <VL_MAXVL>>,), "
 365             "name='li.out0.setvl')",
 366             "Op(kind=OpKind.VecCopyFromReg, "
 367             "input_vals=[<li.outputs[0]: <I64*32>>, "
 368             "<li.out0.setvl.outputs[0]: <VL_MAXVL>>], "
 369             "input_uses=(<li.out0.copy.input_uses[0]: <I64*32>>, "
 370             "<li.out0.copy.input_uses[1]: <VL_MAXVL>>), "
 371             "immediates=[], "
 372             "outputs=(<li.out0.copy.outputs[0]: <I64*32>>,), "
 373             "name='li.out0.copy')",
 374             "Op(kind=OpKind.SetCA, "
 375             "input_vals=[], "
 376             "input_uses=(), "
 377             "immediates=[], "
 378             "outputs=(<ca.outputs[0]: <CA>>,), name='ca')",
 379             "Op(kind=OpKind.SetVLI, "
 380             "input_vals=[], "
 381             "input_uses=(), "
 382             "immediates=[32], "
 383             "outputs=(<add.inp0.setvl.outputs[0]: <VL_MAXVL>>,), "
 384             "name='add.inp0.setvl')",
 385             "Op(kind=OpKind.VecCopyToReg, "
 386             "input_vals=[<ld.out0.copy.outputs[0]: <I64*32>>, "
 387             "<add.inp0.setvl.outputs[0]: <VL_MAXVL>>], "
 388             "input_uses=(<add.inp0.copy.input_uses[0]: <I64*32>>, "
 389             "<add.inp0.copy.input_uses[1]: <VL_MAXVL>>), "
 390             "immediates=[], "
 391             "outputs=(<add.inp0.copy.outputs[0]: <I64*32>>,), "
 392             "name='add.inp0.copy')",
 393             "Op(kind=OpKind.SetVLI, "
 394             "input_vals=[], "
 395             "input_uses=(), "
 396             "immediates=[32], "
 397             "outputs=(<add.inp1.setvl.outputs[0]: <VL_MAXVL>>,), "
 398             "name='add.inp1.setvl')",
 399             "Op(kind=OpKind.VecCopyToReg, "
 400             "input_vals=[<li.out0.copy.outputs[0]: <I64*32>>, "
 401             "<add.inp1.setvl.outputs[0]: <VL_MAXVL>>], "
 402             "input_uses=(<add.inp1.copy.input_uses[0]: <I64*32>>, "
 403             "<add.inp1.copy.input_uses[1]: <VL_MAXVL>>), "
 404             "immediates=[], "
 405             "outputs=(<add.inp1.copy.outputs[0]: <I64*32>>,), "
 406             "name='add.inp1.copy')",
 407             "Op(kind=OpKind.SvAddE, "
 408             "input_vals=[<add.inp0.copy.outputs[0]: <I64*32>>, "
 409             "<add.inp1.copy.outputs[0]: <I64*32>>, <ca.outputs[0]: <CA>>, "
 410             "<vl.outputs[0]: <VL_MAXVL>>], "
 411             "input_uses=(<add.input_uses[0]: <I64*32>>, "
 412             "<add.input_uses[1]: <I64*32>>, <add.input_uses[2]: <CA>>, "
 413             "<add.input_uses[3]: <VL_MAXVL>>), "
 414             "immediates=[], "
 415             "outputs=(<add.outputs[0]: <I64*32>>, <add.outputs[1]: <CA>>), "
 416             "name='add')",
 417             "Op(kind=OpKind.SetVLI, "
 418             "input_vals=[], "
 419             "input_uses=(), "
 420             "immediates=[32], "
 421             "outputs=(<add.out0.setvl.outputs[0]: <VL_MAXVL>>,), "
 422             "name='add.out0.setvl')",
 423             "Op(kind=OpKind.VecCopyFromReg, "
 424             "input_vals=[<add.outputs[0]: <I64*32>>, "
 425             "<add.out0.setvl.outputs[0]: <VL_MAXVL>>], "
 426             "input_uses=(<add.out0.copy.input_uses[0]: <I64*32>>, "
 427             "<add.out0.copy.input_uses[1]: <VL_MAXVL>>), "
 428             "immediates=[], "
 429             "outputs=(<add.out0.copy.outputs[0]: <I64*32>>,), "
 430             "name='add.out0.copy')",
 431             "Op(kind=OpKind.SetVLI, "
 432             "input_vals=[], "
 433             "input_uses=(), "
 434             "immediates=[32], "
 435             "outputs=(<st.inp0.setvl.outputs[0]: <VL_MAXVL>>,), "
 436             "name='st.inp0.setvl')",
 437             "Op(kind=OpKind.VecCopyToReg, "
 438             "input_vals=[<add.out0.copy.outputs[0]: <I64*32>>, "
 439             "<st.inp0.setvl.outputs[0]: <VL_MAXVL>>], "
 440             "input_uses=(<st.inp0.copy.input_uses[0]: <I64*32>>, "
 441             "<st.inp0.copy.input_uses[1]: <VL_MAXVL>>), "
 442             "immediates=[], "
 443             "outputs=(<st.inp0.copy.outputs[0]: <I64*32>>,), "
 444             "name='st.inp0.copy')",
 445             "Op(kind=OpKind.CopyToReg, "
 446             "input_vals=[<arg.out0.copy.outputs[0]: <I64>>], "
 447             "input_uses=(<st.inp1.copy.input_uses[0]: <I64>>,), "
 448             "immediates=[], "
 449             "outputs=(<st.inp1.copy.outputs[0]: <I64>>,), "
 450             "name='st.inp1.copy')",
 451             "Op(kind=OpKind.SvStd, "
 452             "input_vals=[<st.inp0.copy.outputs[0]: <I64*32>>, "
 453             "<st.inp1.copy.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>], "
 454             "input_uses=(<st.input_uses[0]: <I64*32>>, "
 455             "<st.input_uses[1]: <I64>>, <st.input_uses[2]: <VL_MAXVL>>), "
 456             "immediates=[0], "
 457             "outputs=(), name='st')",
 458         ])
 459         self.assertEqual([repr(op.properties) for op in fn.ops], [
 460             "OpProperties(kind=OpKind.FuncArgR3, "
 461             "inputs=(), "
 462             "outputs=("
 463             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 464             "LocKind.GPR: FBitSet([3])}), ty=<I64>), "
 465             "tied_input_index=None, spread_index=None, "
 466             "write_stage=OpStage.Early),), maxvl=1)",
 467             "OpProperties(kind=OpKind.CopyFromReg, "
 468             "inputs=("
 469             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 470             "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
 471             "ty=<I64>), "
 472             "tied_input_index=None, spread_index=None, "
 473             "write_stage=OpStage.Early),), "
 474             "outputs=("
 475             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 476             "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)]), "
 477             "LocKind.StackI64: FBitSet(range(0, 1024))}), ty=<I64>), "
 478             "tied_input_index=None, spread_index=None, "
 479             "write_stage=OpStage.Late),), maxvl=1)",
 480             "OpProperties(kind=OpKind.SetVLI, "
 481             "inputs=(), "
 482             "outputs=("
 483             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 484             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 485             "tied_input_index=None, spread_index=None, "
 486             "write_stage=OpStage.Late),), maxvl=1)",
 487             "OpProperties(kind=OpKind.CopyToReg, "
 488             "inputs=("
 489             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 490             "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)]), "
 491             "LocKind.StackI64: FBitSet(range(0, 1024))}), ty=<I64>), "
 492             "tied_input_index=None, spread_index=None, "
 493             "write_stage=OpStage.Early),), "
 494             "outputs=("
 495             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 496             "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
 497             "ty=<I64>), "
 498             "tied_input_index=None, spread_index=None, "
 499             "write_stage=OpStage.Late),), maxvl=1)",
 500             "OpProperties(kind=OpKind.SvLd, "
 501             "inputs=("
 502             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 503             "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
 504             "ty=<I64>), "
 505             "tied_input_index=None, spread_index=None, "
 506             "write_stage=OpStage.Early), "
 507             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 508             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 509             "tied_input_index=None, spread_index=None, "
 510             "write_stage=OpStage.Early)), "
 511             "outputs=("
 512             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 513             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 514             "tied_input_index=None, spread_index=None, "
 515             "write_stage=OpStage.Early),), maxvl=32)",
 516             "OpProperties(kind=OpKind.SetVLI, "
 517             "inputs=(), "
 518             "outputs=("
 519             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 520             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 521             "tied_input_index=None, spread_index=None, "
 522             "write_stage=OpStage.Late),), maxvl=1)",
 523             "OpProperties(kind=OpKind.VecCopyFromReg, "
 524             "inputs=("
 525             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 526             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 527             "tied_input_index=None, spread_index=None, "
 528             "write_stage=OpStage.Early), "
 529             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 530             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 531             "tied_input_index=None, spread_index=None, "
 532             "write_stage=OpStage.Early)), "
 533             "outputs=("
 534             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 535             "LocKind.GPR: FBitSet(range(14, 97)), "
 536             "LocKind.StackI64: FBitSet(range(0, 993))}), ty=<I64*32>), "
 537             "tied_input_index=None, spread_index=None, "
 538             "write_stage=OpStage.Late),), maxvl=32)",
 539             "OpProperties(kind=OpKind.SvLI, "
 540             "inputs=("
 541             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 542             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 543             "tied_input_index=None, spread_index=None, "
 544             "write_stage=OpStage.Early),), "
 545             "outputs=("
 546             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 547             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 548             "tied_input_index=None, spread_index=None, "
 549             "write_stage=OpStage.Early),), maxvl=32)",
 550             "OpProperties(kind=OpKind.SetVLI, "
 551             "inputs=(), "
 552             "outputs=("
 553             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 554             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 555             "tied_input_index=None, spread_index=None, "
 556             "write_stage=OpStage.Late),), maxvl=1)",
 557             "OpProperties(kind=OpKind.VecCopyFromReg, "
 558             "inputs=("
 559             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 560             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 561             "tied_input_index=None, spread_index=None, "
 562             "write_stage=OpStage.Early), "
 563             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 564             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 565             "tied_input_index=None, spread_index=None, "
 566             "write_stage=OpStage.Early)), "
 567             "outputs=("
 568             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 569             "LocKind.GPR: FBitSet(range(14, 97)), "
 570             "LocKind.StackI64: FBitSet(range(0, 993))}), ty=<I64*32>), "
 571             "tied_input_index=None, spread_index=None, "
 572             "write_stage=OpStage.Late),), maxvl=32)",
 573             "OpProperties(kind=OpKind.SetCA, "
 574             "inputs=(), "
 575             "outputs=("
 576             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 577             "LocKind.CA: FBitSet([0])}), ty=<CA>), "
 578             "tied_input_index=None, spread_index=None, "
 579             "write_stage=OpStage.Late),), maxvl=1)",
 580             "OpProperties(kind=OpKind.SetVLI, "
 581             "inputs=(), "
 582             "outputs=("
 583             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 584             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 585             "tied_input_index=None, spread_index=None, "
 586             "write_stage=OpStage.Late),), maxvl=1)",
 587             "OpProperties(kind=OpKind.VecCopyToReg, "
 588             "inputs=("
 589             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 590             "LocKind.GPR: FBitSet(range(14, 97)), "
 591             "LocKind.StackI64: FBitSet(range(0, 993))}), ty=<I64*32>), "
 592             "tied_input_index=None, spread_index=None, "
 593             "write_stage=OpStage.Early), "
 594             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 595             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 596             "tied_input_index=None, spread_index=None, "
 597             "write_stage=OpStage.Early)), "
 598             "outputs=("
 599             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 600             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 601             "tied_input_index=None, spread_index=None, "
 602             "write_stage=OpStage.Late),), maxvl=32)",
 603             "OpProperties(kind=OpKind.SetVLI, "
 604             "inputs=(), "
 605             "outputs=("
 606             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 607             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 608             "tied_input_index=None, spread_index=None, "
 609             "write_stage=OpStage.Late),), maxvl=1)",
 610             "OpProperties(kind=OpKind.VecCopyToReg, "
 611             "inputs=("
 612             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 613             "LocKind.GPR: FBitSet(range(14, 97)), "
 614             "LocKind.StackI64: FBitSet(range(0, 993))}), ty=<I64*32>), "
 615             "tied_input_index=None, spread_index=None, "
 616             "write_stage=OpStage.Early), "
 617             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 618             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 619             "tied_input_index=None, spread_index=None, "
 620             "write_stage=OpStage.Early)), "
 621             "outputs=("
 622             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 623             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 624             "tied_input_index=None, spread_index=None, "
 625             "write_stage=OpStage.Late),), maxvl=32)",
 626             "OpProperties(kind=OpKind.SvAddE, "
 627             "inputs=("
 628             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 629             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 630             "tied_input_index=None, spread_index=None, "
 631             "write_stage=OpStage.Early), "
 632             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 633             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 634             "tied_input_index=None, spread_index=None, "
 635             "write_stage=OpStage.Early), "
 636             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 637             "LocKind.CA: FBitSet([0])}), ty=<CA>), "
 638             "tied_input_index=None, spread_index=None, "
 639             "write_stage=OpStage.Early), "
 640             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 641             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 642             "tied_input_index=None, spread_index=None, "
 643             "write_stage=OpStage.Early)), "
 644             "outputs=("
 645             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 646             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 647             "tied_input_index=None, spread_index=None, "
 648             "write_stage=OpStage.Early), "
 649             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 650             "LocKind.CA: FBitSet([0])}), ty=<CA>), "
 651             "tied_input_index=None, spread_index=None, "
 652             "write_stage=OpStage.Early)), maxvl=32)",
 653             "OpProperties(kind=OpKind.SetVLI, "
 654             "inputs=(), "
 655             "outputs=("
 656             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 657             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 658             "tied_input_index=None, spread_index=None, "
 659             "write_stage=OpStage.Late),), maxvl=1)",
 660             "OpProperties(kind=OpKind.VecCopyFromReg, "
 661             "inputs=("
 662             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 663             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 664             "tied_input_index=None, spread_index=None, "
 665             "write_stage=OpStage.Early), "
 666             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 667             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 668             "tied_input_index=None, spread_index=None, "
 669             "write_stage=OpStage.Early)), "
 670             "outputs=("
 671             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 672             "LocKind.GPR: FBitSet(range(14, 97)), "
 673             "LocKind.StackI64: FBitSet(range(0, 993))}), ty=<I64*32>), "
 674             "tied_input_index=None, spread_index=None, "
 675             "write_stage=OpStage.Late),), maxvl=32)",
 676             "OpProperties(kind=OpKind.SetVLI, "
 677             "inputs=(), "
 678             "outputs=("
 679             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 680             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 681             "tied_input_index=None, spread_index=None, "
 682             "write_stage=OpStage.Late),), maxvl=1)",
 683             "OpProperties(kind=OpKind.VecCopyToReg, "
 684             "inputs=("
 685             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 686             "LocKind.GPR: FBitSet(range(14, 97)), "
 687             "LocKind.StackI64: FBitSet(range(0, 993))}), ty=<I64*32>), "
 688             "tied_input_index=None, spread_index=None, "
 689             "write_stage=OpStage.Early), "
 690             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 691             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 692             "tied_input_index=None, spread_index=None, "
 693             "write_stage=OpStage.Early)), "
 694             "outputs=("
 695             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 696             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 697             "tied_input_index=None, spread_index=None, "
 698             "write_stage=OpStage.Late),), maxvl=32)",
 699             "OpProperties(kind=OpKind.CopyToReg, "
 700             "inputs=("
 701             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 702             "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)]), "
 703             "LocKind.StackI64: FBitSet(range(0, 1024))}), ty=<I64>), "
 704             "tied_input_index=None, spread_index=None, "
 705             "write_stage=OpStage.Early),), "
 706             "outputs=("
 707             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 708             "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
 709             "ty=<I64>), "
 710             "tied_input_index=None, spread_index=None, "
 711             "write_stage=OpStage.Late),), maxvl=1)",
 712             "OpProperties(kind=OpKind.SvStd, "
 713             "inputs=("
 714             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 715             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 716             "tied_input_index=None, spread_index=None, "
 717             "write_stage=OpStage.Early), "
 718             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 719             "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
 720             "ty=<I64>), "
 721             "tied_input_index=None, spread_index=None, "
 722             "write_stage=OpStage.Early), "
 723             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 724             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 725             "tied_input_index=None, spread_index=None, "
 726             "write_stage=OpStage.Early)), "
 727             "outputs=(), maxvl=32)",
 728         ])
 729
 730     def test_sim(self):
 731         fn, arg = self.make_add_fn()
 732         addr = 0x100
 733         state = PreRASimState(ssa_vals={arg: (addr,)}, memory={})
 734         state.store(addr=addr, value=0xffffffff_ffffffff,
 735                     size_in_bytes=GPR_SIZE_IN_BYTES)
 736         state.store(addr=addr + GPR_SIZE_IN_BYTES, value=0xabcdef01_23456789,
 737                     size_in_bytes=GPR_SIZE_IN_BYTES)
 738         self.assertEqual(
 739             repr(state),
 740             "PreRASimState(ssa_vals={<arg.outputs[0]: <I64>>: (0x100,)}, "
 741             "memory={\n"
 742             "0x00100: <0xffffffffffffffff>,\n"
 743             "0x00108: <0xabcdef0123456789>})")
 744         fn.pre_ra_sim(state)
 745         self.assertEqual(
 746             repr(state),
 747             "PreRASimState(ssa_vals={\n"
 748             "<arg.outputs[0]: <I64>>: (0x100,),\n"
 749             "<vl.outputs[0]: <VL_MAXVL>>: (0x20,),\n"
 750             "<ld.outputs[0]: <I64*32>>: (\n"
 751             "    0xffffffffffffffff, 0xabcdef0123456789, 0x0, 0x0,\n"
 752             "    0x0, 0x0, 0x0, 0x0,\n"
 753             "    0x0, 0x0, 0x0, 0x0,\n"
 754             "    0x0, 0x0, 0x0, 0x0,\n"
 755             "    0x0, 0x0, 0x0, 0x0,\n"
 756             "    0x0, 0x0, 0x0, 0x0,\n"
 757             "    0x0, 0x0, 0x0, 0x0,\n"
 758             "    0x0, 0x0, 0x0, 0x0),\n"
 759             "<li.outputs[0]: <I64*32>>: (\n"
 760             "    0x0, 0x0, 0x0, 0x0,\n"
 761             "    0x0, 0x0, 0x0, 0x0,\n"
 762             "    0x0, 0x0, 0x0, 0x0,\n"
 763             "    0x0, 0x0, 0x0, 0x0,\n"
 764             "    0x0, 0x0, 0x0, 0x0,\n"
 765             "    0x0, 0x0, 0x0, 0x0,\n"
 766             "    0x0, 0x0, 0x0, 0x0,\n"
 767             "    0x0, 0x0, 0x0, 0x0),\n"
 768             "<ca.outputs[0]: <CA>>: (0x1,),\n"
 769             "<add.outputs[0]: <I64*32>>: (\n"
 770             "    0x0, 0xabcdef012345678a, 0x0, 0x0,\n"
 771             "    0x0, 0x0, 0x0, 0x0,\n"
 772             "    0x0, 0x0, 0x0, 0x0,\n"
 773             "    0x0, 0x0, 0x0, 0x0,\n"
 774             "    0x0, 0x0, 0x0, 0x0,\n"
 775             "    0x0, 0x0, 0x0, 0x0,\n"
 776             "    0x0, 0x0, 0x0, 0x0,\n"
 777             "    0x0, 0x0, 0x0, 0x0),\n"
 778             "<add.outputs[1]: <CA>>: (0x0,),\n"
 779             "}, memory={\n"
 780             "0x00100: <0x0000000000000000>,\n"
 781             "0x00108: <0xabcdef012345678a>,\n"
 782             "0x00110: <0x0000000000000000>,\n"
 783             "0x00118: <0x0000000000000000>,\n"
 784             "0x00120: <0x0000000000000000>,\n"
 785             "0x00128: <0x0000000000000000>,\n"
 786             "0x00130: <0x0000000000000000>,\n"
 787             "0x00138: <0x0000000000000000>,\n"
 788             "0x00140: <0x0000000000000000>,\n"
 789             "0x00148: <0x0000000000000000>,\n"
 790             "0x00150: <0x0000000000000000>,\n"
 791             "0x00158: <0x0000000000000000>,\n"
 792             "0x00160: <0x0000000000000000>,\n"
 793             "0x00168: <0x0000000000000000>,\n"
 794             "0x00170: <0x0000000000000000>,\n"
 795             "0x00178: <0x0000000000000000>,\n"
 796             "0x00180: <0x0000000000000000>,\n"
 797             "0x00188: <0x0000000000000000>,\n"
 798             "0x00190: <0x0000000000000000>,\n"
 799             "0x00198: <0x0000000000000000>,\n"
 800             "0x001a0: <0x0000000000000000>,\n"
 801             "0x001a8: <0x0000000000000000>,\n"
 802             "0x001b0: <0x0000000000000000>,\n"
 803             "0x001b8: <0x0000000000000000>,\n"
 804             "0x001c0: <0x0000000000000000>,\n"
 805             "0x001c8: <0x0000000000000000>,\n"
 806             "0x001d0: <0x0000000000000000>,\n"
 807             "0x001d8: <0x0000000000000000>,\n"
 808             "0x001e0: <0x0000000000000000>,\n"
 809             "0x001e8: <0x0000000000000000>,\n"
 810             "0x001f0: <0x0000000000000000>,\n"
 811             "0x001f8: <0x0000000000000000>})")
 812
 813
 814 if __name__ == "__main__":
 815     _ = unittest.main()