working on code
[bigint-presentation-code.git] / src / bigint_presentation_code / _tests / test_compiler_ir2.py
1 import unittest
2
3 from bigint_presentation_code.compiler_ir2 import (GPR_SIZE_IN_BYTES, Fn,
4 OpKind, PreRASimState,
5 SSAVal)
6
7
8 class TestCompilerIR(unittest.TestCase):
9 maxDiff = None
10
11 def make_add_fn(self):
12 # type: () -> tuple[Fn, SSAVal]
13 fn = Fn()
14 op0 = fn.append_new_op(OpKind.FuncArgR3, name="arg")
15 arg = op0.outputs[0]
16 MAXVL = 32
17 op1 = fn.append_new_op(OpKind.SetVLI, immediates=[MAXVL], name="vl")
18 vl = op1.outputs[0]
19 op2 = fn.append_new_op(
20 OpKind.SvLd, input_vals=[arg, vl], immediates=[0], maxvl=MAXVL,
21 name="ld")
22 a = op2.outputs[0]
23 op3 = fn.append_new_op(OpKind.SvLI, input_vals=[vl], immediates=[0],
24 maxvl=MAXVL, name="li")
25 b = op3.outputs[0]
26 op4 = fn.append_new_op(OpKind.SetCA, name="ca")
27 ca = op4.outputs[0]
28 op5 = fn.append_new_op(
29 OpKind.SvAddE, input_vals=[a, b, ca, vl], maxvl=MAXVL, name="add")
30 s = op5.outputs[0]
31 fn.append_new_op(OpKind.SvStd, input_vals=[s, arg, vl],
32 immediates=[0], maxvl=MAXVL, name="st")
33 return fn, arg
34
35 def test_repr(self):
36 fn, _arg = self.make_add_fn()
37 self.assertEqual([repr(i) for i in fn.ops], [
38 "Op(kind=OpKind.FuncArgR3, "
39 "input_vals=[], "
40 "input_uses=(), "
41 "immediates=[], "
42 "outputs=(<arg.outputs[0]: <I64>>,), name='arg')",
43 "Op(kind=OpKind.SetVLI, "
44 "input_vals=[], "
45 "input_uses=(), "
46 "immediates=[32], "
47 "outputs=(<vl.outputs[0]: <VL_MAXVL>>,), name='vl')",
48 "Op(kind=OpKind.SvLd, "
49 "input_vals=[<arg.outputs[0]: <I64>>, "
50 "<vl.outputs[0]: <VL_MAXVL>>], "
51 "input_uses=(<ld.input_uses[0]: <I64>>, "
52 "<ld.input_uses[1]: <VL_MAXVL>>), "
53 "immediates=[0], "
54 "outputs=(<ld.outputs[0]: <I64*32>>,), name='ld')",
55 "Op(kind=OpKind.SvLI, "
56 "input_vals=[<vl.outputs[0]: <VL_MAXVL>>], "
57 "input_uses=(<li.input_uses[0]: <VL_MAXVL>>,), "
58 "immediates=[0], "
59 "outputs=(<li.outputs[0]: <I64*32>>,), name='li')",
60 "Op(kind=OpKind.SetCA, "
61 "input_vals=[], "
62 "input_uses=(), "
63 "immediates=[], "
64 "outputs=(<ca.outputs[0]: <CA>>,), name='ca')",
65 "Op(kind=OpKind.SvAddE, "
66 "input_vals=[<ld.outputs[0]: <I64*32>>, "
67 "<li.outputs[0]: <I64*32>>, <ca.outputs[0]: <CA>>, "
68 "<vl.outputs[0]: <VL_MAXVL>>], "
69 "input_uses=(<add.input_uses[0]: <I64*32>>, "
70 "<add.input_uses[1]: <I64*32>>, <add.input_uses[2]: <CA>>, "
71 "<add.input_uses[3]: <VL_MAXVL>>), "
72 "immediates=[], "
73 "outputs=(<add.outputs[0]: <I64*32>>, <add.outputs[1]: <CA>>), "
74 "name='add')",
75 "Op(kind=OpKind.SvStd, "
76 "input_vals=[<add.outputs[0]: <I64*32>>, <arg.outputs[0]: <I64>>, "
77 "<vl.outputs[0]: <VL_MAXVL>>], "
78 "input_uses=(<st.input_uses[0]: <I64*32>>, "
79 "<st.input_uses[1]: <I64>>, <st.input_uses[2]: <VL_MAXVL>>), "
80 "immediates=[0], "
81 "outputs=(), name='st')",
82 ])
83 self.assertEqual([repr(op.properties) for op in fn.ops], [
84 "OpProperties(kind=OpKind.FuncArgR3, "
85 "inputs=(), "
86 "outputs=("
87 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
88 "LocKind.GPR: FBitSet([3])}), ty=<I64>), "
89 "tied_input_index=None, spread_index=None),), maxvl=1)",
90 "OpProperties(kind=OpKind.SetVLI, "
91 "inputs=(), "
92 "outputs=("
93 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
94 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
95 "tied_input_index=None, spread_index=None),), maxvl=1)",
96 "OpProperties(kind=OpKind.SvLd, "
97 "inputs=("
98 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
99 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
100 "ty=<I64>), "
101 "tied_input_index=None, spread_index=None), "
102 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
103 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
104 "tied_input_index=None, spread_index=None)), "
105 "outputs=("
106 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
107 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
108 "tied_input_index=None, spread_index=None),), maxvl=32)",
109 "OpProperties(kind=OpKind.SvLI, "
110 "inputs=("
111 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
112 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
113 "tied_input_index=None, spread_index=None),), "
114 "outputs=("
115 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
116 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
117 "tied_input_index=None, spread_index=None),), maxvl=32)",
118 "OpProperties(kind=OpKind.SetCA, "
119 "inputs=(), "
120 "outputs=("
121 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
122 "LocKind.CA: FBitSet([0])}), ty=<CA>), "
123 "tied_input_index=None, spread_index=None),), maxvl=1)",
124 "OpProperties(kind=OpKind.SvAddE, "
125 "inputs=("
126 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
127 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
128 "tied_input_index=None, spread_index=None), "
129 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
130 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
131 "tied_input_index=None, spread_index=None), "
132 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
133 "LocKind.CA: FBitSet([0])}), ty=<CA>), "
134 "tied_input_index=None, spread_index=None), "
135 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
136 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
137 "tied_input_index=None, spread_index=None)), "
138 "outputs=("
139 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
140 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
141 "tied_input_index=None, spread_index=None), "
142 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
143 "LocKind.CA: FBitSet([0])}), ty=<CA>), "
144 "tied_input_index=None, spread_index=None)), maxvl=32)",
145 "OpProperties(kind=OpKind.SvStd, "
146 "inputs=("
147 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
148 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
149 "tied_input_index=None, spread_index=None), "
150 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
151 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
152 "ty=<I64>), "
153 "tied_input_index=None, spread_index=None), "
154 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
155 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
156 "tied_input_index=None, spread_index=None)), "
157 "outputs=(), maxvl=32)",
158 ])
159
160 def test_pre_ra_insert_copies(self):
161 fn, _arg = self.make_add_fn()
162 fn.pre_ra_insert_copies()
163 self.assertEqual([repr(i) for i in fn.ops], [
164 "Op(kind=OpKind.FuncArgR3, "
165 "input_vals=[], "
166 "input_uses=(), "
167 "immediates=[], "
168 "outputs=(<arg.outputs[0]: <I64>>,), name='arg')",
169 "Op(kind=OpKind.CopyFromReg, "
170 "input_vals=[<arg.outputs[0]: <I64>>], "
171 "input_uses=(<arg.out0.copy.input_uses[0]: <I64>>,), "
172 "immediates=[], "
173 "outputs=(<arg.out0.copy.outputs[0]: <I64>>,), "
174 "name='arg.out0.copy')",
175 "Op(kind=OpKind.SetVLI, "
176 "input_vals=[], "
177 "input_uses=(), "
178 "immediates=[32], "
179 "outputs=(<vl.outputs[0]: <VL_MAXVL>>,), name='vl')",
180 "Op(kind=OpKind.CopyToReg, "
181 "input_vals=[<arg.out0.copy.outputs[0]: <I64>>], "
182 "input_uses=(<ld.inp0.copy.input_uses[0]: <I64>>,), "
183 "immediates=[], "
184 "outputs=(<ld.inp0.copy.outputs[0]: <I64>>,), name='ld.inp0.copy')",
185 "Op(kind=OpKind.SvLd, "
186 "input_vals=[<ld.inp0.copy.outputs[0]: <I64>>, "
187 "<vl.outputs[0]: <VL_MAXVL>>], "
188 "input_uses=(<ld.input_uses[0]: <I64>>, "
189 "<ld.input_uses[1]: <VL_MAXVL>>), "
190 "immediates=[0], "
191 "outputs=(<ld.outputs[0]: <I64*32>>,), name='ld')",
192 "Op(kind=OpKind.SetVLI, "
193 "input_vals=[], "
194 "input_uses=(), "
195 "immediates=[32], "
196 "outputs=(<ld.out0.setvl.outputs[0]: <VL_MAXVL>>,), "
197 "name='ld.out0.setvl')",
198 "Op(kind=OpKind.VecCopyFromReg, "
199 "input_vals=[<ld.outputs[0]: <I64*32>>, "
200 "<ld.out0.setvl.outputs[0]: <VL_MAXVL>>], "
201 "input_uses=(<ld.out0.copy.input_uses[0]: <I64*32>>, "
202 "<ld.out0.copy.input_uses[1]: <VL_MAXVL>>), "
203 "immediates=[], "
204 "outputs=(<ld.out0.copy.outputs[0]: <I64*32>>,), "
205 "name='ld.out0.copy')",
206 "Op(kind=OpKind.SvLI, "
207 "input_vals=[<vl.outputs[0]: <VL_MAXVL>>], "
208 "input_uses=(<li.input_uses[0]: <VL_MAXVL>>,), "
209 "immediates=[0], "
210 "outputs=(<li.outputs[0]: <I64*32>>,), name='li')",
211 "Op(kind=OpKind.SetVLI, "
212 "input_vals=[], "
213 "input_uses=(), "
214 "immediates=[32], "
215 "outputs=(<li.out0.setvl.outputs[0]: <VL_MAXVL>>,), "
216 "name='li.out0.setvl')",
217 "Op(kind=OpKind.VecCopyFromReg, "
218 "input_vals=[<li.outputs[0]: <I64*32>>, "
219 "<li.out0.setvl.outputs[0]: <VL_MAXVL>>], "
220 "input_uses=(<li.out0.copy.input_uses[0]: <I64*32>>, "
221 "<li.out0.copy.input_uses[1]: <VL_MAXVL>>), "
222 "immediates=[], "
223 "outputs=(<li.out0.copy.outputs[0]: <I64*32>>,), "
224 "name='li.out0.copy')",
225 "Op(kind=OpKind.SetCA, "
226 "input_vals=[], "
227 "input_uses=(), "
228 "immediates=[], "
229 "outputs=(<ca.outputs[0]: <CA>>,), name='ca')",
230 "Op(kind=OpKind.SetVLI, "
231 "input_vals=[], "
232 "input_uses=(), "
233 "immediates=[32], "
234 "outputs=(<add.inp0.setvl.outputs[0]: <VL_MAXVL>>,), "
235 "name='add.inp0.setvl')",
236 "Op(kind=OpKind.VecCopyToReg, "
237 "input_vals=[<ld.out0.copy.outputs[0]: <I64*32>>, "
238 "<add.inp0.setvl.outputs[0]: <VL_MAXVL>>], "
239 "input_uses=(<add.inp0.copy.input_uses[0]: <I64*32>>, "
240 "<add.inp0.copy.input_uses[1]: <VL_MAXVL>>), "
241 "immediates=[], "
242 "outputs=(<add.inp0.copy.outputs[0]: <I64*32>>,), "
243 "name='add.inp0.copy')",
244 "Op(kind=OpKind.SetVLI, "
245 "input_vals=[], "
246 "input_uses=(), "
247 "immediates=[32], "
248 "outputs=(<add.inp1.setvl.outputs[0]: <VL_MAXVL>>,), "
249 "name='add.inp1.setvl')",
250 "Op(kind=OpKind.VecCopyToReg, "
251 "input_vals=[<li.out0.copy.outputs[0]: <I64*32>>, "
252 "<add.inp1.setvl.outputs[0]: <VL_MAXVL>>], "
253 "input_uses=(<add.inp1.copy.input_uses[0]: <I64*32>>, "
254 "<add.inp1.copy.input_uses[1]: <VL_MAXVL>>), "
255 "immediates=[], "
256 "outputs=(<add.inp1.copy.outputs[0]: <I64*32>>,), "
257 "name='add.inp1.copy')",
258 "Op(kind=OpKind.SvAddE, "
259 "input_vals=[<add.inp0.copy.outputs[0]: <I64*32>>, "
260 "<add.inp1.copy.outputs[0]: <I64*32>>, <ca.outputs[0]: <CA>>, "
261 "<vl.outputs[0]: <VL_MAXVL>>], "
262 "input_uses=(<add.input_uses[0]: <I64*32>>, "
263 "<add.input_uses[1]: <I64*32>>, <add.input_uses[2]: <CA>>, "
264 "<add.input_uses[3]: <VL_MAXVL>>), "
265 "immediates=[], "
266 "outputs=(<add.outputs[0]: <I64*32>>, <add.outputs[1]: <CA>>), "
267 "name='add')",
268 "Op(kind=OpKind.SetVLI, "
269 "input_vals=[], "
270 "input_uses=(), "
271 "immediates=[32], "
272 "outputs=(<add.out0.setvl.outputs[0]: <VL_MAXVL>>,), "
273 "name='add.out0.setvl')",
274 "Op(kind=OpKind.VecCopyFromReg, "
275 "input_vals=[<add.outputs[0]: <I64*32>>, "
276 "<add.out0.setvl.outputs[0]: <VL_MAXVL>>], "
277 "input_uses=(<add.out0.copy.input_uses[0]: <I64*32>>, "
278 "<add.out0.copy.input_uses[1]: <VL_MAXVL>>), "
279 "immediates=[], "
280 "outputs=(<add.out0.copy.outputs[0]: <I64*32>>,), "
281 "name='add.out0.copy')",
282 "Op(kind=OpKind.SetVLI, "
283 "input_vals=[], "
284 "input_uses=(), "
285 "immediates=[32], "
286 "outputs=(<st.inp0.setvl.outputs[0]: <VL_MAXVL>>,), "
287 "name='st.inp0.setvl')",
288 "Op(kind=OpKind.VecCopyToReg, "
289 "input_vals=[<add.out0.copy.outputs[0]: <I64*32>>, "
290 "<st.inp0.setvl.outputs[0]: <VL_MAXVL>>], "
291 "input_uses=(<st.inp0.copy.input_uses[0]: <I64*32>>, "
292 "<st.inp0.copy.input_uses[1]: <VL_MAXVL>>), "
293 "immediates=[], "
294 "outputs=(<st.inp0.copy.outputs[0]: <I64*32>>,), "
295 "name='st.inp0.copy')",
296 "Op(kind=OpKind.CopyToReg, "
297 "input_vals=[<arg.out0.copy.outputs[0]: <I64>>], "
298 "input_uses=(<st.inp1.copy.input_uses[0]: <I64>>,), "
299 "immediates=[], "
300 "outputs=(<st.inp1.copy.outputs[0]: <I64>>,), "
301 "name='st.inp1.copy')",
302 "Op(kind=OpKind.SvStd, "
303 "input_vals=[<st.inp0.copy.outputs[0]: <I64*32>>, "
304 "<st.inp1.copy.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>], "
305 "input_uses=(<st.input_uses[0]: <I64*32>>, "
306 "<st.input_uses[1]: <I64>>, <st.input_uses[2]: <VL_MAXVL>>), "
307 "immediates=[0], "
308 "outputs=(), name='st')",
309 ])
310 self.assertEqual([repr(op.properties) for op in fn.ops], [
311 "OpProperties(kind=OpKind.FuncArgR3, "
312 "inputs=(), "
313 "outputs=("
314 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
315 "LocKind.GPR: FBitSet([3])}), ty=<I64>), "
316 "tied_input_index=None, spread_index=None),), maxvl=1)",
317 "OpProperties(kind=OpKind.CopyFromReg, "
318 "inputs=("
319 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
320 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
321 "ty=<I64>), "
322 "tied_input_index=None, spread_index=None),), "
323 "outputs=("
324 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
325 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)]), "
326 "LocKind.StackI64: FBitSet(range(0, 1024))}), ty=<I64>), "
327 "tied_input_index=None, spread_index=None),), maxvl=1)",
328 "OpProperties(kind=OpKind.SetVLI, "
329 "inputs=(), "
330 "outputs=("
331 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
332 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
333 "tied_input_index=None, spread_index=None),), maxvl=1)",
334 "OpProperties(kind=OpKind.CopyToReg, "
335 "inputs=("
336 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
337 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)]), "
338 "LocKind.StackI64: FBitSet(range(0, 1024))}), ty=<I64>), "
339 "tied_input_index=None, spread_index=None),), "
340 "outputs=("
341 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
342 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
343 "ty=<I64>), "
344 "tied_input_index=None, spread_index=None),), maxvl=1)",
345 "OpProperties(kind=OpKind.SvLd, "
346 "inputs=("
347 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
348 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
349 "ty=<I64>), "
350 "tied_input_index=None, spread_index=None), "
351 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
352 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
353 "tied_input_index=None, spread_index=None)), "
354 "outputs=("
355 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
356 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
357 "tied_input_index=None, spread_index=None),), maxvl=32)",
358 "OpProperties(kind=OpKind.SetVLI, "
359 "inputs=(), "
360 "outputs=("
361 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
362 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
363 "tied_input_index=None, spread_index=None),), maxvl=1)",
364 "OpProperties(kind=OpKind.VecCopyFromReg, "
365 "inputs=("
366 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
367 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
368 "tied_input_index=None, spread_index=None), "
369 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
370 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
371 "tied_input_index=None, spread_index=None)), "
372 "outputs=("
373 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
374 "LocKind.GPR: FBitSet(range(14, 97)), "
375 "LocKind.StackI64: FBitSet(range(0, 993))}), ty=<I64*32>), "
376 "tied_input_index=None, spread_index=None),), maxvl=32)",
377 "OpProperties(kind=OpKind.SvLI, "
378 "inputs=("
379 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
380 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
381 "tied_input_index=None, spread_index=None),), "
382 "outputs=("
383 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
384 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
385 "tied_input_index=None, spread_index=None),), maxvl=32)",
386 "OpProperties(kind=OpKind.SetVLI, "
387 "inputs=(), "
388 "outputs=("
389 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
390 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
391 "tied_input_index=None, spread_index=None),), maxvl=1)",
392 "OpProperties(kind=OpKind.VecCopyFromReg, "
393 "inputs=("
394 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
395 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
396 "tied_input_index=None, spread_index=None), "
397 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
398 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
399 "tied_input_index=None, spread_index=None)), "
400 "outputs=("
401 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
402 "LocKind.GPR: FBitSet(range(14, 97)), "
403 "LocKind.StackI64: FBitSet(range(0, 993))}), ty=<I64*32>), "
404 "tied_input_index=None, spread_index=None),), maxvl=32)",
405 "OpProperties(kind=OpKind.SetCA, "
406 "inputs=(), "
407 "outputs=("
408 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
409 "LocKind.CA: FBitSet([0])}), ty=<CA>), "
410 "tied_input_index=None, spread_index=None),), maxvl=1)",
411 "OpProperties(kind=OpKind.SetVLI, "
412 "inputs=(), "
413 "outputs=("
414 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
415 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
416 "tied_input_index=None, spread_index=None),), maxvl=1)",
417 "OpProperties(kind=OpKind.VecCopyToReg, "
418 "inputs=("
419 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
420 "LocKind.GPR: FBitSet(range(14, 97)), "
421 "LocKind.StackI64: FBitSet(range(0, 993))}), ty=<I64*32>), "
422 "tied_input_index=None, spread_index=None), "
423 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
424 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
425 "tied_input_index=None, spread_index=None)), "
426 "outputs=("
427 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
428 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
429 "tied_input_index=None, spread_index=None),), maxvl=32)",
430 "OpProperties(kind=OpKind.SetVLI, "
431 "inputs=(), "
432 "outputs=("
433 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
434 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
435 "tied_input_index=None, spread_index=None),), maxvl=1)",
436 "OpProperties(kind=OpKind.VecCopyToReg, "
437 "inputs=("
438 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
439 "LocKind.GPR: FBitSet(range(14, 97)), "
440 "LocKind.StackI64: FBitSet(range(0, 993))}), ty=<I64*32>), "
441 "tied_input_index=None, spread_index=None), "
442 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
443 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
444 "tied_input_index=None, spread_index=None)), "
445 "outputs=("
446 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
447 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
448 "tied_input_index=None, spread_index=None),), maxvl=32)",
449 "OpProperties(kind=OpKind.SvAddE, "
450 "inputs=("
451 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
452 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
453 "tied_input_index=None, spread_index=None), "
454 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
455 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
456 "tied_input_index=None, spread_index=None), "
457 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
458 "LocKind.CA: FBitSet([0])}), ty=<CA>), "
459 "tied_input_index=None, spread_index=None), "
460 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
461 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
462 "tied_input_index=None, spread_index=None)), "
463 "outputs=("
464 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
465 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
466 "tied_input_index=None, spread_index=None), "
467 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
468 "LocKind.CA: FBitSet([0])}), ty=<CA>), "
469 "tied_input_index=None, spread_index=None)), maxvl=32)",
470 "OpProperties(kind=OpKind.SetVLI, "
471 "inputs=(), "
472 "outputs=("
473 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
474 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
475 "tied_input_index=None, spread_index=None),), maxvl=1)",
476 "OpProperties(kind=OpKind.VecCopyFromReg, "
477 "inputs=("
478 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
479 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
480 "tied_input_index=None, spread_index=None), "
481 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
482 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
483 "tied_input_index=None, spread_index=None)), "
484 "outputs=("
485 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
486 "LocKind.GPR: FBitSet(range(14, 97)), "
487 "LocKind.StackI64: FBitSet(range(0, 993))}), ty=<I64*32>), "
488 "tied_input_index=None, spread_index=None),), maxvl=32)",
489 "OpProperties(kind=OpKind.SetVLI, "
490 "inputs=(), "
491 "outputs=("
492 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
493 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
494 "tied_input_index=None, spread_index=None),), maxvl=1)",
495 "OpProperties(kind=OpKind.VecCopyToReg, "
496 "inputs=("
497 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
498 "LocKind.GPR: FBitSet(range(14, 97)), "
499 "LocKind.StackI64: FBitSet(range(0, 993))}), ty=<I64*32>), "
500 "tied_input_index=None, spread_index=None), "
501 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
502 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
503 "tied_input_index=None, spread_index=None)), "
504 "outputs=("
505 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
506 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
507 "tied_input_index=None, spread_index=None),), maxvl=32)",
508 "OpProperties(kind=OpKind.CopyToReg, "
509 "inputs=("
510 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
511 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)]), "
512 "LocKind.StackI64: FBitSet(range(0, 1024))}), ty=<I64>), "
513 "tied_input_index=None, spread_index=None),), "
514 "outputs=("
515 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
516 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
517 "ty=<I64>), "
518 "tied_input_index=None, spread_index=None),), maxvl=1)",
519 "OpProperties(kind=OpKind.SvStd, "
520 "inputs=("
521 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
522 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
523 "tied_input_index=None, spread_index=None), "
524 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
525 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
526 "ty=<I64>), "
527 "tied_input_index=None, spread_index=None), "
528 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
529 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
530 "tied_input_index=None, spread_index=None)), "
531 "outputs=(), maxvl=32)",
532 ])
533
534 def test_sim(self):
535 fn, arg = self.make_add_fn()
536 addr = 0x100
537 state = PreRASimState(ssa_vals={arg: (addr,)}, memory={})
538 state.store(addr=addr, value=0xffffffff_ffffffff,
539 size_in_bytes=GPR_SIZE_IN_BYTES)
540 state.store(addr=addr + GPR_SIZE_IN_BYTES, value=0xabcdef01_23456789,
541 size_in_bytes=GPR_SIZE_IN_BYTES)
542 self.assertEqual(
543 repr(state),
544 "PreRASimState(ssa_vals={<arg.outputs[0]: <I64>>: (0x100,)}, "
545 "memory={\n"
546 "0x00100: <0xffffffffffffffff>,\n"
547 "0x00108: <0xabcdef0123456789>})")
548 fn.pre_ra_sim(state)
549 self.assertEqual(
550 repr(state),
551 "PreRASimState(ssa_vals={\n"
552 "<arg.outputs[0]: <I64>>: (0x100,),\n"
553 "<vl.outputs[0]: <VL_MAXVL>>: (0x20,),\n"
554 "<ld.outputs[0]: <I64*32>>: (\n"
555 " 0xffffffffffffffff, 0xabcdef0123456789, 0x0, 0x0,\n"
556 " 0x0, 0x0, 0x0, 0x0,\n"
557 " 0x0, 0x0, 0x0, 0x0,\n"
558 " 0x0, 0x0, 0x0, 0x0,\n"
559 " 0x0, 0x0, 0x0, 0x0,\n"
560 " 0x0, 0x0, 0x0, 0x0,\n"
561 " 0x0, 0x0, 0x0, 0x0,\n"
562 " 0x0, 0x0, 0x0, 0x0),\n"
563 "<li.outputs[0]: <I64*32>>: (\n"
564 " 0x0, 0x0, 0x0, 0x0,\n"
565 " 0x0, 0x0, 0x0, 0x0,\n"
566 " 0x0, 0x0, 0x0, 0x0,\n"
567 " 0x0, 0x0, 0x0, 0x0,\n"
568 " 0x0, 0x0, 0x0, 0x0,\n"
569 " 0x0, 0x0, 0x0, 0x0,\n"
570 " 0x0, 0x0, 0x0, 0x0,\n"
571 " 0x0, 0x0, 0x0, 0x0),\n"
572 "<ca.outputs[0]: <CA>>: (0x1,),\n"
573 "<add.outputs[0]: <I64*32>>: (\n"
574 " 0x0, 0xabcdef012345678a, 0x0, 0x0,\n"
575 " 0x0, 0x0, 0x0, 0x0,\n"
576 " 0x0, 0x0, 0x0, 0x0,\n"
577 " 0x0, 0x0, 0x0, 0x0,\n"
578 " 0x0, 0x0, 0x0, 0x0,\n"
579 " 0x0, 0x0, 0x0, 0x0,\n"
580 " 0x0, 0x0, 0x0, 0x0,\n"
581 " 0x0, 0x0, 0x0, 0x0),\n"
582 "<add.outputs[1]: <CA>>: (0x0,),\n"
583 "}, memory={\n"
584 "0x00100: <0x0000000000000000>,\n"
585 "0x00108: <0xabcdef012345678a>,\n"
586 "0x00110: <0x0000000000000000>,\n"
587 "0x00118: <0x0000000000000000>,\n"
588 "0x00120: <0x0000000000000000>,\n"
589 "0x00128: <0x0000000000000000>,\n"
590 "0x00130: <0x0000000000000000>,\n"
591 "0x00138: <0x0000000000000000>,\n"
592 "0x00140: <0x0000000000000000>,\n"
593 "0x00148: <0x0000000000000000>,\n"
594 "0x00150: <0x0000000000000000>,\n"
595 "0x00158: <0x0000000000000000>,\n"
596 "0x00160: <0x0000000000000000>,\n"
597 "0x00168: <0x0000000000000000>,\n"
598 "0x00170: <0x0000000000000000>,\n"
599 "0x00178: <0x0000000000000000>,\n"
600 "0x00180: <0x0000000000000000>,\n"
601 "0x00188: <0x0000000000000000>,\n"
602 "0x00190: <0x0000000000000000>,\n"
603 "0x00198: <0x0000000000000000>,\n"
604 "0x001a0: <0x0000000000000000>,\n"
605 "0x001a8: <0x0000000000000000>,\n"
606 "0x001b0: <0x0000000000000000>,\n"
607 "0x001b8: <0x0000000000000000>,\n"
608 "0x001c0: <0x0000000000000000>,\n"
609 "0x001c8: <0x0000000000000000>,\n"
610 "0x001d0: <0x0000000000000000>,\n"
611 "0x001d8: <0x0000000000000000>,\n"
612 "0x001e0: <0x0000000000000000>,\n"
613 "0x001e8: <0x0000000000000000>,\n"
614 "0x001f0: <0x0000000000000000>,\n"
615 "0x001f8: <0x0000000000000000>})")
616
617
618 if __name__ == "__main__":
619 unittest.main()