src/bigint_presentation_code/_tests/test_compiler_ir2.py

   1 import unittest
   2
   3 from bigint_presentation_code.compiler_ir2 import (GPR_SIZE_IN_BYTES, Fn,
   4                                                    OpKind, PreRASimState,
   5                                                    SSAVal)
   6
   7
   8 class TestCompilerIR(unittest.TestCase):
   9     maxDiff = None
  10
  11     def make_add_fn(self):
  12         # type: () -> tuple[Fn, SSAVal]
  13         fn = Fn()
  14         op0 = fn.append_new_op(OpKind.FuncArgR3, name="arg")
  15         arg = op0.outputs[0]
  16         MAXVL = 32
  17         op1 = fn.append_new_op(OpKind.SetVLI, immediates=[MAXVL], name="vl")
  18         vl = op1.outputs[0]
  19         op2 = fn.append_new_op(
  20             OpKind.SvLd, inputs=[arg, vl], immediates=[0], maxvl=MAXVL,
  21             name="ld")
  22         a = op2.outputs[0]
  23         op3 = fn.append_new_op(
  24             OpKind.SvLI, inputs=[vl], immediates=[0], maxvl=MAXVL, name="li")
  25         b = op3.outputs[0]
  26         op4 = fn.append_new_op(OpKind.SetCA, name="ca")
  27         ca = op4.outputs[0]
  28         op5 = fn.append_new_op(
  29             OpKind.SvAddE, inputs=[a, b, ca, vl], maxvl=MAXVL, name="add")
  30         s = op5.outputs[0]
  31         fn.append_new_op(
  32             OpKind.SvStd, inputs=[s, arg, vl], immediates=[0], maxvl=MAXVL,
  33             name="st")
  34         return fn, arg
  35
  36     def test_repr(self):
  37         fn, _arg = self.make_add_fn()
  38         self.assertEqual([repr(i) for i in fn.ops], [
  39             "Op(kind=OpKind.FuncArgR3, "
  40             "inputs=[], "
  41             "immediates=[], "
  42             "outputs=(<arg.outputs[0]: <I64>>,), name='arg')",
  43             "Op(kind=OpKind.SetVLI, "
  44             "inputs=[], "
  45             "immediates=[32], "
  46             "outputs=(<vl.outputs[0]: <VL_MAXVL>>,), name='vl')",
  47             "Op(kind=OpKind.SvLd, "
  48             "inputs=[<arg.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>], "
  49             "immediates=[0], "
  50             "outputs=(<ld.outputs[0]: <I64*32>>,), name='ld')",
  51             "Op(kind=OpKind.SvLI, "
  52             "inputs=[<vl.outputs[0]: <VL_MAXVL>>], "
  53             "immediates=[0], "
  54             "outputs=(<li.outputs[0]: <I64*32>>,), name='li')",
  55             "Op(kind=OpKind.SetCA, "
  56             "inputs=[], "
  57             "immediates=[], "
  58             "outputs=(<ca.outputs[0]: <CA>>,), name='ca')",
  59             "Op(kind=OpKind.SvAddE, "
  60             "inputs=[<ld.outputs[0]: <I64*32>>, <li.outputs[0]: <I64*32>>, "
  61             "<ca.outputs[0]: <CA>>, <vl.outputs[0]: <VL_MAXVL>>], "
  62             "immediates=[], "
  63             "outputs=(<add.outputs[0]: <I64*32>>, <add.outputs[1]: <CA>>), "
  64             "name='add')",
  65             "Op(kind=OpKind.SvStd, "
  66             "inputs=[<add.outputs[0]: <I64*32>>, <arg.outputs[0]: <I64>>, "
  67             "<vl.outputs[0]: <VL_MAXVL>>], "
  68             "immediates=[0], "
  69             "outputs=(), name='st')",
  70         ])
  71         self.assertEqual([repr(op.properties) for op in fn.ops], [
  72             "OpProperties(kind=OpKind.FuncArgR3, "
  73             "inputs=(), "
  74             "outputs=("
  75             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
  76             "LocKind.GPR: FBitSet([3])}), ty=<I64>), "
  77             "tied_input_index=None, spread_index=None),), maxvl=1)",
  78             "OpProperties(kind=OpKind.SetVLI, "
  79             "inputs=(), "
  80             "outputs=("
  81             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
  82             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
  83             "tied_input_index=None, spread_index=None),), maxvl=1)",
  84             "OpProperties(kind=OpKind.SvLd, "
  85             "inputs=("
  86             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
  87             "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
  88             "ty=<I64>), "
  89             "tied_input_index=None, spread_index=None), "
  90             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
  91             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
  92             "tied_input_index=None, spread_index=None)), "
  93             "outputs=("
  94             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
  95             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
  96             "tied_input_index=None, spread_index=None),), maxvl=32)",
  97             "OpProperties(kind=OpKind.SvLI, "
  98             "inputs=("
  99             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 100             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 101             "tied_input_index=None, spread_index=None),), "
 102             "outputs=("
 103             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 104             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 105             "tied_input_index=None, spread_index=None),), maxvl=32)",
 106             "OpProperties(kind=OpKind.SetCA, "
 107             "inputs=(), "
 108             "outputs=("
 109             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 110             "LocKind.CA: FBitSet([0])}), ty=<CA>), "
 111             "tied_input_index=None, spread_index=None),), maxvl=1)",
 112             "OpProperties(kind=OpKind.SvAddE, "
 113             "inputs=("
 114             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 115             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 116             "tied_input_index=None, spread_index=None), "
 117             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 118             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 119             "tied_input_index=None, spread_index=None), "
 120             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 121             "LocKind.CA: FBitSet([0])}), ty=<CA>), "
 122             "tied_input_index=None, spread_index=None), "
 123             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 124             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 125             "tied_input_index=None, spread_index=None)), "
 126             "outputs=("
 127             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 128             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 129             "tied_input_index=None, spread_index=None), "
 130             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 131             "LocKind.CA: FBitSet([0])}), ty=<CA>), "
 132             "tied_input_index=None, spread_index=None)), maxvl=32)",
 133             "OpProperties(kind=OpKind.SvStd, "
 134             "inputs=("
 135             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 136             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 137             "tied_input_index=None, spread_index=None), "
 138             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 139             "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
 140             "ty=<I64>), "
 141             "tied_input_index=None, spread_index=None), "
 142             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 143             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 144             "tied_input_index=None, spread_index=None)), "
 145             "outputs=(), maxvl=32)",
 146         ])
 147
 148     def test_pre_ra_insert_copies(self):
 149         fn, _arg = self.make_add_fn()
 150         fn.pre_ra_insert_copies()
 151         self.assertEqual([repr(i) for i in fn.ops], [
 152             "Op(kind=OpKind.FuncArgR3, "
 153             "inputs=[], "
 154             "immediates=[], "
 155             "outputs=(<arg.outputs[0]: <I64>>,), name='arg')",
 156             "Op(kind=OpKind.CopyFromReg, "
 157             "inputs=[<arg.outputs[0]: <I64>>], "
 158             "immediates=[], "
 159             "outputs=(<2.outputs[0]: <I64>>,), name='2')",
 160             "Op(kind=OpKind.SetVLI, "
 161             "inputs=[], "
 162             "immediates=[32], "
 163             "outputs=(<vl.outputs[0]: <VL_MAXVL>>,), name='vl')",
 164             "Op(kind=OpKind.CopyToReg, "
 165             "inputs=[<2.outputs[0]: <I64>>], "
 166             "immediates=[], "
 167             "outputs=(<3.outputs[0]: <I64>>,), name='3')",
 168             "Op(kind=OpKind.SvLd, "
 169             "inputs=[<3.outputs[0]: <I64>>, <vl.outputs[0]: <VL_MAXVL>>], "
 170             "immediates=[0], "
 171             "outputs=(<ld.outputs[0]: <I64*32>>,), name='ld')",
 172             "Op(kind=OpKind.SetVLI, "
 173             "inputs=[], "
 174             "immediates=[32], "
 175             "outputs=(<4.outputs[0]: <VL_MAXVL>>,), name='4')",
 176             "Op(kind=OpKind.VecCopyFromReg, "
 177             "inputs=[<ld.outputs[0]: <I64*32>>, <4.outputs[0]: <VL_MAXVL>>], "
 178             "immediates=[], "
 179             "outputs=(<5.outputs[0]: <I64*32>>,), name='5')",
 180             "Op(kind=OpKind.SvLI, "
 181             "inputs=[<vl.outputs[0]: <VL_MAXVL>>], "
 182             "immediates=[0], "
 183             "outputs=(<li.outputs[0]: <I64*32>>,), name='li')",
 184             "Op(kind=OpKind.SetVLI, "
 185             "inputs=[], "
 186             "immediates=[32], "
 187             "outputs=(<6.outputs[0]: <VL_MAXVL>>,), name='6')",
 188             "Op(kind=OpKind.VecCopyFromReg, "
 189             "inputs=[<li.outputs[0]: <I64*32>>, <6.outputs[0]: <VL_MAXVL>>], "
 190             "immediates=[], "
 191             "outputs=(<7.outputs[0]: <I64*32>>,), name='7')",
 192             "Op(kind=OpKind.SetCA, "
 193             "inputs=[], "
 194             "immediates=[], "
 195             "outputs=(<ca.outputs[0]: <CA>>,), name='ca')",
 196             "Op(kind=OpKind.SetVLI, "
 197             "inputs=[], "
 198             "immediates=[32], "
 199             "outputs=(<8.outputs[0]: <VL_MAXVL>>,), name='8')",
 200             "Op(kind=OpKind.VecCopyToReg, "
 201             "inputs=[<5.outputs[0]: <I64*32>>, <8.outputs[0]: <VL_MAXVL>>], "
 202             "immediates=[], "
 203             "outputs=(<9.outputs[0]: <I64*32>>,), name='9')",
 204             "Op(kind=OpKind.SetVLI, "
 205             "inputs=[], "
 206             "immediates=[32], "
 207             "outputs=(<10.outputs[0]: <VL_MAXVL>>,), name='10')",
 208             "Op(kind=OpKind.VecCopyToReg, "
 209             "inputs=[<7.outputs[0]: <I64*32>>, <10.outputs[0]: <VL_MAXVL>>], "
 210             "immediates=[], "
 211             "outputs=(<11.outputs[0]: <I64*32>>,), name='11')",
 212             "Op(kind=OpKind.SvAddE, "
 213             "inputs=[<9.outputs[0]: <I64*32>>, <11.outputs[0]: <I64*32>>, "
 214             "<ca.outputs[0]: <CA>>, <vl.outputs[0]: <VL_MAXVL>>], "
 215             "immediates=[], "
 216             "outputs=(<add.outputs[0]: <I64*32>>, <add.outputs[1]: <CA>>), "
 217             "name='add')",
 218             "Op(kind=OpKind.SetVLI, "
 219             "inputs=[], "
 220             "immediates=[32], "
 221             "outputs=(<12.outputs[0]: <VL_MAXVL>>,), name='12')",
 222             "Op(kind=OpKind.VecCopyFromReg, "
 223             "inputs=[<add.outputs[0]: <I64*32>>, "
 224             "<12.outputs[0]: <VL_MAXVL>>], "
 225             "immediates=[], "
 226             "outputs=(<13.outputs[0]: <I64*32>>,), name='13')",
 227             "Op(kind=OpKind.SetVLI, "
 228             "inputs=[], "
 229             "immediates=[32], "
 230             "outputs=(<14.outputs[0]: <VL_MAXVL>>,), name='14')",
 231             "Op(kind=OpKind.VecCopyToReg, "
 232             "inputs=[<13.outputs[0]: <I64*32>>, <14.outputs[0]: <VL_MAXVL>>], "
 233             "immediates=[], "
 234             "outputs=(<15.outputs[0]: <I64*32>>,), name='15')",
 235             "Op(kind=OpKind.CopyToReg, "
 236             "inputs=[<2.outputs[0]: <I64>>], "
 237             "immediates=[], "
 238             "outputs=(<16.outputs[0]: <I64>>,), name='16')",
 239             "Op(kind=OpKind.SvStd, "
 240             "inputs=[<15.outputs[0]: <I64*32>>, <16.outputs[0]: <I64>>, "
 241             "<vl.outputs[0]: <VL_MAXVL>>], "
 242             "immediates=[0], "
 243             "outputs=(), name='st')",
 244         ])
 245         self.assertEqual([repr(op.properties) for op in fn.ops], [
 246             "OpProperties(kind=OpKind.FuncArgR3, "
 247             "inputs=(), "
 248             "outputs=("
 249             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 250             "LocKind.GPR: FBitSet([3])}), ty=<I64>), "
 251             "tied_input_index=None, spread_index=None),), maxvl=1)",
 252             "OpProperties(kind=OpKind.CopyFromReg, "
 253             "inputs=("
 254             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 255             "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
 256             "ty=<I64>), "
 257             "tied_input_index=None, spread_index=None),), "
 258             "outputs=("
 259             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 260             "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)]), "
 261             "LocKind.StackI64: FBitSet(range(0, 1024))}), ty=<I64>), "
 262             "tied_input_index=None, spread_index=None),), maxvl=1)",
 263             "OpProperties(kind=OpKind.SetVLI, "
 264             "inputs=(), "
 265             "outputs=("
 266             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 267             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 268             "tied_input_index=None, spread_index=None),), maxvl=1)",
 269             "OpProperties(kind=OpKind.CopyToReg, "
 270             "inputs=("
 271             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 272             "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)]), "
 273             "LocKind.StackI64: FBitSet(range(0, 1024))}), ty=<I64>), "
 274             "tied_input_index=None, spread_index=None),), "
 275             "outputs=("
 276             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 277             "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
 278             "ty=<I64>), "
 279             "tied_input_index=None, spread_index=None),), maxvl=1)",
 280             "OpProperties(kind=OpKind.SvLd, "
 281             "inputs=("
 282             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 283             "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
 284             "ty=<I64>), "
 285             "tied_input_index=None, spread_index=None), "
 286             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 287             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 288             "tied_input_index=None, spread_index=None)), "
 289             "outputs=("
 290             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 291             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 292             "tied_input_index=None, spread_index=None),), maxvl=32)",
 293             "OpProperties(kind=OpKind.SetVLI, "
 294             "inputs=(), "
 295             "outputs=("
 296             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 297             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 298             "tied_input_index=None, spread_index=None),), maxvl=1)",
 299             "OpProperties(kind=OpKind.VecCopyFromReg, "
 300             "inputs=("
 301             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 302             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 303             "tied_input_index=None, spread_index=None), "
 304             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 305             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 306             "tied_input_index=None, spread_index=None)), "
 307             "outputs=("
 308             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 309             "LocKind.GPR: FBitSet(range(14, 97)), "
 310             "LocKind.StackI64: FBitSet(range(0, 993))}), ty=<I64*32>), "
 311             "tied_input_index=None, spread_index=None),), maxvl=32)",
 312             "OpProperties(kind=OpKind.SvLI, "
 313             "inputs=("
 314             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 315             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 316             "tied_input_index=None, spread_index=None),), "
 317             "outputs=("
 318             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 319             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 320             "tied_input_index=None, spread_index=None),), maxvl=32)",
 321             "OpProperties(kind=OpKind.SetVLI, "
 322             "inputs=(), "
 323             "outputs=("
 324             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 325             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 326             "tied_input_index=None, spread_index=None),), maxvl=1)",
 327             "OpProperties(kind=OpKind.VecCopyFromReg, "
 328             "inputs=("
 329             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 330             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 331             "tied_input_index=None, spread_index=None), "
 332             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 333             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 334             "tied_input_index=None, spread_index=None)), "
 335             "outputs=("
 336             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 337             "LocKind.GPR: FBitSet(range(14, 97)), "
 338             "LocKind.StackI64: FBitSet(range(0, 993))}), ty=<I64*32>), "
 339             "tied_input_index=None, spread_index=None),), maxvl=32)",
 340             "OpProperties(kind=OpKind.SetCA, "
 341             "inputs=(), "
 342             "outputs=("
 343             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 344             "LocKind.CA: FBitSet([0])}), ty=<CA>), "
 345             "tied_input_index=None, spread_index=None),), maxvl=1)",
 346             "OpProperties(kind=OpKind.SetVLI, "
 347             "inputs=(), "
 348             "outputs=("
 349             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 350             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 351             "tied_input_index=None, spread_index=None),), maxvl=1)",
 352             "OpProperties(kind=OpKind.VecCopyToReg, "
 353             "inputs=("
 354             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 355             "LocKind.GPR: FBitSet(range(14, 97)), "
 356             "LocKind.StackI64: FBitSet(range(0, 993))}), ty=<I64*32>), "
 357             "tied_input_index=None, spread_index=None), "
 358             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 359             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 360             "tied_input_index=None, spread_index=None)), "
 361             "outputs=("
 362             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 363             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 364             "tied_input_index=None, spread_index=None),), maxvl=32)",
 365             "OpProperties(kind=OpKind.SetVLI, "
 366             "inputs=(), "
 367             "outputs=("
 368             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 369             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 370             "tied_input_index=None, spread_index=None),), maxvl=1)",
 371             "OpProperties(kind=OpKind.VecCopyToReg, "
 372             "inputs=("
 373             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 374             "LocKind.GPR: FBitSet(range(14, 97)), "
 375             "LocKind.StackI64: FBitSet(range(0, 993))}), ty=<I64*32>), "
 376             "tied_input_index=None, spread_index=None), "
 377             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 378             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 379             "tied_input_index=None, spread_index=None)), "
 380             "outputs=("
 381             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 382             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 383             "tied_input_index=None, spread_index=None),), maxvl=32)",
 384             "OpProperties(kind=OpKind.SvAddE, "
 385             "inputs=("
 386             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 387             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 388             "tied_input_index=None, spread_index=None), "
 389             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 390             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 391             "tied_input_index=None, spread_index=None), "
 392             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 393             "LocKind.CA: FBitSet([0])}), ty=<CA>), "
 394             "tied_input_index=None, spread_index=None), "
 395             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 396             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 397             "tied_input_index=None, spread_index=None)), "
 398             "outputs=("
 399             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 400             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 401             "tied_input_index=None, spread_index=None), "
 402             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 403             "LocKind.CA: FBitSet([0])}), ty=<CA>), "
 404             "tied_input_index=None, spread_index=None)), maxvl=32)",
 405             "OpProperties(kind=OpKind.SetVLI, "
 406             "inputs=(), "
 407             "outputs=("
 408             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 409             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 410             "tied_input_index=None, spread_index=None),), maxvl=1)",
 411             "OpProperties(kind=OpKind.VecCopyFromReg, "
 412             "inputs=("
 413             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 414             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 415             "tied_input_index=None, spread_index=None), "
 416             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 417             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 418             "tied_input_index=None, spread_index=None)), "
 419             "outputs=("
 420             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 421             "LocKind.GPR: FBitSet(range(14, 97)), "
 422             "LocKind.StackI64: FBitSet(range(0, 993))}), ty=<I64*32>), "
 423             "tied_input_index=None, spread_index=None),), maxvl=32)",
 424             "OpProperties(kind=OpKind.SetVLI, "
 425             "inputs=(), "
 426             "outputs=("
 427             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 428             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 429             "tied_input_index=None, spread_index=None),), maxvl=1)",
 430             "OpProperties(kind=OpKind.VecCopyToReg, "
 431             "inputs=("
 432             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 433             "LocKind.GPR: FBitSet(range(14, 97)), "
 434             "LocKind.StackI64: FBitSet(range(0, 993))}), ty=<I64*32>), "
 435             "tied_input_index=None, spread_index=None), "
 436             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 437             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 438             "tied_input_index=None, spread_index=None)), "
 439             "outputs=("
 440             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 441             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 442             "tied_input_index=None, spread_index=None),), maxvl=32)",
 443             "OpProperties(kind=OpKind.CopyToReg, "
 444             "inputs=("
 445             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 446             "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)]), "
 447             "LocKind.StackI64: FBitSet(range(0, 1024))}), ty=<I64>), "
 448             "tied_input_index=None, spread_index=None),), "
 449             "outputs=("
 450             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 451             "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
 452             "ty=<I64>), "
 453             "tied_input_index=None, spread_index=None),), maxvl=1)",
 454             "OpProperties(kind=OpKind.SvStd, "
 455             "inputs=("
 456             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 457             "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
 458             "tied_input_index=None, spread_index=None), "
 459             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 460             "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
 461             "ty=<I64>), "
 462             "tied_input_index=None, spread_index=None), "
 463             "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
 464             "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
 465             "tied_input_index=None, spread_index=None)), "
 466             "outputs=(), maxvl=32)",
 467         ])
 468
 469     def test_sim(self):
 470         fn, arg = self.make_add_fn()
 471         addr = 0x100
 472         state = PreRASimState(ssa_vals={arg: (addr,)}, memory={})
 473         state.store(addr=addr, value=0xffffffff_ffffffff,
 474                     size_in_bytes=GPR_SIZE_IN_BYTES)
 475         state.store(addr=addr + GPR_SIZE_IN_BYTES, value=0xabcdef01_23456789,
 476                     size_in_bytes=GPR_SIZE_IN_BYTES)
 477         self.assertEqual(
 478             repr(state),
 479             "PreRASimState(ssa_vals={<arg.outputs[0]: <I64>>: (0x100,)}, "
 480             "memory={\n"
 481             "0x00100: <0xffffffffffffffff>,\n"
 482             "0x00108: <0xabcdef0123456789>})")
 483         fn.pre_ra_sim(state)
 484         self.assertEqual(
 485             repr(state),
 486             "PreRASimState(ssa_vals={\n"
 487             "<arg.outputs[0]: <I64>>: (0x100,),\n"
 488             "<vl.outputs[0]: <VL_MAXVL>>: (0x20,),\n"
 489             "<ld.outputs[0]: <I64*32>>: (\n"
 490             "    0xffffffffffffffff, 0xabcdef0123456789, 0x0, 0x0,\n"
 491             "    0x0, 0x0, 0x0, 0x0,\n"
 492             "    0x0, 0x0, 0x0, 0x0,\n"
 493             "    0x0, 0x0, 0x0, 0x0,\n"
 494             "    0x0, 0x0, 0x0, 0x0,\n"
 495             "    0x0, 0x0, 0x0, 0x0,\n"
 496             "    0x0, 0x0, 0x0, 0x0,\n"
 497             "    0x0, 0x0, 0x0, 0x0),\n"
 498             "<li.outputs[0]: <I64*32>>: (\n"
 499             "    0x0, 0x0, 0x0, 0x0,\n"
 500             "    0x0, 0x0, 0x0, 0x0,\n"
 501             "    0x0, 0x0, 0x0, 0x0,\n"
 502             "    0x0, 0x0, 0x0, 0x0,\n"
 503             "    0x0, 0x0, 0x0, 0x0,\n"
 504             "    0x0, 0x0, 0x0, 0x0,\n"
 505             "    0x0, 0x0, 0x0, 0x0,\n"
 506             "    0x0, 0x0, 0x0, 0x0),\n"
 507             "<ca.outputs[0]: <CA>>: (0x1,),\n"
 508             "<add.outputs[0]: <I64*32>>: (\n"
 509             "    0x0, 0xabcdef012345678a, 0x0, 0x0,\n"
 510             "    0x0, 0x0, 0x0, 0x0,\n"
 511             "    0x0, 0x0, 0x0, 0x0,\n"
 512             "    0x0, 0x0, 0x0, 0x0,\n"
 513             "    0x0, 0x0, 0x0, 0x0,\n"
 514             "    0x0, 0x0, 0x0, 0x0,\n"
 515             "    0x0, 0x0, 0x0, 0x0,\n"
 516             "    0x0, 0x0, 0x0, 0x0),\n"
 517             "<add.outputs[1]: <CA>>: (0x0,),\n"
 518             "}, memory={\n"
 519             "0x00100: <0x0000000000000000>,\n"
 520             "0x00108: <0xabcdef012345678a>,\n"
 521             "0x00110: <0x0000000000000000>,\n"
 522             "0x00118: <0x0000000000000000>,\n"
 523             "0x00120: <0x0000000000000000>,\n"
 524             "0x00128: <0x0000000000000000>,\n"
 525             "0x00130: <0x0000000000000000>,\n"
 526             "0x00138: <0x0000000000000000>,\n"
 527             "0x00140: <0x0000000000000000>,\n"
 528             "0x00148: <0x0000000000000000>,\n"
 529             "0x00150: <0x0000000000000000>,\n"
 530             "0x00158: <0x0000000000000000>,\n"
 531             "0x00160: <0x0000000000000000>,\n"
 532             "0x00168: <0x0000000000000000>,\n"
 533             "0x00170: <0x0000000000000000>,\n"
 534             "0x00178: <0x0000000000000000>,\n"
 535             "0x00180: <0x0000000000000000>,\n"
 536             "0x00188: <0x0000000000000000>,\n"
 537             "0x00190: <0x0000000000000000>,\n"
 538             "0x00198: <0x0000000000000000>,\n"
 539             "0x001a0: <0x0000000000000000>,\n"
 540             "0x001a8: <0x0000000000000000>,\n"
 541             "0x001b0: <0x0000000000000000>,\n"
 542             "0x001b8: <0x0000000000000000>,\n"
 543             "0x001c0: <0x0000000000000000>,\n"
 544             "0x001c8: <0x0000000000000000>,\n"
 545             "0x001d0: <0x0000000000000000>,\n"
 546             "0x001d8: <0x0000000000000000>,\n"
 547             "0x001e0: <0x0000000000000000>,\n"
 548             "0x001e8: <0x0000000000000000>,\n"
 549             "0x001f0: <0x0000000000000000>,\n"
 550             "0x001f8: <0x0000000000000000>})")
 551
 552
 553 if __name__ == "__main__":
 554     unittest.main()