add op.properties to repr tests
[bigint-presentation-code.git] / src / bigint_presentation_code / _tests / test_compiler_ir2.py
1 import unittest
2
3 from bigint_presentation_code.compiler_ir2 import (GPR_SIZE_IN_BYTES, Fn,
4 OpKind, PreRASimState,
5 SSAVal)
6
7
8 class TestCompilerIR(unittest.TestCase):
9 maxDiff = None
10
11 def make_add_fn(self):
12 # type: () -> tuple[Fn, SSAVal]
13 fn = Fn()
14 op0 = fn.append_new_op(OpKind.FuncArgR3, name="arg")
15 arg = op0.outputs[0]
16 MAXVL = 32
17 op1 = fn.append_new_op(OpKind.SetVLI, immediates=[MAXVL], name="vl")
18 vl = op1.outputs[0]
19 op2 = fn.append_new_op(
20 OpKind.SvLd, inputs=[arg, vl], immediates=[0], maxvl=MAXVL,
21 name="ld")
22 a = op2.outputs[0]
23 op3 = fn.append_new_op(
24 OpKind.SvLI, inputs=[vl], immediates=[0], maxvl=MAXVL, name="li")
25 b = op3.outputs[0]
26 op4 = fn.append_new_op(OpKind.SetCA, name="ca")
27 ca = op4.outputs[0]
28 op5 = fn.append_new_op(
29 OpKind.SvAddE, inputs=[a, b, ca, vl], maxvl=MAXVL, name="add")
30 s = op5.outputs[0]
31 fn.append_new_op(
32 OpKind.SvStd, inputs=[s, arg, vl], immediates=[0], maxvl=MAXVL,
33 name="st")
34 return fn, arg
35
36 def test_repr(self):
37 fn, _arg = self.make_add_fn()
38 self.assertEqual([repr(i) for i in fn.ops], [
39 "Op(kind=OpKind.FuncArgR3, "
40 "inputs=[], "
41 "immediates=[], "
42 "outputs=(<arg#0: <I64>>,), name='arg')",
43 "Op(kind=OpKind.SetVLI, "
44 "inputs=[], "
45 "immediates=[32], "
46 "outputs=(<vl#0: <VL_MAXVL>>,), name='vl')",
47 "Op(kind=OpKind.SvLd, "
48 "inputs=[<arg#0: <I64>>, <vl#0: <VL_MAXVL>>], "
49 "immediates=[0], "
50 "outputs=(<ld#0: <I64*32>>,), name='ld')",
51 "Op(kind=OpKind.SvLI, "
52 "inputs=[<vl#0: <VL_MAXVL>>], "
53 "immediates=[0], "
54 "outputs=(<li#0: <I64*32>>,), name='li')",
55 "Op(kind=OpKind.SetCA, "
56 "inputs=[], "
57 "immediates=[], "
58 "outputs=(<ca#0: <CA>>,), name='ca')",
59 "Op(kind=OpKind.SvAddE, "
60 "inputs=[<ld#0: <I64*32>>, <li#0: <I64*32>>, <ca#0: <CA>>, "
61 "<vl#0: <VL_MAXVL>>], "
62 "immediates=[], "
63 "outputs=(<add#0: <I64*32>>, <add#1: <CA>>), name='add')",
64 "Op(kind=OpKind.SvStd, "
65 "inputs=[<add#0: <I64*32>>, <arg#0: <I64>>, <vl#0: <VL_MAXVL>>], "
66 "immediates=[0], "
67 "outputs=(), name='st')",
68 ])
69 self.assertEqual([repr(op.properties) for op in fn.ops], [
70 "OpProperties(kind=OpKind.FuncArgR3, "
71 "inputs=(), "
72 "outputs=("
73 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
74 "LocKind.GPR: FBitSet([3])}), ty=<I64>), "
75 "tied_input_index=None, spread_index=None),), maxvl=1)",
76 "OpProperties(kind=OpKind.SetVLI, "
77 "inputs=(), "
78 "outputs=("
79 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
80 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
81 "tied_input_index=None, spread_index=None),), maxvl=1)",
82 "OpProperties(kind=OpKind.SvLd, "
83 "inputs=("
84 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
85 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
86 "ty=<I64>), "
87 "tied_input_index=None, spread_index=None), "
88 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
89 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
90 "tied_input_index=None, spread_index=None)), "
91 "outputs=("
92 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
93 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
94 "tied_input_index=None, spread_index=None),), maxvl=32)",
95 "OpProperties(kind=OpKind.SvLI, "
96 "inputs=("
97 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
98 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
99 "tied_input_index=None, spread_index=None),), "
100 "outputs=("
101 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
102 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
103 "tied_input_index=None, spread_index=None),), maxvl=32)",
104 "OpProperties(kind=OpKind.SetCA, "
105 "inputs=(), "
106 "outputs=("
107 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
108 "LocKind.CA: FBitSet([0])}), ty=<CA>), "
109 "tied_input_index=None, spread_index=None),), maxvl=1)",
110 "OpProperties(kind=OpKind.SvAddE, "
111 "inputs=("
112 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
113 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
114 "tied_input_index=None, spread_index=None), "
115 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
116 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
117 "tied_input_index=None, spread_index=None), "
118 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
119 "LocKind.CA: FBitSet([0])}), ty=<CA>), "
120 "tied_input_index=None, spread_index=None), "
121 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
122 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
123 "tied_input_index=None, spread_index=None)), "
124 "outputs=("
125 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
126 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
127 "tied_input_index=None, spread_index=None), "
128 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
129 "LocKind.CA: FBitSet([0])}), ty=<CA>), "
130 "tied_input_index=None, spread_index=None)), maxvl=32)",
131 "OpProperties(kind=OpKind.SvStd, "
132 "inputs=("
133 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
134 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
135 "tied_input_index=None, spread_index=None), "
136 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
137 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
138 "ty=<I64>), "
139 "tied_input_index=None, spread_index=None), "
140 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
141 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
142 "tied_input_index=None, spread_index=None)), "
143 "outputs=(), maxvl=32)",
144 ])
145
146 def test_pre_ra_insert_copies(self):
147 fn, _arg = self.make_add_fn()
148 fn.pre_ra_insert_copies()
149 self.assertEqual([repr(i) for i in fn.ops], [
150 "Op(kind=OpKind.FuncArgR3, "
151 "inputs=[], "
152 "immediates=[], "
153 "outputs=(<arg#0: <I64>>,), name='arg')",
154 "Op(kind=OpKind.CopyFromReg, "
155 "inputs=[<arg#0: <I64>>], "
156 "immediates=[], "
157 "outputs=(<2#0: <I64>>,), name='2')",
158 "Op(kind=OpKind.SetVLI, "
159 "inputs=[], "
160 "immediates=[32], "
161 "outputs=(<vl#0: <VL_MAXVL>>,), name='vl')",
162 "Op(kind=OpKind.CopyToReg, "
163 "inputs=[<2#0: <I64>>], "
164 "immediates=[], "
165 "outputs=(<3#0: <I64>>,), name='3')",
166 "Op(kind=OpKind.SvLd, "
167 "inputs=[<3#0: <I64>>, <vl#0: <VL_MAXVL>>], "
168 "immediates=[0], "
169 "outputs=(<ld#0: <I64*32>>,), name='ld')",
170 "Op(kind=OpKind.SetVLI, "
171 "inputs=[], "
172 "immediates=[32], "
173 "outputs=(<4#0: <VL_MAXVL>>,), name='4')",
174 "Op(kind=OpKind.VecCopyFromReg, "
175 "inputs=[<ld#0: <I64*32>>, <4#0: <VL_MAXVL>>], "
176 "immediates=[], "
177 "outputs=(<5#0: <I64*32>>,), name='5')",
178 "Op(kind=OpKind.SvLI, "
179 "inputs=[<vl#0: <VL_MAXVL>>], "
180 "immediates=[0], "
181 "outputs=(<li#0: <I64*32>>,), name='li')",
182 "Op(kind=OpKind.SetVLI, "
183 "inputs=[], "
184 "immediates=[32], "
185 "outputs=(<6#0: <VL_MAXVL>>,), name='6')",
186 "Op(kind=OpKind.VecCopyFromReg, "
187 "inputs=[<li#0: <I64*32>>, <6#0: <VL_MAXVL>>], "
188 "immediates=[], "
189 "outputs=(<7#0: <I64*32>>,), name='7')",
190 "Op(kind=OpKind.SetCA, "
191 "inputs=[], "
192 "immediates=[], "
193 "outputs=(<ca#0: <CA>>,), name='ca')",
194 "Op(kind=OpKind.SetVLI, "
195 "inputs=[], "
196 "immediates=[32], "
197 "outputs=(<8#0: <VL_MAXVL>>,), name='8')",
198 "Op(kind=OpKind.VecCopyToReg, "
199 "inputs=[<5#0: <I64*32>>, <8#0: <VL_MAXVL>>], "
200 "immediates=[], "
201 "outputs=(<9#0: <I64*32>>,), name='9')",
202 "Op(kind=OpKind.SetVLI, "
203 "inputs=[], "
204 "immediates=[32], "
205 "outputs=(<10#0: <VL_MAXVL>>,), name='10')",
206 "Op(kind=OpKind.VecCopyToReg, "
207 "inputs=[<7#0: <I64*32>>, <10#0: <VL_MAXVL>>], "
208 "immediates=[], "
209 "outputs=(<11#0: <I64*32>>,), name='11')",
210 "Op(kind=OpKind.SvAddE, "
211 "inputs=[<9#0: <I64*32>>, <11#0: <I64*32>>, <ca#0: <CA>>, "
212 "<vl#0: <VL_MAXVL>>], "
213 "immediates=[], "
214 "outputs=(<add#0: <I64*32>>, <add#1: <CA>>), name='add')",
215 "Op(kind=OpKind.SetVLI, "
216 "inputs=[], "
217 "immediates=[32], "
218 "outputs=(<12#0: <VL_MAXVL>>,), name='12')",
219 "Op(kind=OpKind.VecCopyFromReg, "
220 "inputs=[<add#0: <I64*32>>, <12#0: <VL_MAXVL>>], "
221 "immediates=[], "
222 "outputs=(<13#0: <I64*32>>,), name='13')",
223 "Op(kind=OpKind.SetVLI, "
224 "inputs=[], "
225 "immediates=[32], "
226 "outputs=(<14#0: <VL_MAXVL>>,), name='14')",
227 "Op(kind=OpKind.VecCopyToReg, "
228 "inputs=[<13#0: <I64*32>>, <14#0: <VL_MAXVL>>], "
229 "immediates=[], "
230 "outputs=(<15#0: <I64*32>>,), name='15')",
231 "Op(kind=OpKind.CopyToReg, "
232 "inputs=[<2#0: <I64>>], "
233 "immediates=[], "
234 "outputs=(<16#0: <I64>>,), name='16')",
235 "Op(kind=OpKind.SvStd, "
236 "inputs=[<15#0: <I64*32>>, <16#0: <I64>>, <vl#0: <VL_MAXVL>>], "
237 "immediates=[0], "
238 "outputs=(), name='st')",
239 ])
240 self.assertEqual([repr(op.properties) for op in fn.ops], [
241 "OpProperties(kind=OpKind.FuncArgR3, "
242 "inputs=(), "
243 "outputs=("
244 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
245 "LocKind.GPR: FBitSet([3])}), ty=<I64>), "
246 "tied_input_index=None, spread_index=None),), maxvl=1)",
247 "OpProperties(kind=OpKind.CopyFromReg, "
248 "inputs=("
249 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
250 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
251 "ty=<I64>), "
252 "tied_input_index=None, spread_index=None),), "
253 "outputs=("
254 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
255 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)]), "
256 "LocKind.StackI64: FBitSet(range(0, 1024))}), ty=<I64>), "
257 "tied_input_index=None, spread_index=None),), maxvl=1)",
258 "OpProperties(kind=OpKind.SetVLI, "
259 "inputs=(), "
260 "outputs=("
261 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
262 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
263 "tied_input_index=None, spread_index=None),), maxvl=1)",
264 "OpProperties(kind=OpKind.CopyToReg, "
265 "inputs=("
266 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
267 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)]), "
268 "LocKind.StackI64: FBitSet(range(0, 1024))}), ty=<I64>), "
269 "tied_input_index=None, spread_index=None),), "
270 "outputs=("
271 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
272 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
273 "ty=<I64>), "
274 "tied_input_index=None, spread_index=None),), maxvl=1)",
275 "OpProperties(kind=OpKind.SvLd, "
276 "inputs=("
277 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
278 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
279 "ty=<I64>), "
280 "tied_input_index=None, spread_index=None), "
281 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
282 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
283 "tied_input_index=None, spread_index=None)), "
284 "outputs=("
285 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
286 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
287 "tied_input_index=None, spread_index=None),), maxvl=32)",
288 "OpProperties(kind=OpKind.SetVLI, "
289 "inputs=(), "
290 "outputs=("
291 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
292 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
293 "tied_input_index=None, spread_index=None),), maxvl=1)",
294 "OpProperties(kind=OpKind.VecCopyFromReg, "
295 "inputs=("
296 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
297 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
298 "tied_input_index=None, spread_index=None), "
299 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
300 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
301 "tied_input_index=None, spread_index=None)), "
302 "outputs=("
303 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
304 "LocKind.GPR: FBitSet(range(14, 97)), "
305 "LocKind.StackI64: FBitSet(range(0, 993))}), ty=<I64*32>), "
306 "tied_input_index=None, spread_index=None),), maxvl=32)",
307 "OpProperties(kind=OpKind.SvLI, "
308 "inputs=("
309 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
310 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
311 "tied_input_index=None, spread_index=None),), "
312 "outputs=("
313 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
314 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
315 "tied_input_index=None, spread_index=None),), maxvl=32)",
316 "OpProperties(kind=OpKind.SetVLI, "
317 "inputs=(), "
318 "outputs=("
319 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
320 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
321 "tied_input_index=None, spread_index=None),), maxvl=1)",
322 "OpProperties(kind=OpKind.VecCopyFromReg, "
323 "inputs=("
324 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
325 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
326 "tied_input_index=None, spread_index=None), "
327 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
328 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
329 "tied_input_index=None, spread_index=None)), "
330 "outputs=("
331 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
332 "LocKind.GPR: FBitSet(range(14, 97)), "
333 "LocKind.StackI64: FBitSet(range(0, 993))}), ty=<I64*32>), "
334 "tied_input_index=None, spread_index=None),), maxvl=32)",
335 "OpProperties(kind=OpKind.SetCA, "
336 "inputs=(), "
337 "outputs=("
338 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
339 "LocKind.CA: FBitSet([0])}), ty=<CA>), "
340 "tied_input_index=None, spread_index=None),), maxvl=1)",
341 "OpProperties(kind=OpKind.SetVLI, "
342 "inputs=(), "
343 "outputs=("
344 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
345 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
346 "tied_input_index=None, spread_index=None),), maxvl=1)",
347 "OpProperties(kind=OpKind.VecCopyToReg, "
348 "inputs=("
349 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
350 "LocKind.GPR: FBitSet(range(14, 97)), "
351 "LocKind.StackI64: FBitSet(range(0, 993))}), ty=<I64*32>), "
352 "tied_input_index=None, spread_index=None), "
353 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
354 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
355 "tied_input_index=None, spread_index=None)), "
356 "outputs=("
357 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
358 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
359 "tied_input_index=None, spread_index=None),), maxvl=32)",
360 "OpProperties(kind=OpKind.SetVLI, "
361 "inputs=(), "
362 "outputs=("
363 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
364 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
365 "tied_input_index=None, spread_index=None),), maxvl=1)",
366 "OpProperties(kind=OpKind.VecCopyToReg, "
367 "inputs=("
368 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
369 "LocKind.GPR: FBitSet(range(14, 97)), "
370 "LocKind.StackI64: FBitSet(range(0, 993))}), ty=<I64*32>), "
371 "tied_input_index=None, spread_index=None), "
372 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
373 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
374 "tied_input_index=None, spread_index=None)), "
375 "outputs=("
376 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
377 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
378 "tied_input_index=None, spread_index=None),), maxvl=32)",
379 "OpProperties(kind=OpKind.SvAddE, "
380 "inputs=("
381 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
382 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
383 "tied_input_index=None, spread_index=None), "
384 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
385 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
386 "tied_input_index=None, spread_index=None), "
387 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
388 "LocKind.CA: FBitSet([0])}), ty=<CA>), "
389 "tied_input_index=None, spread_index=None), "
390 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
391 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
392 "tied_input_index=None, spread_index=None)), "
393 "outputs=("
394 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
395 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
396 "tied_input_index=None, spread_index=None), "
397 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
398 "LocKind.CA: FBitSet([0])}), ty=<CA>), "
399 "tied_input_index=None, spread_index=None)), maxvl=32)",
400 "OpProperties(kind=OpKind.SetVLI, "
401 "inputs=(), "
402 "outputs=("
403 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
404 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
405 "tied_input_index=None, spread_index=None),), maxvl=1)",
406 "OpProperties(kind=OpKind.VecCopyFromReg, "
407 "inputs=("
408 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
409 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
410 "tied_input_index=None, spread_index=None), "
411 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
412 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
413 "tied_input_index=None, spread_index=None)), "
414 "outputs=("
415 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
416 "LocKind.GPR: FBitSet(range(14, 97)), "
417 "LocKind.StackI64: FBitSet(range(0, 993))}), ty=<I64*32>), "
418 "tied_input_index=None, spread_index=None),), maxvl=32)",
419 "OpProperties(kind=OpKind.SetVLI, "
420 "inputs=(), "
421 "outputs=("
422 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
423 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
424 "tied_input_index=None, spread_index=None),), maxvl=1)",
425 "OpProperties(kind=OpKind.VecCopyToReg, "
426 "inputs=("
427 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
428 "LocKind.GPR: FBitSet(range(14, 97)), "
429 "LocKind.StackI64: FBitSet(range(0, 993))}), ty=<I64*32>), "
430 "tied_input_index=None, spread_index=None), "
431 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
432 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
433 "tied_input_index=None, spread_index=None)), "
434 "outputs=("
435 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
436 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
437 "tied_input_index=None, spread_index=None),), maxvl=32)",
438 "OpProperties(kind=OpKind.CopyToReg, "
439 "inputs=("
440 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
441 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)]), "
442 "LocKind.StackI64: FBitSet(range(0, 1024))}), ty=<I64>), "
443 "tied_input_index=None, spread_index=None),), "
444 "outputs=("
445 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
446 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
447 "ty=<I64>), "
448 "tied_input_index=None, spread_index=None),), maxvl=1)",
449 "OpProperties(kind=OpKind.SvStd, "
450 "inputs=("
451 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
452 "LocKind.GPR: FBitSet(range(14, 97))}), ty=<I64*32>), "
453 "tied_input_index=None, spread_index=None), "
454 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
455 "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), "
456 "ty=<I64>), "
457 "tied_input_index=None, spread_index=None), "
458 "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({"
459 "LocKind.VL_MAXVL: FBitSet([0])}), ty=<VL_MAXVL>), "
460 "tied_input_index=None, spread_index=None)), "
461 "outputs=(), maxvl=32)",
462 ])
463
464 def test_sim(self):
465 fn, arg = self.make_add_fn()
466 addr = 0x100
467 state = PreRASimState(ssa_vals={arg: (addr,)}, memory={})
468 state.store(addr=addr, value=0xffffffff_ffffffff,
469 size_in_bytes=GPR_SIZE_IN_BYTES)
470 state.store(addr=addr + GPR_SIZE_IN_BYTES, value=0xabcdef01_23456789,
471 size_in_bytes=GPR_SIZE_IN_BYTES)
472 self.assertEqual(
473 repr(state),
474 "PreRASimState(ssa_vals={<arg#0: <I64>>: (0x100,)}, memory={\n"
475 "0x00100: <0xffffffffffffffff>,\n"
476 "0x00108: <0xabcdef0123456789>})")
477 fn.pre_ra_sim(state)
478 self.assertEqual(
479 repr(state),
480 "PreRASimState(ssa_vals={\n"
481 "<arg#0: <I64>>: (0x100,),\n"
482 "<vl#0: <VL_MAXVL>>: (0x20,),\n"
483 "<ld#0: <I64*32>>: (\n"
484 " 0xffffffffffffffff, 0xabcdef0123456789, 0x0, 0x0,\n"
485 " 0x0, 0x0, 0x0, 0x0,\n"
486 " 0x0, 0x0, 0x0, 0x0,\n"
487 " 0x0, 0x0, 0x0, 0x0,\n"
488 " 0x0, 0x0, 0x0, 0x0,\n"
489 " 0x0, 0x0, 0x0, 0x0,\n"
490 " 0x0, 0x0, 0x0, 0x0,\n"
491 " 0x0, 0x0, 0x0, 0x0),\n"
492 "<li#0: <I64*32>>: (\n"
493 " 0x0, 0x0, 0x0, 0x0,\n"
494 " 0x0, 0x0, 0x0, 0x0,\n"
495 " 0x0, 0x0, 0x0, 0x0,\n"
496 " 0x0, 0x0, 0x0, 0x0,\n"
497 " 0x0, 0x0, 0x0, 0x0,\n"
498 " 0x0, 0x0, 0x0, 0x0,\n"
499 " 0x0, 0x0, 0x0, 0x0,\n"
500 " 0x0, 0x0, 0x0, 0x0),\n"
501 "<ca#0: <CA>>: (0x1,),\n"
502 "<add#0: <I64*32>>: (\n"
503 " 0x0, 0xabcdef012345678a, 0x0, 0x0,\n"
504 " 0x0, 0x0, 0x0, 0x0,\n"
505 " 0x0, 0x0, 0x0, 0x0,\n"
506 " 0x0, 0x0, 0x0, 0x0,\n"
507 " 0x0, 0x0, 0x0, 0x0,\n"
508 " 0x0, 0x0, 0x0, 0x0,\n"
509 " 0x0, 0x0, 0x0, 0x0,\n"
510 " 0x0, 0x0, 0x0, 0x0),\n"
511 "<add#1: <CA>>: (0x0,),\n"
512 "}, memory={\n"
513 "0x00100: <0x0000000000000000>,\n"
514 "0x00108: <0xabcdef012345678a>,\n"
515 "0x00110: <0x0000000000000000>,\n"
516 "0x00118: <0x0000000000000000>,\n"
517 "0x00120: <0x0000000000000000>,\n"
518 "0x00128: <0x0000000000000000>,\n"
519 "0x00130: <0x0000000000000000>,\n"
520 "0x00138: <0x0000000000000000>,\n"
521 "0x00140: <0x0000000000000000>,\n"
522 "0x00148: <0x0000000000000000>,\n"
523 "0x00150: <0x0000000000000000>,\n"
524 "0x00158: <0x0000000000000000>,\n"
525 "0x00160: <0x0000000000000000>,\n"
526 "0x00168: <0x0000000000000000>,\n"
527 "0x00170: <0x0000000000000000>,\n"
528 "0x00178: <0x0000000000000000>,\n"
529 "0x00180: <0x0000000000000000>,\n"
530 "0x00188: <0x0000000000000000>,\n"
531 "0x00190: <0x0000000000000000>,\n"
532 "0x00198: <0x0000000000000000>,\n"
533 "0x001a0: <0x0000000000000000>,\n"
534 "0x001a8: <0x0000000000000000>,\n"
535 "0x001b0: <0x0000000000000000>,\n"
536 "0x001b8: <0x0000000000000000>,\n"
537 "0x001c0: <0x0000000000000000>,\n"
538 "0x001c8: <0x0000000000000000>,\n"
539 "0x001d0: <0x0000000000000000>,\n"
540 "0x001d8: <0x0000000000000000>,\n"
541 "0x001e0: <0x0000000000000000>,\n"
542 "0x001e8: <0x0000000000000000>,\n"
543 "0x001f0: <0x0000000000000000>,\n"
544 "0x001f8: <0x0000000000000000>})")
545
546
547 if __name__ == "__main__":
548 unittest.main()