src/bigint_presentation_code/_tests/test_register_allocator.py

   1 import sys
   2 import unittest
   3 import shutil
   4
   5 from bigint_presentation_code.compiler_ir import (Fn, GenAsmState, OpKind,
   6                                                   SSAVal)
   7 from bigint_presentation_code.register_allocator import allocate_registers
   8 from nmutil.get_test_path import get_test_path
   9
  10
  11 def dump_graphs(test_case, graphs):
  12     # type: (unittest.TestCase, dict[str, str]) -> None
  13     base_path = get_test_path(test_case, "dumped_graphs")
  14     shutil.rmtree(base_path, ignore_errors=True)
  15     base_path.mkdir(parents=True, exist_ok=True)
  16     for name, dot in graphs.items():
  17         path = base_path / name
  18         dot_path = path.with_suffix(".dot")
  19         dot_path.write_text(dot)
  20
  21
  22 class TestRegisterAllocator(unittest.TestCase):
  23     maxDiff = None
  24
  25     def make_add_fn(self):
  26         # type: () -> tuple[Fn, SSAVal]
  27         fn = Fn()
  28         op0 = fn.append_new_op(OpKind.FuncArgR3, name="arg")
  29         arg = op0.outputs[0]
  30         MAXVL = 32
  31         op1 = fn.append_new_op(OpKind.SetVLI, immediates=[MAXVL], name="vl")
  32         vl = op1.outputs[0]
  33         op2 = fn.append_new_op(
  34             OpKind.SvLd, input_vals=[arg, vl], immediates=[0], maxvl=MAXVL,
  35             name="ld")
  36         a = op2.outputs[0]
  37         op3 = fn.append_new_op(OpKind.SvLI, input_vals=[vl], immediates=[0],
  38                                maxvl=MAXVL, name="li")
  39         b = op3.outputs[0]
  40         op4 = fn.append_new_op(OpKind.SetCA, name="ca")
  41         ca = op4.outputs[0]
  42         op5 = fn.append_new_op(
  43             OpKind.SvAddE, input_vals=[a, b, ca, vl], maxvl=MAXVL, name="add")
  44         s = op5.outputs[0]
  45         _ = fn.append_new_op(OpKind.SvStd, input_vals=[s, arg, vl],
  46                              immediates=[0], maxvl=MAXVL, name="st")
  47         return fn, arg
  48
  49     def test_register_allocate(self):
  50         fn, _arg = self.make_add_fn()
  51         reg_assignments = allocate_registers(fn)
  52
  53         self.assertEqual(
  54             repr(reg_assignments),
  55             "{<add.outputs[0]: <I64*32>>: "
  56             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
  57             "<add.inp1.copy.outputs[0]: <I64*32>>: "
  58             "Loc(kind=LocKind.GPR, start=46, reg_len=32), "
  59             "<add.inp0.copy.outputs[0]: <I64*32>>: "
  60             "Loc(kind=LocKind.GPR, start=78, reg_len=32), "
  61             "<st.inp2.setvl.outputs[0]: <VL_MAXVL>>: "
  62             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  63             "<st.inp1.copy.outputs[0]: <I64>>: "
  64             "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
  65             "<st.inp0.copy.outputs[0]: <I64*32>>: "
  66             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
  67             "<st.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
  68             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  69             "<add.out0.copy.outputs[0]: <I64*32>>: "
  70             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
  71             "<add.out0.setvl.outputs[0]: <VL_MAXVL>>: "
  72             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  73             "<ca.outputs[0]: <CA>>: "
  74             "Loc(kind=LocKind.CA, start=0, reg_len=1), "
  75             "<add.outputs[1]: <CA>>: "
  76             "Loc(kind=LocKind.CA, start=0, reg_len=1), "
  77             "<add.inp3.setvl.outputs[0]: <VL_MAXVL>>: "
  78             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  79             "<add.inp1.setvl.outputs[0]: <VL_MAXVL>>: "
  80             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  81             "<add.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
  82             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  83             "<li.out0.copy.outputs[0]: <I64*32>>: "
  84             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
  85             "<li.out0.setvl.outputs[0]: <VL_MAXVL>>: "
  86             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  87             "<li.outputs[0]: <I64*32>>: "
  88             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
  89             "<li.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
  90             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  91             "<ld.out0.copy.outputs[0]: <I64*32>>: "
  92             "Loc(kind=LocKind.GPR, start=46, reg_len=32), "
  93             "<ld.out0.setvl.outputs[0]: <VL_MAXVL>>: "
  94             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  95             "<ld.outputs[0]: <I64*32>>: "
  96             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
  97             "<ld.inp1.setvl.outputs[0]: <VL_MAXVL>>: "
  98             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  99             "<ld.inp0.copy.outputs[0]: <I64>>: "
 100             "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
 101             "<vl.outputs[0]: <VL_MAXVL>>: "
 102             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 103             "<arg.out0.copy.outputs[0]: <I64>>: "
 104             "Loc(kind=LocKind.GPR, start=4, reg_len=1), "
 105             "<arg.outputs[0]: <I64>>: "
 106             "Loc(kind=LocKind.GPR, start=3, reg_len=1)}"
 107         )
 108
 109     def test_gen_asm(self):
 110         fn, _arg = self.make_add_fn()
 111         reg_assignments = allocate_registers(fn)
 112
 113         self.assertEqual(
 114             repr(reg_assignments),
 115             "{<add.outputs[0]: <I64*32>>: "
 116             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 117             "<add.inp1.copy.outputs[0]: <I64*32>>: "
 118             "Loc(kind=LocKind.GPR, start=46, reg_len=32), "
 119             "<add.inp0.copy.outputs[0]: <I64*32>>: "
 120             "Loc(kind=LocKind.GPR, start=78, reg_len=32), "
 121             "<st.inp2.setvl.outputs[0]: <VL_MAXVL>>: "
 122             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 123             "<st.inp1.copy.outputs[0]: <I64>>: "
 124             "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
 125             "<st.inp0.copy.outputs[0]: <I64*32>>: "
 126             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 127             "<st.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
 128             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 129             "<add.out0.copy.outputs[0]: <I64*32>>: "
 130             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 131             "<add.out0.setvl.outputs[0]: <VL_MAXVL>>: "
 132             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 133             "<ca.outputs[0]: <CA>>: "
 134             "Loc(kind=LocKind.CA, start=0, reg_len=1), "
 135             "<add.outputs[1]: <CA>>: "
 136             "Loc(kind=LocKind.CA, start=0, reg_len=1), "
 137             "<add.inp3.setvl.outputs[0]: <VL_MAXVL>>: "
 138             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 139             "<add.inp1.setvl.outputs[0]: <VL_MAXVL>>: "
 140             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 141             "<add.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
 142             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 143             "<li.out0.copy.outputs[0]: <I64*32>>: "
 144             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 145             "<li.out0.setvl.outputs[0]: <VL_MAXVL>>: "
 146             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 147             "<li.outputs[0]: <I64*32>>: "
 148             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 149             "<li.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
 150             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 151             "<ld.out0.copy.outputs[0]: <I64*32>>: "
 152             "Loc(kind=LocKind.GPR, start=46, reg_len=32), "
 153             "<ld.out0.setvl.outputs[0]: <VL_MAXVL>>: "
 154             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 155             "<ld.outputs[0]: <I64*32>>: "
 156             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 157             "<ld.inp1.setvl.outputs[0]: <VL_MAXVL>>: "
 158             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 159             "<ld.inp0.copy.outputs[0]: <I64>>: "
 160             "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
 161             "<vl.outputs[0]: <VL_MAXVL>>: "
 162             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 163             "<arg.out0.copy.outputs[0]: <I64>>: "
 164             "Loc(kind=LocKind.GPR, start=4, reg_len=1), "
 165             "<arg.outputs[0]: <I64>>: "
 166             "Loc(kind=LocKind.GPR, start=3, reg_len=1)}"
 167         )
 168         state = GenAsmState(reg_assignments)
 169         fn.gen_asm(state)
 170         self.assertEqual(state.output, [
 171             'or 4, 3, 3',
 172             'setvl 0, 0, 32, 0, 1, 1',
 173             'or 3, 4, 4',
 174             'setvl 0, 0, 32, 0, 1, 1',
 175             'sv.ld *14, 0(3)',
 176             'setvl 0, 0, 32, 0, 1, 1',
 177             'sv.or *46, *14, *14',
 178             'setvl 0, 0, 32, 0, 1, 1',
 179             'sv.addi *14, 0, 0',
 180             'setvl 0, 0, 32, 0, 1, 1',
 181             'subfc 0, 0, 0',
 182             'setvl 0, 0, 32, 0, 1, 1',
 183             'sv.or *78, *46, *46',
 184             'setvl 0, 0, 32, 0, 1, 1',
 185             'sv.or *46, *14, *14',
 186             'setvl 0, 0, 32, 0, 1, 1',
 187             'sv.adde *14, *78, *46',
 188             'setvl 0, 0, 32, 0, 1, 1',
 189             'setvl 0, 0, 32, 0, 1, 1',
 190             'or 3, 4, 4',
 191             'setvl 0, 0, 32, 0, 1, 1',
 192             'sv.std *14, 0(3)',
 193         ])
 194
 195     def test_register_allocate_graphs(self):
 196         fn, _arg = self.make_add_fn()
 197         graphs = {}  # type: dict[str, str]
 198
 199         def dump_graph(name, dot):
 200             # type: (str, str) -> None
 201             self.assertNotIn(name, graphs, "duplicate graph name")
 202             graphs[name] = dot
 203         allocated = allocate_registers(fn, dump_graph=dump_graph)
 204         self.assertEqual(
 205             repr(allocated),
 206             "{"
 207             "<add.outputs[0]: <I64*32>>: "
 208             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 209             "<add.inp1.copy.outputs[0]: <I64*32>>: "
 210             "Loc(kind=LocKind.GPR, start=46, reg_len=32), "
 211             "<add.inp0.copy.outputs[0]: <I64*32>>: "
 212             "Loc(kind=LocKind.GPR, start=78, reg_len=32), "
 213             "<st.inp2.setvl.outputs[0]: <VL_MAXVL>>: "
 214             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 215             "<st.inp1.copy.outputs[0]: <I64>>: "
 216             "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
 217             "<st.inp0.copy.outputs[0]: <I64*32>>: "
 218             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 219             "<st.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
 220             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 221             "<add.out0.copy.outputs[0]: <I64*32>>: "
 222             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 223             "<add.out0.setvl.outputs[0]: <VL_MAXVL>>: "
 224             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 225             "<ca.outputs[0]: <CA>>: "
 226             "Loc(kind=LocKind.CA, start=0, reg_len=1), "
 227             "<add.outputs[1]: <CA>>: "
 228             "Loc(kind=LocKind.CA, start=0, reg_len=1), "
 229             "<add.inp3.setvl.outputs[0]: <VL_MAXVL>>: "
 230             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 231             "<add.inp1.setvl.outputs[0]: <VL_MAXVL>>: "
 232             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 233             "<add.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
 234             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 235             "<li.out0.copy.outputs[0]: <I64*32>>: "
 236             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 237             "<li.out0.setvl.outputs[0]: <VL_MAXVL>>: "
 238             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 239             "<li.outputs[0]: <I64*32>>: "
 240             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 241             "<li.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
 242             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 243             "<ld.out0.copy.outputs[0]: <I64*32>>: "
 244             "Loc(kind=LocKind.GPR, start=46, reg_len=32), "
 245             "<ld.out0.setvl.outputs[0]: <VL_MAXVL>>: "
 246             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 247             "<ld.outputs[0]: <I64*32>>: "
 248             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 249             "<ld.inp1.setvl.outputs[0]: <VL_MAXVL>>: "
 250             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 251             "<ld.inp0.copy.outputs[0]: <I64>>: "
 252             "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
 253             "<vl.outputs[0]: <VL_MAXVL>>: "
 254             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 255             "<arg.out0.copy.outputs[0]: <I64>>: "
 256             "Loc(kind=LocKind.GPR, start=4, reg_len=1), "
 257             "<arg.outputs[0]: <I64>>: "
 258             "Loc(kind=LocKind.GPR, start=3, reg_len=1)"
 259             "}"
 260         )
 261         dump_graphs(self, graphs)
 262         # FIXME: is_copy_related is not correct, it's missing a bunch of
 263         # edges (which aren't interference edges)
 264         self.assertEqual(graphs, {
 265             'initial':
 266             'graph {\n'
 267             '    "0" [label = "<arg.outputs[0]: <I64>>: 0"]\n'
 268             '    "1" [label = "<arg.out0.copy.outputs[0]: <I64>>: 0"]\n'
 269             '    "2" [label = "<vl.outputs[0]: <VL_MAXVL>>: 0"]\n'
 270             '    "3" [label = "<ld.inp0.copy.outputs[0]: <I64>>: 0"]\n'
 271             '    "4" [label = "<ld.inp1.setvl.outputs[0]: <VL_MAXVL>>: 0"]\n'
 272             '    "5" [label = "<ld.outputs[0]: <I64*32>>: 0"]\n'
 273             '    "6" [label = "<ld.out0.setvl.outputs[0]: <VL_MAXVL>>: 0"]\n'
 274             '    "7" [label = "<ld.out0.copy.outputs[0]: <I64*32>>: 0"]\n'
 275             '    "8" [label = "<li.inp0.setvl.outputs[0]: <VL_MAXVL>>: 0"]\n'
 276             '    "9" [label = "<li.outputs[0]: <I64*32>>: 0"]\n'
 277             '    "10" [label = "<li.out0.setvl.outputs[0]: <VL_MAXVL>>: 0"]\n'
 278             '    "11" [label = "<li.out0.copy.outputs[0]: <I64*32>>: 0"]\n'
 279             '    "12" [label = "<add.inp0.setvl.outputs[0]: <VL_MAXVL>>: 0"]\n'
 280             '    "13" [label = "<add.inp0.copy.outputs[0]: <I64*32>>: 0"]\n'
 281             '    "14" [label = "<add.inp1.setvl.outputs[0]: <VL_MAXVL>>: 0"]\n'
 282             '    "15" [label = "<add.inp1.copy.outputs[0]: <I64*32>>: 0"]\n'
 283             '    "16" [label = "<add.inp3.setvl.outputs[0]: <VL_MAXVL>>: 0"]\n'
 284             '    "17" [label = "<add.outputs[0]: <I64*32>>: 0"]\n'
 285             '    "18" [label = "<ca.outputs[0]: <CA>>: 0\\n'
 286             '<add.outputs[1]: <CA>>: 0"]\n'
 287             '    "19" [label = "<add.out0.setvl.outputs[0]: <VL_MAXVL>>: 0"]\n'
 288             '    "20" [label = "<add.out0.copy.outputs[0]: <I64*32>>: 0"]\n'
 289             '    "21" [label = "<st.inp0.setvl.outputs[0]: <VL_MAXVL>>: 0"]\n'
 290             '    "22" [label = "<st.inp0.copy.outputs[0]: <I64*32>>: 0"]\n'
 291             '    "23" [label = "<st.inp1.copy.outputs[0]: <I64>>: 0"]\n'
 292             '    "24" [label = "<st.inp2.setvl.outputs[0]: <VL_MAXVL>>: 0"]\n'
 293             '    "1" -- "3" [label = "IGEdge(is_copy_related=True)"]\n'
 294             '    "1" -- "5" [label = "IGEdge(is_copy_related=False)"]\n'
 295             '    "1" -- "7" [label = "IGEdge(is_copy_related=False)"]\n'
 296             '    "1" -- "9" [label = "IGEdge(is_copy_related=False)"]\n'
 297             '    "1" -- "11" [label = "IGEdge(is_copy_related=False)"]\n'
 298             '    "1" -- "13" [label = "IGEdge(is_copy_related=False)"]\n'
 299             '    "1" -- "15" [label = "IGEdge(is_copy_related=False)"]\n'
 300             '    "1" -- "17" [label = "IGEdge(is_copy_related=False)"]\n'
 301             '    "1" -- "20" [label = "IGEdge(is_copy_related=False)"]\n'
 302             '    "1" -- "22" [label = "IGEdge(is_copy_related=False)"]\n'
 303             '    "3" -- "5" [label = "IGEdge(is_copy_related=False)"]\n'
 304             '    "7" -- "9" [label = "IGEdge(is_copy_related=False)"]\n'
 305             '    "7" -- "11" [label = "IGEdge(is_copy_related=False)"]\n'
 306             '    "11" -- "13" [label = "IGEdge(is_copy_related=False)"]\n'
 307             '    "13" -- "15" [label = "IGEdge(is_copy_related=False)"]\n'
 308             '    "13" -- "17" [label = "IGEdge(is_copy_related=False)"]\n'
 309             '    "15" -- "17" [label = "IGEdge(is_copy_related=False)"]\n'
 310             '    "22" -- "23" [label = "IGEdge(is_copy_related=False)"]\n'
 311             '}'
 312         })
 313
 314     def test_register_allocate_spread(self):
 315         fn = Fn()
 316         maxvl = 32
 317         vl = fn.append_new_op(OpKind.SetVLI, immediates=[maxvl],
 318                               name="vl", maxvl=maxvl).outputs[0]
 319         li = fn.append_new_op(OpKind.SvLI, input_vals=[vl], immediates=[0],
 320                               name="li", maxvl=maxvl).outputs[0]
 321         spread = fn.append_new_op(OpKind.Spread, input_vals=[li, vl],
 322                                   name="spread", maxvl=maxvl).outputs
 323         _concat = fn.append_new_op(
 324             OpKind.Concat, input_vals=[*spread[::-1], vl],
 325             name="concat", maxvl=maxvl)
 326         reg_assignments = allocate_registers(fn, debug_out=sys.stdout)
 327
 328         self.assertEqual(
 329             repr(reg_assignments),
 330             "{<concat.out0.copy.outputs[0]: <I64*32>>: "
 331             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 332             "<concat.out0.setvl.outputs[0]: <VL_MAXVL>>: "
 333             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 334             "<concat.outputs[0]: <I64*32>>: "
 335             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 336             "<concat.inp0.copy.outputs[0]: <I64>>: "
 337             "Loc(kind=LocKind.GPR, start=14, reg_len=1), "
 338             "<concat.inp1.copy.outputs[0]: <I64>>: "
 339             "Loc(kind=LocKind.GPR, start=15, reg_len=1), "
 340             "<concat.inp2.copy.outputs[0]: <I64>>: "
 341             "Loc(kind=LocKind.GPR, start=16, reg_len=1), "
 342             "<concat.inp3.copy.outputs[0]: <I64>>: "
 343             "Loc(kind=LocKind.GPR, start=17, reg_len=1), "
 344             "<concat.inp4.copy.outputs[0]: <I64>>: "
 345             "Loc(kind=LocKind.GPR, start=18, reg_len=1), "
 346             "<concat.inp5.copy.outputs[0]: <I64>>: "
 347             "Loc(kind=LocKind.GPR, start=19, reg_len=1), "
 348             "<concat.inp6.copy.outputs[0]: <I64>>: "
 349             "Loc(kind=LocKind.GPR, start=20, reg_len=1), "
 350             "<concat.inp7.copy.outputs[0]: <I64>>: "
 351             "Loc(kind=LocKind.GPR, start=21, reg_len=1), "
 352             "<concat.inp8.copy.outputs[0]: <I64>>: "
 353             "Loc(kind=LocKind.GPR, start=22, reg_len=1), "
 354             "<concat.inp9.copy.outputs[0]: <I64>>: "
 355             "Loc(kind=LocKind.GPR, start=23, reg_len=1), "
 356             "<concat.inp10.copy.outputs[0]: <I64>>: "
 357             "Loc(kind=LocKind.GPR, start=24, reg_len=1), "
 358             "<concat.inp11.copy.outputs[0]: <I64>>: "
 359             "Loc(kind=LocKind.GPR, start=25, reg_len=1), "
 360             "<concat.inp12.copy.outputs[0]: <I64>>: "
 361             "Loc(kind=LocKind.GPR, start=26, reg_len=1), "
 362             "<concat.inp13.copy.outputs[0]: <I64>>: "
 363             "Loc(kind=LocKind.GPR, start=27, reg_len=1), "
 364             "<concat.inp14.copy.outputs[0]: <I64>>: "
 365             "Loc(kind=LocKind.GPR, start=28, reg_len=1), "
 366             "<concat.inp15.copy.outputs[0]: <I64>>: "
 367             "Loc(kind=LocKind.GPR, start=29, reg_len=1), "
 368             "<concat.inp16.copy.outputs[0]: <I64>>: "
 369             "Loc(kind=LocKind.GPR, start=30, reg_len=1), "
 370             "<concat.inp17.copy.outputs[0]: <I64>>: "
 371             "Loc(kind=LocKind.GPR, start=31, reg_len=1), "
 372             "<concat.inp18.copy.outputs[0]: <I64>>: "
 373             "Loc(kind=LocKind.GPR, start=32, reg_len=1), "
 374             "<concat.inp19.copy.outputs[0]: <I64>>: "
 375             "Loc(kind=LocKind.GPR, start=33, reg_len=1), "
 376             "<concat.inp20.copy.outputs[0]: <I64>>: "
 377             "Loc(kind=LocKind.GPR, start=34, reg_len=1), "
 378             "<concat.inp21.copy.outputs[0]: <I64>>: "
 379             "Loc(kind=LocKind.GPR, start=35, reg_len=1), "
 380             "<concat.inp22.copy.outputs[0]: <I64>>: "
 381             "Loc(kind=LocKind.GPR, start=36, reg_len=1), "
 382             "<concat.inp23.copy.outputs[0]: <I64>>: "
 383             "Loc(kind=LocKind.GPR, start=37, reg_len=1), "
 384             "<concat.inp24.copy.outputs[0]: <I64>>: "
 385             "Loc(kind=LocKind.GPR, start=38, reg_len=1), "
 386             "<concat.inp25.copy.outputs[0]: <I64>>: "
 387             "Loc(kind=LocKind.GPR, start=39, reg_len=1), "
 388             "<concat.inp26.copy.outputs[0]: <I64>>: "
 389             "Loc(kind=LocKind.GPR, start=40, reg_len=1), "
 390             "<concat.inp27.copy.outputs[0]: <I64>>: "
 391             "Loc(kind=LocKind.GPR, start=41, reg_len=1), "
 392             "<concat.inp28.copy.outputs[0]: <I64>>: "
 393             "Loc(kind=LocKind.GPR, start=42, reg_len=1), "
 394             "<concat.inp29.copy.outputs[0]: <I64>>: "
 395             "Loc(kind=LocKind.GPR, start=43, reg_len=1), "
 396             "<concat.inp30.copy.outputs[0]: <I64>>: "
 397             "Loc(kind=LocKind.GPR, start=44, reg_len=1), "
 398             "<concat.inp31.copy.outputs[0]: <I64>>: "
 399             "Loc(kind=LocKind.GPR, start=45, reg_len=1), "
 400             "<concat.inp32.setvl.outputs[0]: <VL_MAXVL>>: "
 401             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 402             "<spread.out31.copy.outputs[0]: <I64>>: "
 403             "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
 404             "<spread.out30.copy.outputs[0]: <I64>>: "
 405             "Loc(kind=LocKind.GPR, start=4, reg_len=1), "
 406             "<spread.out29.copy.outputs[0]: <I64>>: "
 407             "Loc(kind=LocKind.GPR, start=5, reg_len=1), "
 408             "<spread.outputs[0]: <I64>>: "
 409             "Loc(kind=LocKind.GPR, start=14, reg_len=1), "
 410             "<spread.outputs[1]: <I64>>: "
 411             "Loc(kind=LocKind.GPR, start=15, reg_len=1), "
 412             "<spread.outputs[2]: <I64>>: "
 413             "Loc(kind=LocKind.GPR, start=16, reg_len=1), "
 414             "<spread.outputs[3]: <I64>>: "
 415             "Loc(kind=LocKind.GPR, start=17, reg_len=1), "
 416             "<spread.outputs[4]: <I64>>: "
 417             "Loc(kind=LocKind.GPR, start=18, reg_len=1), "
 418             "<spread.outputs[5]: <I64>>: "
 419             "Loc(kind=LocKind.GPR, start=19, reg_len=1), "
 420             "<spread.outputs[6]: <I64>>: "
 421             "Loc(kind=LocKind.GPR, start=20, reg_len=1), "
 422             "<spread.outputs[7]: <I64>>: "
 423             "Loc(kind=LocKind.GPR, start=21, reg_len=1), "
 424             "<spread.outputs[8]: <I64>>: "
 425             "Loc(kind=LocKind.GPR, start=22, reg_len=1), "
 426             "<spread.outputs[9]: <I64>>: "
 427             "Loc(kind=LocKind.GPR, start=23, reg_len=1), "
 428             "<spread.outputs[10]: <I64>>: "
 429             "Loc(kind=LocKind.GPR, start=24, reg_len=1), "
 430             "<spread.outputs[11]: <I64>>: "
 431             "Loc(kind=LocKind.GPR, start=25, reg_len=1), "
 432             "<spread.outputs[12]: <I64>>: "
 433             "Loc(kind=LocKind.GPR, start=26, reg_len=1), "
 434             "<spread.outputs[13]: <I64>>: "
 435             "Loc(kind=LocKind.GPR, start=27, reg_len=1), "
 436             "<spread.outputs[14]: <I64>>: "
 437             "Loc(kind=LocKind.GPR, start=28, reg_len=1), "
 438             "<spread.outputs[15]: <I64>>: "
 439             "Loc(kind=LocKind.GPR, start=29, reg_len=1), "
 440             "<spread.outputs[16]: <I64>>: "
 441             "Loc(kind=LocKind.GPR, start=30, reg_len=1), "
 442             "<spread.outputs[17]: <I64>>: "
 443             "Loc(kind=LocKind.GPR, start=31, reg_len=1), "
 444             "<spread.outputs[18]: <I64>>: "
 445             "Loc(kind=LocKind.GPR, start=32, reg_len=1), "
 446             "<spread.outputs[19]: <I64>>: "
 447             "Loc(kind=LocKind.GPR, start=33, reg_len=1), "
 448             "<spread.outputs[20]: <I64>>: "
 449             "Loc(kind=LocKind.GPR, start=34, reg_len=1), "
 450             "<spread.outputs[21]: <I64>>: "
 451             "Loc(kind=LocKind.GPR, start=35, reg_len=1), "
 452             "<spread.outputs[22]: <I64>>: "
 453             "Loc(kind=LocKind.GPR, start=36, reg_len=1), "
 454             "<spread.outputs[23]: <I64>>: "
 455             "Loc(kind=LocKind.GPR, start=37, reg_len=1), "
 456             "<spread.outputs[24]: <I64>>: "
 457             "Loc(kind=LocKind.GPR, start=38, reg_len=1), "
 458             "<spread.outputs[25]: <I64>>: "
 459             "Loc(kind=LocKind.GPR, start=39, reg_len=1), "
 460             "<spread.outputs[26]: <I64>>: "
 461             "Loc(kind=LocKind.GPR, start=40, reg_len=1), "
 462             "<spread.outputs[27]: <I64>>: "
 463             "Loc(kind=LocKind.GPR, start=41, reg_len=1), "
 464             "<spread.outputs[28]: <I64>>: "
 465             "Loc(kind=LocKind.GPR, start=42, reg_len=1), "
 466             "<spread.outputs[29]: <I64>>: "
 467             "Loc(kind=LocKind.GPR, start=43, reg_len=1), "
 468             "<spread.outputs[30]: <I64>>: "
 469             "Loc(kind=LocKind.GPR, start=44, reg_len=1), "
 470             "<spread.outputs[31]: <I64>>: "
 471             "Loc(kind=LocKind.GPR, start=45, reg_len=1), "
 472             "<spread.out28.copy.outputs[0]: <I64>>: "
 473             "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
 474             "<spread.out27.copy.outputs[0]: <I64>>: "
 475             "Loc(kind=LocKind.GPR, start=7, reg_len=1), "
 476             "<spread.out26.copy.outputs[0]: <I64>>: "
 477             "Loc(kind=LocKind.GPR, start=8, reg_len=1), "
 478             "<spread.out25.copy.outputs[0]: <I64>>: "
 479             "Loc(kind=LocKind.GPR, start=9, reg_len=1), "
 480             "<spread.out24.copy.outputs[0]: <I64>>: "
 481             "Loc(kind=LocKind.GPR, start=10, reg_len=1), "
 482             "<spread.out23.copy.outputs[0]: <I64>>: "
 483             "Loc(kind=LocKind.GPR, start=11, reg_len=1), "
 484             "<spread.out22.copy.outputs[0]: <I64>>: "
 485             "Loc(kind=LocKind.GPR, start=12, reg_len=1), "
 486             "<spread.out21.copy.outputs[0]: <I64>>: "
 487             "Loc(kind=LocKind.GPR, start=46, reg_len=1), "
 488             "<spread.out20.copy.outputs[0]: <I64>>: "
 489             "Loc(kind=LocKind.GPR, start=47, reg_len=1), "
 490             "<spread.out19.copy.outputs[0]: <I64>>: "
 491             "Loc(kind=LocKind.GPR, start=48, reg_len=1), "
 492             "<spread.out18.copy.outputs[0]: <I64>>: "
 493             "Loc(kind=LocKind.GPR, start=49, reg_len=1), "
 494             "<spread.out17.copy.outputs[0]: <I64>>: "
 495             "Loc(kind=LocKind.GPR, start=50, reg_len=1), "
 496             "<spread.out16.copy.outputs[0]: <I64>>: "
 497             "Loc(kind=LocKind.GPR, start=51, reg_len=1), "
 498             "<spread.out15.copy.outputs[0]: <I64>>: "
 499             "Loc(kind=LocKind.GPR, start=52, reg_len=1), "
 500             "<spread.out14.copy.outputs[0]: <I64>>: "
 501             "Loc(kind=LocKind.GPR, start=53, reg_len=1), "
 502             "<spread.out13.copy.outputs[0]: <I64>>: "
 503             "Loc(kind=LocKind.GPR, start=54, reg_len=1), "
 504             "<spread.out12.copy.outputs[0]: <I64>>: "
 505             "Loc(kind=LocKind.GPR, start=55, reg_len=1), "
 506             "<spread.out11.copy.outputs[0]: <I64>>: "
 507             "Loc(kind=LocKind.GPR, start=56, reg_len=1), "
 508             "<spread.out10.copy.outputs[0]: <I64>>: "
 509             "Loc(kind=LocKind.GPR, start=57, reg_len=1), "
 510             "<spread.out9.copy.outputs[0]: <I64>>: "
 511             "Loc(kind=LocKind.GPR, start=58, reg_len=1), "
 512             "<spread.out8.copy.outputs[0]: <I64>>: "
 513             "Loc(kind=LocKind.GPR, start=59, reg_len=1), "
 514             "<spread.out7.copy.outputs[0]: <I64>>: "
 515             "Loc(kind=LocKind.GPR, start=60, reg_len=1), "
 516             "<spread.out6.copy.outputs[0]: <I64>>: "
 517             "Loc(kind=LocKind.GPR, start=61, reg_len=1), "
 518             "<spread.out5.copy.outputs[0]: <I64>>: "
 519             "Loc(kind=LocKind.GPR, start=62, reg_len=1), "
 520             "<spread.out4.copy.outputs[0]: <I64>>: "
 521             "Loc(kind=LocKind.GPR, start=63, reg_len=1), "
 522             "<spread.out3.copy.outputs[0]: <I64>>: "
 523             "Loc(kind=LocKind.GPR, start=64, reg_len=1), "
 524             "<spread.out2.copy.outputs[0]: <I64>>: "
 525             "Loc(kind=LocKind.GPR, start=65, reg_len=1), "
 526             "<spread.out1.copy.outputs[0]: <I64>>: "
 527             "Loc(kind=LocKind.GPR, start=66, reg_len=1), "
 528             "<spread.out0.copy.outputs[0]: <I64>>: "
 529             "Loc(kind=LocKind.GPR, start=67, reg_len=1), "
 530             "<spread.inp1.setvl.outputs[0]: <VL_MAXVL>>: "
 531             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 532             "<spread.inp0.copy.outputs[0]: <I64*32>>: "
 533             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 534             "<spread.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
 535             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 536             "<li.out0.copy.outputs[0]: <I64*32>>: "
 537             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 538             "<li.out0.setvl.outputs[0]: <VL_MAXVL>>: "
 539             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 540             "<li.outputs[0]: <I64*32>>: "
 541             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 542             "<li.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
 543             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 544             "<vl.outputs[0]: <VL_MAXVL>>: "
 545             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1)}"
 546         )
 547         state = GenAsmState(reg_assignments)
 548         fn.gen_asm(state)
 549         self.assertEqual(state.output, [
 550             'setvl 0, 0, 32, 0, 1, 1',
 551             'setvl 0, 0, 32, 0, 1, 1',
 552             'sv.addi *14, 0, 0',
 553             'setvl 0, 0, 32, 0, 1, 1',
 554             'setvl 0, 0, 32, 0, 1, 1',
 555             'setvl 0, 0, 32, 0, 1, 1',
 556             'or 67, 14, 14',
 557             'or 66, 15, 15',
 558             'or 65, 16, 16',
 559             'or 64, 17, 17',
 560             'or 63, 18, 18',
 561             'or 62, 19, 19',
 562             'or 61, 20, 20',
 563             'or 60, 21, 21',
 564             'or 59, 22, 22',
 565             'or 58, 23, 23',
 566             'or 57, 24, 24',
 567             'or 56, 25, 25',
 568             'or 55, 26, 26',
 569             'or 54, 27, 27',
 570             'or 53, 28, 28',
 571             'or 52, 29, 29',
 572             'or 51, 30, 30',
 573             'or 50, 31, 31',
 574             'or 49, 32, 32',
 575             'or 48, 33, 33',
 576             'or 47, 34, 34',
 577             'or 46, 35, 35',
 578             'or 12, 36, 36',
 579             'or 11, 37, 37',
 580             'or 10, 38, 38',
 581             'or 9, 39, 39',
 582             'or 8, 40, 40',
 583             'or 7, 41, 41',
 584             'or 6, 42, 42',
 585             'or 5, 43, 43',
 586             'or 4, 44, 44',
 587             'or 3, 45, 45',
 588             'or 14, 3, 3',
 589             'or 15, 4, 4',
 590             'or 16, 5, 5',
 591             'or 17, 6, 6',
 592             'or 18, 7, 7',
 593             'or 19, 8, 8',
 594             'or 20, 9, 9',
 595             'or 21, 10, 10',
 596             'or 22, 11, 11',
 597             'or 23, 12, 12',
 598             'or 24, 46, 46',
 599             'or 25, 47, 47',
 600             'or 26, 48, 48',
 601             'or 27, 49, 49',
 602             'or 28, 50, 50',
 603             'or 29, 51, 51',
 604             'or 30, 52, 52',
 605             'or 31, 53, 53',
 606             'or 32, 54, 54',
 607             'or 33, 55, 55',
 608             'or 34, 56, 56',
 609             'or 35, 57, 57',
 610             'or 36, 58, 58',
 611             'or 37, 59, 59',
 612             'or 38, 60, 60',
 613             'or 39, 61, 61',
 614             'or 40, 62, 62',
 615             'or 41, 63, 63',
 616             'or 42, 64, 64',
 617             'or 43, 65, 65',
 618             'or 44, 66, 66',
 619             'or 45, 67, 67',
 620             'setvl 0, 0, 32, 0, 1, 1',
 621             'setvl 0, 0, 32, 0, 1, 1'])
 622
 623
 624 if __name__ == "__main__":
 625     _ = unittest.main()