src/bigint_presentation_code/_tests/test_register_allocator.py

   1 import sys
   2 import unittest
   3 import shutil
   4
   5 from bigint_presentation_code.compiler_ir import (Fn, GenAsmState, OpKind,
   6                                                   SSAVal)
   7 from bigint_presentation_code.register_allocator import allocate_registers
   8 from nmutil.get_test_path import get_test_path
   9
  10
  11 def dump_graphs(test_case, graphs):
  12     # type: (unittest.TestCase, dict[str, str]) -> None
  13     base_path = get_test_path(test_case, "dumped_graphs")
  14     shutil.rmtree(base_path, ignore_errors=True)
  15     base_path.mkdir(parents=True, exist_ok=True)
  16     for name, dot in graphs.items():
  17         path = base_path / name
  18         dot_path = path.with_suffix(".dot")
  19         dot_path.write_text(dot)
  20
  21
  22 class TestRegisterAllocator(unittest.TestCase):
  23     maxDiff = None
  24
  25     def make_add_fn(self):
  26         # type: () -> tuple[Fn, SSAVal]
  27         fn = Fn()
  28         op0 = fn.append_new_op(OpKind.FuncArgR3, name="arg")
  29         arg = op0.outputs[0]
  30         MAXVL = 32
  31         op1 = fn.append_new_op(OpKind.SetVLI, immediates=[MAXVL], name="vl")
  32         vl = op1.outputs[0]
  33         op2 = fn.append_new_op(
  34             OpKind.SvLd, input_vals=[arg, vl], immediates=[0], maxvl=MAXVL,
  35             name="ld")
  36         a = op2.outputs[0]
  37         op3 = fn.append_new_op(OpKind.SvLI, input_vals=[vl], immediates=[0],
  38                                maxvl=MAXVL, name="li")
  39         b = op3.outputs[0]
  40         op4 = fn.append_new_op(OpKind.SetCA, name="ca")
  41         ca = op4.outputs[0]
  42         op5 = fn.append_new_op(
  43             OpKind.SvAddE, input_vals=[a, b, ca, vl], maxvl=MAXVL, name="add")
  44         s = op5.outputs[0]
  45         _ = fn.append_new_op(OpKind.SvStd, input_vals=[s, arg, vl],
  46                              immediates=[0], maxvl=MAXVL, name="st")
  47         return fn, arg
  48
  49     def test_register_allocate(self):
  50         fn, _arg = self.make_add_fn()
  51         reg_assignments = allocate_registers(fn, debug_out=sys.stdout)
  52
  53         self.assertEqual(
  54             repr(reg_assignments),
  55             "{<add.outputs[0]: <I64*32>>: "
  56             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
  57             "<add.inp1.copy.outputs[0]: <I64*32>>: "
  58             "Loc(kind=LocKind.GPR, start=46, reg_len=32), "
  59             "<add.inp0.copy.outputs[0]: <I64*32>>: "
  60             "Loc(kind=LocKind.GPR, start=78, reg_len=32), "
  61             "<st.inp2.setvl.outputs[0]: <VL_MAXVL>>: "
  62             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  63             "<st.inp1.copy.outputs[0]: <I64>>: "
  64             "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
  65             "<st.inp0.copy.outputs[0]: <I64*32>>: "
  66             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
  67             "<st.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
  68             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  69             "<add.out0.copy.outputs[0]: <I64*32>>: "
  70             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
  71             "<add.out0.setvl.outputs[0]: <VL_MAXVL>>: "
  72             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  73             "<ca.outputs[0]: <CA>>: "
  74             "Loc(kind=LocKind.CA, start=0, reg_len=1), "
  75             "<add.outputs[1]: <CA>>: "
  76             "Loc(kind=LocKind.CA, start=0, reg_len=1), "
  77             "<add.inp3.setvl.outputs[0]: <VL_MAXVL>>: "
  78             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  79             "<add.inp1.setvl.outputs[0]: <VL_MAXVL>>: "
  80             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  81             "<add.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
  82             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  83             "<li.out0.copy.outputs[0]: <I64*32>>: "
  84             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
  85             "<li.out0.setvl.outputs[0]: <VL_MAXVL>>: "
  86             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  87             "<li.outputs[0]: <I64*32>>: "
  88             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
  89             "<li.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
  90             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  91             "<ld.out0.copy.outputs[0]: <I64*32>>: "
  92             "Loc(kind=LocKind.GPR, start=46, reg_len=32), "
  93             "<ld.out0.setvl.outputs[0]: <VL_MAXVL>>: "
  94             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  95             "<ld.outputs[0]: <I64*32>>: "
  96             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
  97             "<ld.inp1.setvl.outputs[0]: <VL_MAXVL>>: "
  98             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  99             "<ld.inp0.copy.outputs[0]: <I64>>: "
 100             "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
 101             "<vl.outputs[0]: <VL_MAXVL>>: "
 102             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 103             "<arg.out0.copy.outputs[0]: <I64>>: "
 104             "Loc(kind=LocKind.GPR, start=4, reg_len=1), "
 105             "<arg.outputs[0]: <I64>>: "
 106             "Loc(kind=LocKind.GPR, start=3, reg_len=1)}"
 107         )
 108
 109     def test_gen_asm(self):
 110         fn, _arg = self.make_add_fn()
 111         reg_assignments = allocate_registers(fn)
 112
 113         self.assertEqual(
 114             repr(reg_assignments),
 115             "{"
 116             "<add.outputs[0]: <I64*32>>: "
 117             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 118             "<add.out0.copy.outputs[0]: <I64*32>>: "
 119             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 120             "<st.inp0.copy.outputs[0]: <I64*32>>: "
 121             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 122             "<add.inp1.copy.outputs[0]: <I64*32>>: "
 123             "Loc(kind=LocKind.GPR, start=46, reg_len=32), "
 124             "<li.outputs[0]: <I64*32>>: "
 125             "Loc(kind=LocKind.GPR, start=46, reg_len=32), "
 126             "<li.out0.copy.outputs[0]: <I64*32>>: "
 127             "Loc(kind=LocKind.GPR, start=46, reg_len=32), "
 128             "<add.inp0.copy.outputs[0]: <I64*32>>: "
 129             "Loc(kind=LocKind.GPR, start=78, reg_len=32), "
 130             "<ld.out0.copy.outputs[0]: <I64*32>>: "
 131             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 132             "<ld.outputs[0]: <I64*32>>: "
 133             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 134             "<ld.inp0.copy.outputs[0]: <I64>>: "
 135             "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
 136             "<arg.outputs[0]: <I64>>: "
 137             "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
 138             "<st.inp1.copy.outputs[0]: <I64>>: "
 139             "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
 140             "<arg.out0.copy.outputs[0]: <I64>>: "
 141             "Loc(kind=LocKind.GPR, start=4, reg_len=1), "
 142             "<st.inp2.setvl.outputs[0]: <VL_MAXVL>>: "
 143             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 144             "<st.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
 145             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 146             "<add.out0.setvl.outputs[0]: <VL_MAXVL>>: "
 147             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 148             "<ca.outputs[0]: <CA>>: "
 149             "Loc(kind=LocKind.CA, start=0, reg_len=1), "
 150             "<add.outputs[1]: <CA>>: "
 151             "Loc(kind=LocKind.CA, start=0, reg_len=1), "
 152             "<add.inp3.setvl.outputs[0]: <VL_MAXVL>>: "
 153             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 154             "<add.inp1.setvl.outputs[0]: <VL_MAXVL>>: "
 155             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 156             "<add.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
 157             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 158             "<li.out0.setvl.outputs[0]: <VL_MAXVL>>: "
 159             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 160             "<li.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
 161             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 162             "<ld.out0.setvl.outputs[0]: <VL_MAXVL>>: "
 163             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 164             "<ld.inp1.setvl.outputs[0]: <VL_MAXVL>>: "
 165             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 166             "<vl.outputs[0]: <VL_MAXVL>>: "
 167             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1)"
 168             "}"
 169         )
 170         state = GenAsmState(reg_assignments)
 171         fn.gen_asm(state)
 172         self.assertEqual(state.output, [
 173             'or 4, 3, 3',
 174             'setvl 0, 0, 32, 0, 1, 1',
 175             'or 3, 4, 4',
 176             'setvl 0, 0, 32, 0, 1, 1',
 177             'sv.ld *14, 0(3)',
 178             'setvl 0, 0, 32, 0, 1, 1',
 179             'setvl 0, 0, 32, 0, 1, 1',
 180             'sv.addi *46, 0, 0',
 181             'setvl 0, 0, 32, 0, 1, 1',
 182             'subfc 0, 0, 0',
 183             'setvl 0, 0, 32, 0, 1, 1',
 184             'sv.or *78, *14, *14',
 185             'setvl 0, 0, 32, 0, 1, 1',
 186             'setvl 0, 0, 32, 0, 1, 1',
 187             'sv.adde *14, *78, *46',
 188             'setvl 0, 0, 32, 0, 1, 1',
 189             'setvl 0, 0, 32, 0, 1, 1',
 190             'or 3, 4, 4',
 191             'setvl 0, 0, 32, 0, 1, 1',
 192             'sv.std *14, 0(3)',
 193         ])
 194
 195     def test_register_allocate_graphs(self):
 196         fn, _arg = self.make_add_fn()
 197         graphs = {}  # type: dict[str, str]
 198
 199         def dump_graph(name, dot):
 200             # type: (str, str) -> None
 201             self.assertNotIn(name, graphs, "duplicate graph name")
 202             graphs[name] = dot
 203         allocated = allocate_registers(fn, dump_graph=dump_graph,
 204                                        debug_out=sys.stdout)
 205         dump_graphs(self, graphs)
 206         self.assertEqual(
 207             repr(allocated),
 208             "{"
 209             "<add.outputs[0]: <I64*32>>: "
 210             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 211             "<add.out0.copy.outputs[0]: <I64*32>>: "
 212             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 213             "<st.inp0.copy.outputs[0]: <I64*32>>: "
 214             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 215             "<add.inp1.copy.outputs[0]: <I64*32>>: "
 216             "Loc(kind=LocKind.GPR, start=46, reg_len=32), "
 217             "<li.outputs[0]: <I64*32>>: "
 218             "Loc(kind=LocKind.GPR, start=46, reg_len=32), "
 219             "<li.out0.copy.outputs[0]: <I64*32>>: "
 220             "Loc(kind=LocKind.GPR, start=46, reg_len=32), "
 221             "<add.inp0.copy.outputs[0]: <I64*32>>: "
 222             "Loc(kind=LocKind.GPR, start=78, reg_len=32), "
 223             "<ld.out0.copy.outputs[0]: <I64*32>>: "
 224             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 225             "<ld.outputs[0]: <I64*32>>: "
 226             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 227             "<ld.inp0.copy.outputs[0]: <I64>>: "
 228             "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
 229             "<arg.outputs[0]: <I64>>: "
 230             "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
 231             "<st.inp1.copy.outputs[0]: <I64>>: "
 232             "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
 233             "<arg.out0.copy.outputs[0]: <I64>>: "
 234             "Loc(kind=LocKind.GPR, start=4, reg_len=1), "
 235             "<st.inp2.setvl.outputs[0]: <VL_MAXVL>>: "
 236             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 237             "<st.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
 238             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 239             "<add.out0.setvl.outputs[0]: <VL_MAXVL>>: "
 240             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 241             "<ca.outputs[0]: <CA>>: "
 242             "Loc(kind=LocKind.CA, start=0, reg_len=1), "
 243             "<add.outputs[1]: <CA>>: "
 244             "Loc(kind=LocKind.CA, start=0, reg_len=1), "
 245             "<add.inp3.setvl.outputs[0]: <VL_MAXVL>>: "
 246             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 247             "<add.inp1.setvl.outputs[0]: <VL_MAXVL>>: "
 248             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 249             "<add.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
 250             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 251             "<li.out0.setvl.outputs[0]: <VL_MAXVL>>: "
 252             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 253             "<li.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
 254             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 255             "<ld.out0.setvl.outputs[0]: <VL_MAXVL>>: "
 256             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 257             "<ld.inp1.setvl.outputs[0]: <VL_MAXVL>>: "
 258             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 259             "<vl.outputs[0]: <VL_MAXVL>>: "
 260             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1)"
 261             "}"
 262         )
 263         # FIXME: is_copy_related is not correct, it's missing a bunch of
 264         # edges (which aren't interference edges)
 265         self.assertEqual(graphs, {
 266             'initial': r"""graph {
 267     graph [pack = true]
 268     "0" [label = "<arg.outputs[0]: <I64>>: 0"]
 269     "1" [label = "<arg.out0.copy.outputs[0]: <I64>>: 0"]
 270     "2" [label = "<vl.outputs[0]: <VL_MAXVL>>: 0"]
 271     "3" [label = "<ld.inp0.copy.outputs[0]: <I64>>: 0"]
 272     "4" [label = "<ld.inp1.setvl.outputs[0]: <VL_MAXVL>>: 0"]
 273     "5" [label = "<ld.outputs[0]: <I64*32>>: 0"]
 274     "6" [label = "<ld.out0.setvl.outputs[0]: <VL_MAXVL>>: 0"]
 275     "7" [label = "<ld.out0.copy.outputs[0]: <I64*32>>: 0"]
 276     "8" [label = "<li.inp0.setvl.outputs[0]: <VL_MAXVL>>: 0"]
 277     "9" [label = "<li.outputs[0]: <I64*32>>: 0"]
 278     "10" [label = "<li.out0.setvl.outputs[0]: <VL_MAXVL>>: 0"]
 279     "11" [label = "<li.out0.copy.outputs[0]: <I64*32>>: 0"]
 280     "12" [label = "<add.inp0.setvl.outputs[0]: <VL_MAXVL>>: 0"]
 281     "13" [label = "<add.inp0.copy.outputs[0]: <I64*32>>: 0"]
 282     "14" [label = "<add.inp1.setvl.outputs[0]: <VL_MAXVL>>: 0"]
 283     "15" [label = "<add.inp1.copy.outputs[0]: <I64*32>>: 0"]
 284     "16" [label = "<add.inp3.setvl.outputs[0]: <VL_MAXVL>>: 0"]
 285     "17" [label = "<add.outputs[0]: <I64*32>>: 0"]
 286     "18" [label = "<ca.outputs[0]: <CA>>: 0\n<add.outputs[1]: <CA>>: 0"]
 287     "19" [label = "<add.out0.setvl.outputs[0]: <VL_MAXVL>>: 0"]
 288     "20" [label = "<add.out0.copy.outputs[0]: <I64*32>>: 0"]
 289     "21" [label = "<st.inp0.setvl.outputs[0]: <VL_MAXVL>>: 0"]
 290     "22" [label = "<st.inp0.copy.outputs[0]: <I64*32>>: 0"]
 291     "23" [label = "<st.inp1.copy.outputs[0]: <I64>>: 0"]
 292     "24" [label = "<st.inp2.setvl.outputs[0]: <VL_MAXVL>>: 0"]
 293     "0" -- "1" [label = "copy related", color = "blue", style = "dashed", decorate = true]
 294     "0" -- "3" [label = "copy related", color = "blue", style = "dashed", decorate = true]
 295     "0" -- "23" [label = "copy related", color = "blue", style = "dashed", decorate = true]
 296     "1" -- "3" [label = "interferes", color = "darkred", style = "bold", decorate = true]
 297     "1" -- "3" [label = "copy related", color = "blue", style = "dashed", decorate = true]
 298     "1" -- "5" [label = "interferes", color = "darkred", style = "bold", decorate = true]
 299     "1" -- "7" [label = "interferes", color = "darkred", style = "bold", decorate = true]
 300     "1" -- "9" [label = "interferes", color = "darkred", style = "bold", decorate = true]
 301     "1" -- "11" [label = "interferes", color = "darkred", style = "bold", decorate = true]
 302     "1" -- "13" [label = "interferes", color = "darkred", style = "bold", decorate = true]
 303     "1" -- "15" [label = "interferes", color = "darkred", style = "bold", decorate = true]
 304     "1" -- "17" [label = "interferes", color = "darkred", style = "bold", decorate = true]
 305     "1" -- "20" [label = "interferes", color = "darkred", style = "bold", decorate = true]
 306     "1" -- "22" [label = "interferes", color = "darkred", style = "bold", decorate = true]
 307     "1" -- "23" [label = "copy related", color = "blue", style = "dashed", decorate = true]
 308     "3" -- "5" [label = "interferes", color = "darkred", style = "bold", decorate = true]
 309     "3" -- "23" [label = "copy related", color = "blue", style = "dashed", decorate = true]
 310     "5" -- "7" [label = "copy related", color = "blue", style = "dashed", decorate = true]
 311     "5" -- "13" [label = "copy related", color = "blue", style = "dashed", decorate = true]
 312     "7" -- "9" [label = "interferes", color = "darkred", style = "bold", decorate = true]
 313     "7" -- "11" [label = "interferes", color = "darkred", style = "bold", decorate = true]
 314     "7" -- "13" [label = "copy related", color = "blue", style = "dashed", decorate = true]
 315     "9" -- "11" [label = "copy related", color = "blue", style = "dashed", decorate = true]
 316     "9" -- "15" [label = "copy related", color = "blue", style = "dashed", decorate = true]
 317     "11" -- "13" [label = "interferes", color = "darkred", style = "bold", decorate = true]
 318     "11" -- "15" [label = "copy related", color = "blue", style = "dashed", decorate = true]
 319     "13" -- "15" [label = "interferes", color = "darkred", style = "bold", decorate = true]
 320     "13" -- "17" [label = "interferes", color = "darkred", style = "bold", decorate = true]
 321     "15" -- "17" [label = "interferes", color = "darkred", style = "bold", decorate = true]
 322     "17" -- "20" [label = "copy related", color = "blue", style = "dashed", decorate = true]
 323     "17" -- "22" [label = "copy related", color = "blue", style = "dashed", decorate = true]
 324     "20" -- "22" [label = "copy related", color = "blue", style = "dashed", decorate = true]
 325     "22" -- "23" [label = "interferes", color = "darkred", style = "bold", decorate = true]
 326 }"""
 327         })
 328
 329     def test_register_allocate_spread(self):
 330         fn = Fn()
 331         maxvl = 32
 332         vl = fn.append_new_op(OpKind.SetVLI, immediates=[maxvl],
 333                               name="vl", maxvl=maxvl).outputs[0]
 334         li = fn.append_new_op(OpKind.SvLI, input_vals=[vl], immediates=[0],
 335                               name="li", maxvl=maxvl).outputs[0]
 336         spread = fn.append_new_op(OpKind.Spread, input_vals=[li, vl],
 337                                   name="spread", maxvl=maxvl).outputs
 338         _concat = fn.append_new_op(
 339             OpKind.Concat, input_vals=[*spread[::-1], vl],
 340             name="concat", maxvl=maxvl)
 341         reg_assignments = allocate_registers(fn, debug_out=sys.stdout)
 342
 343         self.assertEqual(
 344             repr(reg_assignments),
 345             "{<concat.out0.copy.outputs[0]: <I64*32>>: "
 346             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 347             "<concat.out0.setvl.outputs[0]: <VL_MAXVL>>: "
 348             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 349             "<concat.outputs[0]: <I64*32>>: "
 350             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 351             "<concat.inp0.copy.outputs[0]: <I64>>: "
 352             "Loc(kind=LocKind.GPR, start=14, reg_len=1), "
 353             "<concat.inp1.copy.outputs[0]: <I64>>: "
 354             "Loc(kind=LocKind.GPR, start=15, reg_len=1), "
 355             "<concat.inp2.copy.outputs[0]: <I64>>: "
 356             "Loc(kind=LocKind.GPR, start=16, reg_len=1), "
 357             "<concat.inp3.copy.outputs[0]: <I64>>: "
 358             "Loc(kind=LocKind.GPR, start=17, reg_len=1), "
 359             "<concat.inp4.copy.outputs[0]: <I64>>: "
 360             "Loc(kind=LocKind.GPR, start=18, reg_len=1), "
 361             "<concat.inp5.copy.outputs[0]: <I64>>: "
 362             "Loc(kind=LocKind.GPR, start=19, reg_len=1), "
 363             "<concat.inp6.copy.outputs[0]: <I64>>: "
 364             "Loc(kind=LocKind.GPR, start=20, reg_len=1), "
 365             "<concat.inp7.copy.outputs[0]: <I64>>: "
 366             "Loc(kind=LocKind.GPR, start=21, reg_len=1), "
 367             "<concat.inp8.copy.outputs[0]: <I64>>: "
 368             "Loc(kind=LocKind.GPR, start=22, reg_len=1), "
 369             "<concat.inp9.copy.outputs[0]: <I64>>: "
 370             "Loc(kind=LocKind.GPR, start=23, reg_len=1), "
 371             "<concat.inp10.copy.outputs[0]: <I64>>: "
 372             "Loc(kind=LocKind.GPR, start=24, reg_len=1), "
 373             "<concat.inp11.copy.outputs[0]: <I64>>: "
 374             "Loc(kind=LocKind.GPR, start=25, reg_len=1), "
 375             "<concat.inp12.copy.outputs[0]: <I64>>: "
 376             "Loc(kind=LocKind.GPR, start=26, reg_len=1), "
 377             "<concat.inp13.copy.outputs[0]: <I64>>: "
 378             "Loc(kind=LocKind.GPR, start=27, reg_len=1), "
 379             "<concat.inp14.copy.outputs[0]: <I64>>: "
 380             "Loc(kind=LocKind.GPR, start=28, reg_len=1), "
 381             "<concat.inp15.copy.outputs[0]: <I64>>: "
 382             "Loc(kind=LocKind.GPR, start=29, reg_len=1), "
 383             "<concat.inp16.copy.outputs[0]: <I64>>: "
 384             "Loc(kind=LocKind.GPR, start=30, reg_len=1), "
 385             "<concat.inp17.copy.outputs[0]: <I64>>: "
 386             "Loc(kind=LocKind.GPR, start=31, reg_len=1), "
 387             "<concat.inp18.copy.outputs[0]: <I64>>: "
 388             "Loc(kind=LocKind.GPR, start=32, reg_len=1), "
 389             "<concat.inp19.copy.outputs[0]: <I64>>: "
 390             "Loc(kind=LocKind.GPR, start=33, reg_len=1), "
 391             "<concat.inp20.copy.outputs[0]: <I64>>: "
 392             "Loc(kind=LocKind.GPR, start=34, reg_len=1), "
 393             "<concat.inp21.copy.outputs[0]: <I64>>: "
 394             "Loc(kind=LocKind.GPR, start=35, reg_len=1), "
 395             "<concat.inp22.copy.outputs[0]: <I64>>: "
 396             "Loc(kind=LocKind.GPR, start=36, reg_len=1), "
 397             "<concat.inp23.copy.outputs[0]: <I64>>: "
 398             "Loc(kind=LocKind.GPR, start=37, reg_len=1), "
 399             "<concat.inp24.copy.outputs[0]: <I64>>: "
 400             "Loc(kind=LocKind.GPR, start=38, reg_len=1), "
 401             "<concat.inp25.copy.outputs[0]: <I64>>: "
 402             "Loc(kind=LocKind.GPR, start=39, reg_len=1), "
 403             "<concat.inp26.copy.outputs[0]: <I64>>: "
 404             "Loc(kind=LocKind.GPR, start=40, reg_len=1), "
 405             "<concat.inp27.copy.outputs[0]: <I64>>: "
 406             "Loc(kind=LocKind.GPR, start=41, reg_len=1), "
 407             "<concat.inp28.copy.outputs[0]: <I64>>: "
 408             "Loc(kind=LocKind.GPR, start=42, reg_len=1), "
 409             "<concat.inp29.copy.outputs[0]: <I64>>: "
 410             "Loc(kind=LocKind.GPR, start=43, reg_len=1), "
 411             "<concat.inp30.copy.outputs[0]: <I64>>: "
 412             "Loc(kind=LocKind.GPR, start=44, reg_len=1), "
 413             "<concat.inp31.copy.outputs[0]: <I64>>: "
 414             "Loc(kind=LocKind.GPR, start=45, reg_len=1), "
 415             "<concat.inp32.setvl.outputs[0]: <VL_MAXVL>>: "
 416             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 417             "<spread.out31.copy.outputs[0]: <I64>>: "
 418             "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
 419             "<spread.out30.copy.outputs[0]: <I64>>: "
 420             "Loc(kind=LocKind.GPR, start=4, reg_len=1), "
 421             "<spread.out29.copy.outputs[0]: <I64>>: "
 422             "Loc(kind=LocKind.GPR, start=5, reg_len=1), "
 423             "<spread.outputs[0]: <I64>>: "
 424             "Loc(kind=LocKind.GPR, start=14, reg_len=1), "
 425             "<spread.outputs[1]: <I64>>: "
 426             "Loc(kind=LocKind.GPR, start=15, reg_len=1), "
 427             "<spread.outputs[2]: <I64>>: "
 428             "Loc(kind=LocKind.GPR, start=16, reg_len=1), "
 429             "<spread.outputs[3]: <I64>>: "
 430             "Loc(kind=LocKind.GPR, start=17, reg_len=1), "
 431             "<spread.outputs[4]: <I64>>: "
 432             "Loc(kind=LocKind.GPR, start=18, reg_len=1), "
 433             "<spread.outputs[5]: <I64>>: "
 434             "Loc(kind=LocKind.GPR, start=19, reg_len=1), "
 435             "<spread.outputs[6]: <I64>>: "
 436             "Loc(kind=LocKind.GPR, start=20, reg_len=1), "
 437             "<spread.outputs[7]: <I64>>: "
 438             "Loc(kind=LocKind.GPR, start=21, reg_len=1), "
 439             "<spread.outputs[8]: <I64>>: "
 440             "Loc(kind=LocKind.GPR, start=22, reg_len=1), "
 441             "<spread.outputs[9]: <I64>>: "
 442             "Loc(kind=LocKind.GPR, start=23, reg_len=1), "
 443             "<spread.outputs[10]: <I64>>: "
 444             "Loc(kind=LocKind.GPR, start=24, reg_len=1), "
 445             "<spread.outputs[11]: <I64>>: "
 446             "Loc(kind=LocKind.GPR, start=25, reg_len=1), "
 447             "<spread.outputs[12]: <I64>>: "
 448             "Loc(kind=LocKind.GPR, start=26, reg_len=1), "
 449             "<spread.outputs[13]: <I64>>: "
 450             "Loc(kind=LocKind.GPR, start=27, reg_len=1), "
 451             "<spread.outputs[14]: <I64>>: "
 452             "Loc(kind=LocKind.GPR, start=28, reg_len=1), "
 453             "<spread.outputs[15]: <I64>>: "
 454             "Loc(kind=LocKind.GPR, start=29, reg_len=1), "
 455             "<spread.outputs[16]: <I64>>: "
 456             "Loc(kind=LocKind.GPR, start=30, reg_len=1), "
 457             "<spread.outputs[17]: <I64>>: "
 458             "Loc(kind=LocKind.GPR, start=31, reg_len=1), "
 459             "<spread.outputs[18]: <I64>>: "
 460             "Loc(kind=LocKind.GPR, start=32, reg_len=1), "
 461             "<spread.outputs[19]: <I64>>: "
 462             "Loc(kind=LocKind.GPR, start=33, reg_len=1), "
 463             "<spread.outputs[20]: <I64>>: "
 464             "Loc(kind=LocKind.GPR, start=34, reg_len=1), "
 465             "<spread.outputs[21]: <I64>>: "
 466             "Loc(kind=LocKind.GPR, start=35, reg_len=1), "
 467             "<spread.outputs[22]: <I64>>: "
 468             "Loc(kind=LocKind.GPR, start=36, reg_len=1), "
 469             "<spread.outputs[23]: <I64>>: "
 470             "Loc(kind=LocKind.GPR, start=37, reg_len=1), "
 471             "<spread.outputs[24]: <I64>>: "
 472             "Loc(kind=LocKind.GPR, start=38, reg_len=1), "
 473             "<spread.outputs[25]: <I64>>: "
 474             "Loc(kind=LocKind.GPR, start=39, reg_len=1), "
 475             "<spread.outputs[26]: <I64>>: "
 476             "Loc(kind=LocKind.GPR, start=40, reg_len=1), "
 477             "<spread.outputs[27]: <I64>>: "
 478             "Loc(kind=LocKind.GPR, start=41, reg_len=1), "
 479             "<spread.outputs[28]: <I64>>: "
 480             "Loc(kind=LocKind.GPR, start=42, reg_len=1), "
 481             "<spread.outputs[29]: <I64>>: "
 482             "Loc(kind=LocKind.GPR, start=43, reg_len=1), "
 483             "<spread.outputs[30]: <I64>>: "
 484             "Loc(kind=LocKind.GPR, start=44, reg_len=1), "
 485             "<spread.outputs[31]: <I64>>: "
 486             "Loc(kind=LocKind.GPR, start=45, reg_len=1), "
 487             "<spread.out28.copy.outputs[0]: <I64>>: "
 488             "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
 489             "<spread.out27.copy.outputs[0]: <I64>>: "
 490             "Loc(kind=LocKind.GPR, start=7, reg_len=1), "
 491             "<spread.out26.copy.outputs[0]: <I64>>: "
 492             "Loc(kind=LocKind.GPR, start=8, reg_len=1), "
 493             "<spread.out25.copy.outputs[0]: <I64>>: "
 494             "Loc(kind=LocKind.GPR, start=9, reg_len=1), "
 495             "<spread.out24.copy.outputs[0]: <I64>>: "
 496             "Loc(kind=LocKind.GPR, start=10, reg_len=1), "
 497             "<spread.out23.copy.outputs[0]: <I64>>: "
 498             "Loc(kind=LocKind.GPR, start=11, reg_len=1), "
 499             "<spread.out22.copy.outputs[0]: <I64>>: "
 500             "Loc(kind=LocKind.GPR, start=12, reg_len=1), "
 501             "<spread.out21.copy.outputs[0]: <I64>>: "
 502             "Loc(kind=LocKind.GPR, start=46, reg_len=1), "
 503             "<spread.out20.copy.outputs[0]: <I64>>: "
 504             "Loc(kind=LocKind.GPR, start=47, reg_len=1), "
 505             "<spread.out19.copy.outputs[0]: <I64>>: "
 506             "Loc(kind=LocKind.GPR, start=48, reg_len=1), "
 507             "<spread.out18.copy.outputs[0]: <I64>>: "
 508             "Loc(kind=LocKind.GPR, start=49, reg_len=1), "
 509             "<spread.out17.copy.outputs[0]: <I64>>: "
 510             "Loc(kind=LocKind.GPR, start=50, reg_len=1), "
 511             "<spread.out16.copy.outputs[0]: <I64>>: "
 512             "Loc(kind=LocKind.GPR, start=51, reg_len=1), "
 513             "<spread.out15.copy.outputs[0]: <I64>>: "
 514             "Loc(kind=LocKind.GPR, start=52, reg_len=1), "
 515             "<spread.out14.copy.outputs[0]: <I64>>: "
 516             "Loc(kind=LocKind.GPR, start=53, reg_len=1), "
 517             "<spread.out13.copy.outputs[0]: <I64>>: "
 518             "Loc(kind=LocKind.GPR, start=54, reg_len=1), "
 519             "<spread.out12.copy.outputs[0]: <I64>>: "
 520             "Loc(kind=LocKind.GPR, start=55, reg_len=1), "
 521             "<spread.out11.copy.outputs[0]: <I64>>: "
 522             "Loc(kind=LocKind.GPR, start=56, reg_len=1), "
 523             "<spread.out10.copy.outputs[0]: <I64>>: "
 524             "Loc(kind=LocKind.GPR, start=57, reg_len=1), "
 525             "<spread.out9.copy.outputs[0]: <I64>>: "
 526             "Loc(kind=LocKind.GPR, start=58, reg_len=1), "
 527             "<spread.out8.copy.outputs[0]: <I64>>: "
 528             "Loc(kind=LocKind.GPR, start=59, reg_len=1), "
 529             "<spread.out7.copy.outputs[0]: <I64>>: "
 530             "Loc(kind=LocKind.GPR, start=60, reg_len=1), "
 531             "<spread.out6.copy.outputs[0]: <I64>>: "
 532             "Loc(kind=LocKind.GPR, start=61, reg_len=1), "
 533             "<spread.out5.copy.outputs[0]: <I64>>: "
 534             "Loc(kind=LocKind.GPR, start=62, reg_len=1), "
 535             "<spread.out4.copy.outputs[0]: <I64>>: "
 536             "Loc(kind=LocKind.GPR, start=63, reg_len=1), "
 537             "<spread.out3.copy.outputs[0]: <I64>>: "
 538             "Loc(kind=LocKind.GPR, start=64, reg_len=1), "
 539             "<spread.out2.copy.outputs[0]: <I64>>: "
 540             "Loc(kind=LocKind.GPR, start=65, reg_len=1), "
 541             "<spread.out1.copy.outputs[0]: <I64>>: "
 542             "Loc(kind=LocKind.GPR, start=66, reg_len=1), "
 543             "<spread.out0.copy.outputs[0]: <I64>>: "
 544             "Loc(kind=LocKind.GPR, start=67, reg_len=1), "
 545             "<spread.inp1.setvl.outputs[0]: <VL_MAXVL>>: "
 546             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 547             "<spread.inp0.copy.outputs[0]: <I64*32>>: "
 548             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 549             "<spread.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
 550             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 551             "<li.out0.copy.outputs[0]: <I64*32>>: "
 552             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 553             "<li.out0.setvl.outputs[0]: <VL_MAXVL>>: "
 554             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 555             "<li.outputs[0]: <I64*32>>: "
 556             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 557             "<li.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
 558             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 559             "<vl.outputs[0]: <VL_MAXVL>>: "
 560             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1)}"
 561         )
 562         state = GenAsmState(reg_assignments)
 563         fn.gen_asm(state)
 564         self.assertEqual(state.output, [
 565             'setvl 0, 0, 32, 0, 1, 1',
 566             'setvl 0, 0, 32, 0, 1, 1',
 567             'sv.addi *14, 0, 0',
 568             'setvl 0, 0, 32, 0, 1, 1',
 569             'setvl 0, 0, 32, 0, 1, 1',
 570             'setvl 0, 0, 32, 0, 1, 1',
 571             'or 67, 14, 14',
 572             'or 66, 15, 15',
 573             'or 65, 16, 16',
 574             'or 64, 17, 17',
 575             'or 63, 18, 18',
 576             'or 62, 19, 19',
 577             'or 61, 20, 20',
 578             'or 60, 21, 21',
 579             'or 59, 22, 22',
 580             'or 58, 23, 23',
 581             'or 57, 24, 24',
 582             'or 56, 25, 25',
 583             'or 55, 26, 26',
 584             'or 54, 27, 27',
 585             'or 53, 28, 28',
 586             'or 52, 29, 29',
 587             'or 51, 30, 30',
 588             'or 50, 31, 31',
 589             'or 49, 32, 32',
 590             'or 48, 33, 33',
 591             'or 47, 34, 34',
 592             'or 46, 35, 35',
 593             'or 12, 36, 36',
 594             'or 11, 37, 37',
 595             'or 10, 38, 38',
 596             'or 9, 39, 39',
 597             'or 8, 40, 40',
 598             'or 7, 41, 41',
 599             'or 6, 42, 42',
 600             'or 5, 43, 43',
 601             'or 4, 44, 44',
 602             'or 3, 45, 45',
 603             'or 14, 3, 3',
 604             'or 15, 4, 4',
 605             'or 16, 5, 5',
 606             'or 17, 6, 6',
 607             'or 18, 7, 7',
 608             'or 19, 8, 8',
 609             'or 20, 9, 9',
 610             'or 21, 10, 10',
 611             'or 22, 11, 11',
 612             'or 23, 12, 12',
 613             'or 24, 46, 46',
 614             'or 25, 47, 47',
 615             'or 26, 48, 48',
 616             'or 27, 49, 49',
 617             'or 28, 50, 50',
 618             'or 29, 51, 51',
 619             'or 30, 52, 52',
 620             'or 31, 53, 53',
 621             'or 32, 54, 54',
 622             'or 33, 55, 55',
 623             'or 34, 56, 56',
 624             'or 35, 57, 57',
 625             'or 36, 58, 58',
 626             'or 37, 59, 59',
 627             'or 38, 60, 60',
 628             'or 39, 61, 61',
 629             'or 40, 62, 62',
 630             'or 41, 63, 63',
 631             'or 42, 64, 64',
 632             'or 43, 65, 65',
 633             'or 44, 66, 66',
 634             'or 45, 67, 67',
 635             'setvl 0, 0, 32, 0, 1, 1',
 636             'setvl 0, 0, 32, 0, 1, 1'])
 637
 638
 639 if __name__ == "__main__":
 640     _ = unittest.main()