src/bigint_presentation_code/_tests/test_register_allocator2.py

   1 import sys
   2 import unittest
   3
   4 from bigint_presentation_code.compiler_ir2 import (Fn, GenAsmState, OpKind,
   5                                                    SSAVal)
   6 from bigint_presentation_code.register_allocator2 import allocate_registers
   7
   8
   9 class TestCompilerIR(unittest.TestCase):
  10     maxDiff = None
  11
  12     def make_add_fn(self):
  13         # type: () -> tuple[Fn, SSAVal]
  14         fn = Fn()
  15         op0 = fn.append_new_op(OpKind.FuncArgR3, name="arg")
  16         arg = op0.outputs[0]
  17         MAXVL = 32
  18         op1 = fn.append_new_op(OpKind.SetVLI, immediates=[MAXVL], name="vl")
  19         vl = op1.outputs[0]
  20         op2 = fn.append_new_op(
  21             OpKind.SvLd, input_vals=[arg, vl], immediates=[0], maxvl=MAXVL,
  22             name="ld")
  23         a = op2.outputs[0]
  24         op3 = fn.append_new_op(OpKind.SvLI, input_vals=[vl], immediates=[0],
  25                                maxvl=MAXVL, name="li")
  26         b = op3.outputs[0]
  27         op4 = fn.append_new_op(OpKind.SetCA, name="ca")
  28         ca = op4.outputs[0]
  29         op5 = fn.append_new_op(
  30             OpKind.SvAddE, input_vals=[a, b, ca, vl], maxvl=MAXVL, name="add")
  31         s = op5.outputs[0]
  32         _ = fn.append_new_op(OpKind.SvStd, input_vals=[s, arg, vl],
  33                              immediates=[0], maxvl=MAXVL, name="st")
  34         return fn, arg
  35
  36     def test_register_allocate(self):
  37         fn, _arg = self.make_add_fn()
  38         reg_assignments = allocate_registers(fn)
  39
  40         self.assertEqual(
  41             repr(reg_assignments),
  42             "{<add.outputs[0]: <I64*32>>: "
  43             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
  44             "<add.inp1.copy.outputs[0]: <I64*32>>: "
  45             "Loc(kind=LocKind.GPR, start=46, reg_len=32), "
  46             "<add.inp0.copy.outputs[0]: <I64*32>>: "
  47             "Loc(kind=LocKind.GPR, start=78, reg_len=32), "
  48             "<st.inp2.setvl.outputs[0]: <VL_MAXVL>>: "
  49             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  50             "<st.inp1.copy.outputs[0]: <I64>>: "
  51             "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
  52             "<st.inp0.copy.outputs[0]: <I64*32>>: "
  53             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
  54             "<st.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
  55             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  56             "<add.out0.copy.outputs[0]: <I64*32>>: "
  57             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
  58             "<add.out0.setvl.outputs[0]: <VL_MAXVL>>: "
  59             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  60             "<ca.outputs[0]: <CA>>: "
  61             "Loc(kind=LocKind.CA, start=0, reg_len=1), "
  62             "<add.outputs[1]: <CA>>: "
  63             "Loc(kind=LocKind.CA, start=0, reg_len=1), "
  64             "<add.inp3.setvl.outputs[0]: <VL_MAXVL>>: "
  65             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  66             "<add.inp1.setvl.outputs[0]: <VL_MAXVL>>: "
  67             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  68             "<add.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
  69             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  70             "<li.out0.copy.outputs[0]: <I64*32>>: "
  71             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
  72             "<li.out0.setvl.outputs[0]: <VL_MAXVL>>: "
  73             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  74             "<li.outputs[0]: <I64*32>>: "
  75             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
  76             "<li.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
  77             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  78             "<ld.out0.copy.outputs[0]: <I64*32>>: "
  79             "Loc(kind=LocKind.GPR, start=46, reg_len=32), "
  80             "<ld.out0.setvl.outputs[0]: <VL_MAXVL>>: "
  81             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  82             "<ld.outputs[0]: <I64*32>>: "
  83             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
  84             "<ld.inp1.setvl.outputs[0]: <VL_MAXVL>>: "
  85             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  86             "<ld.inp0.copy.outputs[0]: <I64>>: "
  87             "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
  88             "<vl.outputs[0]: <VL_MAXVL>>: "
  89             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
  90             "<arg.out0.copy.outputs[0]: <I64>>: "
  91             "Loc(kind=LocKind.GPR, start=4, reg_len=1), "
  92             "<arg.outputs[0]: <I64>>: "
  93             "Loc(kind=LocKind.GPR, start=3, reg_len=1)}"
  94         )
  95
  96     def test_gen_asm(self):
  97         fn, _arg = self.make_add_fn()
  98         reg_assignments = allocate_registers(fn)
  99
 100         self.assertEqual(
 101             repr(reg_assignments),
 102             "{<add.outputs[0]: <I64*32>>: "
 103             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 104             "<add.inp1.copy.outputs[0]: <I64*32>>: "
 105             "Loc(kind=LocKind.GPR, start=46, reg_len=32), "
 106             "<add.inp0.copy.outputs[0]: <I64*32>>: "
 107             "Loc(kind=LocKind.GPR, start=78, reg_len=32), "
 108             "<st.inp2.setvl.outputs[0]: <VL_MAXVL>>: "
 109             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 110             "<st.inp1.copy.outputs[0]: <I64>>: "
 111             "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
 112             "<st.inp0.copy.outputs[0]: <I64*32>>: "
 113             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 114             "<st.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
 115             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 116             "<add.out0.copy.outputs[0]: <I64*32>>: "
 117             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 118             "<add.out0.setvl.outputs[0]: <VL_MAXVL>>: "
 119             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 120             "<ca.outputs[0]: <CA>>: "
 121             "Loc(kind=LocKind.CA, start=0, reg_len=1), "
 122             "<add.outputs[1]: <CA>>: "
 123             "Loc(kind=LocKind.CA, start=0, reg_len=1), "
 124             "<add.inp3.setvl.outputs[0]: <VL_MAXVL>>: "
 125             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 126             "<add.inp1.setvl.outputs[0]: <VL_MAXVL>>: "
 127             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 128             "<add.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
 129             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 130             "<li.out0.copy.outputs[0]: <I64*32>>: "
 131             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 132             "<li.out0.setvl.outputs[0]: <VL_MAXVL>>: "
 133             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 134             "<li.outputs[0]: <I64*32>>: "
 135             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 136             "<li.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
 137             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 138             "<ld.out0.copy.outputs[0]: <I64*32>>: "
 139             "Loc(kind=LocKind.GPR, start=46, reg_len=32), "
 140             "<ld.out0.setvl.outputs[0]: <VL_MAXVL>>: "
 141             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 142             "<ld.outputs[0]: <I64*32>>: "
 143             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 144             "<ld.inp1.setvl.outputs[0]: <VL_MAXVL>>: "
 145             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 146             "<ld.inp0.copy.outputs[0]: <I64>>: "
 147             "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
 148             "<vl.outputs[0]: <VL_MAXVL>>: "
 149             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 150             "<arg.out0.copy.outputs[0]: <I64>>: "
 151             "Loc(kind=LocKind.GPR, start=4, reg_len=1), "
 152             "<arg.outputs[0]: <I64>>: "
 153             "Loc(kind=LocKind.GPR, start=3, reg_len=1)}"
 154         )
 155         state = GenAsmState(reg_assignments)
 156         fn.gen_asm(state)
 157         self.assertEqual(state.output, [
 158             'or 4, 3, 3',
 159             'setvl 0, 0, 32, 0, 1, 1',
 160             'or 3, 4, 4',
 161             'setvl 0, 0, 32, 0, 1, 1',
 162             'sv.ld *14, 0(3)',
 163             'setvl 0, 0, 32, 0, 1, 1',
 164             'sv.or *46, *14, *14',
 165             'setvl 0, 0, 32, 0, 1, 1',
 166             'sv.addi *14, 0, 0',
 167             'setvl 0, 0, 32, 0, 1, 1',
 168             'subfc 0, 0, 0',
 169             'setvl 0, 0, 32, 0, 1, 1',
 170             'sv.or *78, *46, *46',
 171             'setvl 0, 0, 32, 0, 1, 1',
 172             'sv.or *46, *14, *14',
 173             'setvl 0, 0, 32, 0, 1, 1',
 174             'sv.adde *14, *78, *46',
 175             'setvl 0, 0, 32, 0, 1, 1',
 176             'setvl 0, 0, 32, 0, 1, 1',
 177             'or 3, 4, 4',
 178             'setvl 0, 0, 32, 0, 1, 1',
 179             'sv.std *14, 0(3)',
 180         ])
 181
 182     def test_register_allocate_spread(self):
 183         fn = Fn()
 184         maxvl = 32
 185         vl = fn.append_new_op(OpKind.SetVLI, immediates=[maxvl],
 186                               name="vl", maxvl=maxvl).outputs[0]
 187         li = fn.append_new_op(OpKind.SvLI, input_vals=[vl], immediates=[0],
 188                               name="li", maxvl=maxvl).outputs[0]
 189         spread = fn.append_new_op(OpKind.Spread, input_vals=[li, vl],
 190                                   name="spread", maxvl=maxvl).outputs
 191         _concat = fn.append_new_op(
 192             OpKind.Concat, input_vals=[*spread[::-1], vl],
 193             name="concat", maxvl=maxvl)
 194         reg_assignments = allocate_registers(fn, debug_out=sys.stdout)
 195
 196         self.assertEqual(
 197             repr(reg_assignments),
 198             "{<concat.out0.copy.outputs[0]: <I64*32>>: "
 199             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 200             "<concat.out0.setvl.outputs[0]: <VL_MAXVL>>: "
 201             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 202             "<concat.outputs[0]: <I64*32>>: "
 203             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 204             "<concat.inp0.copy.outputs[0]: <I64>>: "
 205             "Loc(kind=LocKind.GPR, start=14, reg_len=1), "
 206             "<concat.inp1.copy.outputs[0]: <I64>>: "
 207             "Loc(kind=LocKind.GPR, start=15, reg_len=1), "
 208             "<concat.inp2.copy.outputs[0]: <I64>>: "
 209             "Loc(kind=LocKind.GPR, start=16, reg_len=1), "
 210             "<concat.inp3.copy.outputs[0]: <I64>>: "
 211             "Loc(kind=LocKind.GPR, start=17, reg_len=1), "
 212             "<concat.inp4.copy.outputs[0]: <I64>>: "
 213             "Loc(kind=LocKind.GPR, start=18, reg_len=1), "
 214             "<concat.inp5.copy.outputs[0]: <I64>>: "
 215             "Loc(kind=LocKind.GPR, start=19, reg_len=1), "
 216             "<concat.inp6.copy.outputs[0]: <I64>>: "
 217             "Loc(kind=LocKind.GPR, start=20, reg_len=1), "
 218             "<concat.inp7.copy.outputs[0]: <I64>>: "
 219             "Loc(kind=LocKind.GPR, start=21, reg_len=1), "
 220             "<concat.inp8.copy.outputs[0]: <I64>>: "
 221             "Loc(kind=LocKind.GPR, start=22, reg_len=1), "
 222             "<concat.inp9.copy.outputs[0]: <I64>>: "
 223             "Loc(kind=LocKind.GPR, start=23, reg_len=1), "
 224             "<concat.inp10.copy.outputs[0]: <I64>>: "
 225             "Loc(kind=LocKind.GPR, start=24, reg_len=1), "
 226             "<concat.inp11.copy.outputs[0]: <I64>>: "
 227             "Loc(kind=LocKind.GPR, start=25, reg_len=1), "
 228             "<concat.inp12.copy.outputs[0]: <I64>>: "
 229             "Loc(kind=LocKind.GPR, start=26, reg_len=1), "
 230             "<concat.inp13.copy.outputs[0]: <I64>>: "
 231             "Loc(kind=LocKind.GPR, start=27, reg_len=1), "
 232             "<concat.inp14.copy.outputs[0]: <I64>>: "
 233             "Loc(kind=LocKind.GPR, start=28, reg_len=1), "
 234             "<concat.inp15.copy.outputs[0]: <I64>>: "
 235             "Loc(kind=LocKind.GPR, start=29, reg_len=1), "
 236             "<concat.inp16.copy.outputs[0]: <I64>>: "
 237             "Loc(kind=LocKind.GPR, start=30, reg_len=1), "
 238             "<concat.inp17.copy.outputs[0]: <I64>>: "
 239             "Loc(kind=LocKind.GPR, start=31, reg_len=1), "
 240             "<concat.inp18.copy.outputs[0]: <I64>>: "
 241             "Loc(kind=LocKind.GPR, start=32, reg_len=1), "
 242             "<concat.inp19.copy.outputs[0]: <I64>>: "
 243             "Loc(kind=LocKind.GPR, start=33, reg_len=1), "
 244             "<concat.inp20.copy.outputs[0]: <I64>>: "
 245             "Loc(kind=LocKind.GPR, start=34, reg_len=1), "
 246             "<concat.inp21.copy.outputs[0]: <I64>>: "
 247             "Loc(kind=LocKind.GPR, start=35, reg_len=1), "
 248             "<concat.inp22.copy.outputs[0]: <I64>>: "
 249             "Loc(kind=LocKind.GPR, start=36, reg_len=1), "
 250             "<concat.inp23.copy.outputs[0]: <I64>>: "
 251             "Loc(kind=LocKind.GPR, start=37, reg_len=1), "
 252             "<concat.inp24.copy.outputs[0]: <I64>>: "
 253             "Loc(kind=LocKind.GPR, start=38, reg_len=1), "
 254             "<concat.inp25.copy.outputs[0]: <I64>>: "
 255             "Loc(kind=LocKind.GPR, start=39, reg_len=1), "
 256             "<concat.inp26.copy.outputs[0]: <I64>>: "
 257             "Loc(kind=LocKind.GPR, start=40, reg_len=1), "
 258             "<concat.inp27.copy.outputs[0]: <I64>>: "
 259             "Loc(kind=LocKind.GPR, start=41, reg_len=1), "
 260             "<concat.inp28.copy.outputs[0]: <I64>>: "
 261             "Loc(kind=LocKind.GPR, start=42, reg_len=1), "
 262             "<concat.inp29.copy.outputs[0]: <I64>>: "
 263             "Loc(kind=LocKind.GPR, start=43, reg_len=1), "
 264             "<concat.inp30.copy.outputs[0]: <I64>>: "
 265             "Loc(kind=LocKind.GPR, start=44, reg_len=1), "
 266             "<concat.inp31.copy.outputs[0]: <I64>>: "
 267             "Loc(kind=LocKind.GPR, start=45, reg_len=1), "
 268             "<concat.inp32.setvl.outputs[0]: <VL_MAXVL>>: "
 269             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 270             "<spread.out31.copy.outputs[0]: <I64>>: "
 271             "Loc(kind=LocKind.GPR, start=3, reg_len=1), "
 272             "<spread.out30.copy.outputs[0]: <I64>>: "
 273             "Loc(kind=LocKind.GPR, start=4, reg_len=1), "
 274             "<spread.out29.copy.outputs[0]: <I64>>: "
 275             "Loc(kind=LocKind.GPR, start=5, reg_len=1), "
 276             "<spread.outputs[0]: <I64>>: "
 277             "Loc(kind=LocKind.GPR, start=14, reg_len=1), "
 278             "<spread.outputs[1]: <I64>>: "
 279             "Loc(kind=LocKind.GPR, start=15, reg_len=1), "
 280             "<spread.outputs[2]: <I64>>: "
 281             "Loc(kind=LocKind.GPR, start=16, reg_len=1), "
 282             "<spread.outputs[3]: <I64>>: "
 283             "Loc(kind=LocKind.GPR, start=17, reg_len=1), "
 284             "<spread.outputs[4]: <I64>>: "
 285             "Loc(kind=LocKind.GPR, start=18, reg_len=1), "
 286             "<spread.outputs[5]: <I64>>: "
 287             "Loc(kind=LocKind.GPR, start=19, reg_len=1), "
 288             "<spread.outputs[6]: <I64>>: "
 289             "Loc(kind=LocKind.GPR, start=20, reg_len=1), "
 290             "<spread.outputs[7]: <I64>>: "
 291             "Loc(kind=LocKind.GPR, start=21, reg_len=1), "
 292             "<spread.outputs[8]: <I64>>: "
 293             "Loc(kind=LocKind.GPR, start=22, reg_len=1), "
 294             "<spread.outputs[9]: <I64>>: "
 295             "Loc(kind=LocKind.GPR, start=23, reg_len=1), "
 296             "<spread.outputs[10]: <I64>>: "
 297             "Loc(kind=LocKind.GPR, start=24, reg_len=1), "
 298             "<spread.outputs[11]: <I64>>: "
 299             "Loc(kind=LocKind.GPR, start=25, reg_len=1), "
 300             "<spread.outputs[12]: <I64>>: "
 301             "Loc(kind=LocKind.GPR, start=26, reg_len=1), "
 302             "<spread.outputs[13]: <I64>>: "
 303             "Loc(kind=LocKind.GPR, start=27, reg_len=1), "
 304             "<spread.outputs[14]: <I64>>: "
 305             "Loc(kind=LocKind.GPR, start=28, reg_len=1), "
 306             "<spread.outputs[15]: <I64>>: "
 307             "Loc(kind=LocKind.GPR, start=29, reg_len=1), "
 308             "<spread.outputs[16]: <I64>>: "
 309             "Loc(kind=LocKind.GPR, start=30, reg_len=1), "
 310             "<spread.outputs[17]: <I64>>: "
 311             "Loc(kind=LocKind.GPR, start=31, reg_len=1), "
 312             "<spread.outputs[18]: <I64>>: "
 313             "Loc(kind=LocKind.GPR, start=32, reg_len=1), "
 314             "<spread.outputs[19]: <I64>>: "
 315             "Loc(kind=LocKind.GPR, start=33, reg_len=1), "
 316             "<spread.outputs[20]: <I64>>: "
 317             "Loc(kind=LocKind.GPR, start=34, reg_len=1), "
 318             "<spread.outputs[21]: <I64>>: "
 319             "Loc(kind=LocKind.GPR, start=35, reg_len=1), "
 320             "<spread.outputs[22]: <I64>>: "
 321             "Loc(kind=LocKind.GPR, start=36, reg_len=1), "
 322             "<spread.outputs[23]: <I64>>: "
 323             "Loc(kind=LocKind.GPR, start=37, reg_len=1), "
 324             "<spread.outputs[24]: <I64>>: "
 325             "Loc(kind=LocKind.GPR, start=38, reg_len=1), "
 326             "<spread.outputs[25]: <I64>>: "
 327             "Loc(kind=LocKind.GPR, start=39, reg_len=1), "
 328             "<spread.outputs[26]: <I64>>: "
 329             "Loc(kind=LocKind.GPR, start=40, reg_len=1), "
 330             "<spread.outputs[27]: <I64>>: "
 331             "Loc(kind=LocKind.GPR, start=41, reg_len=1), "
 332             "<spread.outputs[28]: <I64>>: "
 333             "Loc(kind=LocKind.GPR, start=42, reg_len=1), "
 334             "<spread.outputs[29]: <I64>>: "
 335             "Loc(kind=LocKind.GPR, start=43, reg_len=1), "
 336             "<spread.outputs[30]: <I64>>: "
 337             "Loc(kind=LocKind.GPR, start=44, reg_len=1), "
 338             "<spread.outputs[31]: <I64>>: "
 339             "Loc(kind=LocKind.GPR, start=45, reg_len=1), "
 340             "<spread.out28.copy.outputs[0]: <I64>>: "
 341             "Loc(kind=LocKind.GPR, start=6, reg_len=1), "
 342             "<spread.out27.copy.outputs[0]: <I64>>: "
 343             "Loc(kind=LocKind.GPR, start=7, reg_len=1), "
 344             "<spread.out26.copy.outputs[0]: <I64>>: "
 345             "Loc(kind=LocKind.GPR, start=8, reg_len=1), "
 346             "<spread.out25.copy.outputs[0]: <I64>>: "
 347             "Loc(kind=LocKind.GPR, start=9, reg_len=1), "
 348             "<spread.out24.copy.outputs[0]: <I64>>: "
 349             "Loc(kind=LocKind.GPR, start=10, reg_len=1), "
 350             "<spread.out23.copy.outputs[0]: <I64>>: "
 351             "Loc(kind=LocKind.GPR, start=11, reg_len=1), "
 352             "<spread.out22.copy.outputs[0]: <I64>>: "
 353             "Loc(kind=LocKind.GPR, start=12, reg_len=1), "
 354             "<spread.out21.copy.outputs[0]: <I64>>: "
 355             "Loc(kind=LocKind.GPR, start=46, reg_len=1), "
 356             "<spread.out20.copy.outputs[0]: <I64>>: "
 357             "Loc(kind=LocKind.GPR, start=47, reg_len=1), "
 358             "<spread.out19.copy.outputs[0]: <I64>>: "
 359             "Loc(kind=LocKind.GPR, start=48, reg_len=1), "
 360             "<spread.out18.copy.outputs[0]: <I64>>: "
 361             "Loc(kind=LocKind.GPR, start=49, reg_len=1), "
 362             "<spread.out17.copy.outputs[0]: <I64>>: "
 363             "Loc(kind=LocKind.GPR, start=50, reg_len=1), "
 364             "<spread.out16.copy.outputs[0]: <I64>>: "
 365             "Loc(kind=LocKind.GPR, start=51, reg_len=1), "
 366             "<spread.out15.copy.outputs[0]: <I64>>: "
 367             "Loc(kind=LocKind.GPR, start=52, reg_len=1), "
 368             "<spread.out14.copy.outputs[0]: <I64>>: "
 369             "Loc(kind=LocKind.GPR, start=53, reg_len=1), "
 370             "<spread.out13.copy.outputs[0]: <I64>>: "
 371             "Loc(kind=LocKind.GPR, start=54, reg_len=1), "
 372             "<spread.out12.copy.outputs[0]: <I64>>: "
 373             "Loc(kind=LocKind.GPR, start=55, reg_len=1), "
 374             "<spread.out11.copy.outputs[0]: <I64>>: "
 375             "Loc(kind=LocKind.GPR, start=56, reg_len=1), "
 376             "<spread.out10.copy.outputs[0]: <I64>>: "
 377             "Loc(kind=LocKind.GPR, start=57, reg_len=1), "
 378             "<spread.out9.copy.outputs[0]: <I64>>: "
 379             "Loc(kind=LocKind.GPR, start=58, reg_len=1), "
 380             "<spread.out8.copy.outputs[0]: <I64>>: "
 381             "Loc(kind=LocKind.GPR, start=59, reg_len=1), "
 382             "<spread.out7.copy.outputs[0]: <I64>>: "
 383             "Loc(kind=LocKind.GPR, start=60, reg_len=1), "
 384             "<spread.out6.copy.outputs[0]: <I64>>: "
 385             "Loc(kind=LocKind.GPR, start=61, reg_len=1), "
 386             "<spread.out5.copy.outputs[0]: <I64>>: "
 387             "Loc(kind=LocKind.GPR, start=62, reg_len=1), "
 388             "<spread.out4.copy.outputs[0]: <I64>>: "
 389             "Loc(kind=LocKind.GPR, start=63, reg_len=1), "
 390             "<spread.out3.copy.outputs[0]: <I64>>: "
 391             "Loc(kind=LocKind.GPR, start=64, reg_len=1), "
 392             "<spread.out2.copy.outputs[0]: <I64>>: "
 393             "Loc(kind=LocKind.GPR, start=65, reg_len=1), "
 394             "<spread.out1.copy.outputs[0]: <I64>>: "
 395             "Loc(kind=LocKind.GPR, start=66, reg_len=1), "
 396             "<spread.out0.copy.outputs[0]: <I64>>: "
 397             "Loc(kind=LocKind.GPR, start=67, reg_len=1), "
 398             "<spread.inp1.setvl.outputs[0]: <VL_MAXVL>>: "
 399             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 400             "<spread.inp0.copy.outputs[0]: <I64*32>>: "
 401             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 402             "<spread.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
 403             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 404             "<li.out0.copy.outputs[0]: <I64*32>>: "
 405             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 406             "<li.out0.setvl.outputs[0]: <VL_MAXVL>>: "
 407             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 408             "<li.outputs[0]: <I64*32>>: "
 409             "Loc(kind=LocKind.GPR, start=14, reg_len=32), "
 410             "<li.inp0.setvl.outputs[0]: <VL_MAXVL>>: "
 411             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1), "
 412             "<vl.outputs[0]: <VL_MAXVL>>: "
 413             "Loc(kind=LocKind.VL_MAXVL, start=0, reg_len=1)}"
 414         )
 415         state = GenAsmState(reg_assignments)
 416         fn.gen_asm(state)
 417         self.assertEqual(state.output, [
 418             'setvl 0, 0, 32, 0, 1, 1',
 419             'setvl 0, 0, 32, 0, 1, 1',
 420             'sv.addi *14, 0, 0',
 421             'setvl 0, 0, 32, 0, 1, 1',
 422             'setvl 0, 0, 32, 0, 1, 1',
 423             'setvl 0, 0, 32, 0, 1, 1',
 424             'or 67, 14, 14',
 425             'or 66, 15, 15',
 426             'or 65, 16, 16',
 427             'or 64, 17, 17',
 428             'or 63, 18, 18',
 429             'or 62, 19, 19',
 430             'or 61, 20, 20',
 431             'or 60, 21, 21',
 432             'or 59, 22, 22',
 433             'or 58, 23, 23',
 434             'or 57, 24, 24',
 435             'or 56, 25, 25',
 436             'or 55, 26, 26',
 437             'or 54, 27, 27',
 438             'or 53, 28, 28',
 439             'or 52, 29, 29',
 440             'or 51, 30, 30',
 441             'or 50, 31, 31',
 442             'or 49, 32, 32',
 443             'or 48, 33, 33',
 444             'or 47, 34, 34',
 445             'or 46, 35, 35',
 446             'or 12, 36, 36',
 447             'or 11, 37, 37',
 448             'or 10, 38, 38',
 449             'or 9, 39, 39',
 450             'or 8, 40, 40',
 451             'or 7, 41, 41',
 452             'or 6, 42, 42',
 453             'or 5, 43, 43',
 454             'or 4, 44, 44',
 455             'or 3, 45, 45',
 456             'or 14, 3, 3',
 457             'or 15, 4, 4',
 458             'or 16, 5, 5',
 459             'or 17, 6, 6',
 460             'or 18, 7, 7',
 461             'or 19, 8, 8',
 462             'or 20, 9, 9',
 463             'or 21, 10, 10',
 464             'or 22, 11, 11',
 465             'or 23, 12, 12',
 466             'or 24, 46, 46',
 467             'or 25, 47, 47',
 468             'or 26, 48, 48',
 469             'or 27, 49, 49',
 470             'or 28, 50, 50',
 471             'or 29, 51, 51',
 472             'or 30, 52, 52',
 473             'or 31, 53, 53',
 474             'or 32, 54, 54',
 475             'or 33, 55, 55',
 476             'or 34, 56, 56',
 477             'or 35, 57, 57',
 478             'or 36, 58, 58',
 479             'or 37, 59, 59',
 480             'or 38, 60, 60',
 481             'or 39, 61, 61',
 482             'or 40, 62, 62',
 483             'or 41, 63, 63',
 484             'or 42, 64, 64',
 485             'or 43, 65, 65',
 486             'or 44, 66, 66',
 487             'or 45, 67, 67',
 488             'setvl 0, 0, 32, 0, 1, 1',
 489             'setvl 0, 0, 32, 0, 1, 1'])
 490
 491
 492 if __name__ == "__main__":
 493     _ = unittest.main()