src/bsv/bsv_lib/slow_peripherals_template.bsv

   1 package slow_peripherals;
   2         /*===== Project imports =====*/
   3         import defined_types::*;
   4         import AXI4_Lite_Fabric::*;
   5         import AXI4_Lite_Types::*;
   6         import AXI4_Fabric::*;
   7         import AXI4_Types::*;
   8         import Semi_FIFOF::*;
   9         import AXI4Lite_AXI4_Bridge::*;
  10         `include "instance_defines.bsv"
  11     /* ==== define the AXI Addresses ==== */
  12 {2}
  13     /* ==== define the number of slow peripheral irqs ==== */
  14 {11}
  15     /*====== AXI4 Lite slave declarations =======*/
  16
  17 {3}
  18         /*===========================*/
  19         /*=== package imports ===*/
  20         import Clocks::*;
  21         import GetPut::*;
  22         import ClientServer::*;
  23         import Connectable::*;
  24         import Vector::*;
  25         import FIFO::*;
  26         /*=======================*/
  27         /*===== Import the slow peripherals ====*/
  28 {0}
  29     `ifdef CLINT
  30         import clint::*;
  31     `endif
  32     `ifdef PLIC
  33         import plic             ::*;
  34     `endif
  35         `ifdef AXIEXP
  36                 import axiexpansion     ::*;
  37         `endif
  38         `ifdef QSPI
  39                 import qspi                              :: *;
  40         `endif
  41         /*=====================================*/
  42
  43         /*===== interface declaration =====*/
  44         interface SP_dedicated_ios;
  45                 `ifdef AXIEXP
  46                         interface Get#(Bit#(67)) axiexp1_out;
  47                         interface Put#(Bit#(67)) axiexp1_in;
  48                 `endif
  49         endinterface
  50         interface Ifc_slow_peripherals;
  51                 interface AXI4_Slave_IFC#(`ADDR,`DATA,`USERSPACE) axi_slave;
  52                 interface SP_dedicated_ios slow_ios;
  53                 `ifdef CLINT
  54                         method Bit#(1) msip_int;
  55                         method Bit#(1) mtip_int;
  56                         method Bit#(`DATA) mtime;
  57                 `endif
  58                 `ifdef PLIC method ActionValue#(Tuple2#(Bool,Bool)) intrpt_note; `endif
  59         interface IOCellSide iocell_side; // mandatory interface
  60         `ifdef PLIC
  61 {1}
  62         `endif
  63         endinterface
  64         /*================================*/
  65
  66         function Tuple2#(Bool, Bit#(TLog#(Num_Slow_Slaves)))
  67                      fn_address_mapping (Bit#(`ADDR) addr);
  68         `ifdef CLINT
  69             if(addr>=`ClintBase && addr<=`ClintEnd)
  70                 return tuple2(True,fromInteger(valueOf(CLINT_slave_num)));
  71             else
  72         `endif
  73         `ifdef PLIC
  74             if(addr>=`PLICBase && addr<=`PLICEnd)
  75                 return tuple2(True,fromInteger(valueOf(Plic_slave_num)));
  76             else
  77         `endif
  78         `ifdef AXIEXP
  79             if(addr>=`AxiExp1Base && addr<=`AxiExp1End)
  80                 return tuple2(True,fromInteger(valueOf(AxiExp1_slave_num)));
  81             else
  82         `endif
  83 {4}
  84         return tuple2(False,?);
  85         endfunction
  86
  87         (*synthesize*)
  88         module mkslow_peripherals#(Clock fast_clock, Reset fast_reset,
  89                                Clock uart_clock, Reset uart_reset
  90                               `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif
  91                               )(Ifc_slow_peripherals);
  92                 Clock sp_clock <-exposeCurrentClock; // slow peripheral clock
  93                 Reset sp_reset <-exposeCurrentReset; // slow peripheral reset
  94
  95                 /*======= Module declarations for each peripheral =======*/
  96 {5}
  97                 `ifdef CLINT
  98                         Ifc_clint       clint <- mkclint();
  99                 `endif
 100                 `ifdef PLIC
 101                         Ifc_PLIC_AXI    plic <- mkplicperipheral();
 102             Wire#(Bit#(TLog#(`INTERRUPT_PINS))) interrupt_id <- mkWire();
 103             Vector#(`INTERRUPT_PINS, FIFO#(bit))
 104                             ff_gateway_queue <- replicateM(mkFIFO);
 105                 `endif
 106                 `ifdef AXIEXP
 107                         Ifc_AxiExpansion axiexp1 <- mkAxiExpansion();
 108                 `endif
 109         Ifc_pinmux pinmux <- mkpinmux; // mandatory
 110
 111                 /*=======================================================*/
 112
 113             AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `ADDR, `DATA,`USERSPACE)
 114                 slow_fabric <- mkAXI4_Lite_Fabric(fn_address_mapping);
 115                 Ifc_AXI4Lite_AXI4_Bridge
 116                 bridge<-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset);
 117
 118                 mkConnection (bridge.axi4_lite_master,  slow_fabric.v_from_masters [0]);
 119                 /*======= Slave connections to AXI4Lite fabric =========*/
 120 {6}
 121                 `ifdef CLINT
 122                         mkConnection (slow_fabric.v_to_slaves
 123                     [fromInteger(valueOf(CLINT_slave_num))],
 124                     clint.axi4_slave);
 125                 `endif
 126                 `ifdef PLIC
 127                         mkConnection (slow_fabric.v_to_slaves
 128                     [fromInteger(valueOf(Plic_slave_num))],
 129                     plic.axi4_slave_plic); //
 130                 `endif
 131                 `ifdef AXIEXP
 132                 mkConnection (slow_fabric.v_to_slaves
 133                     [fromInteger(valueOf(AxiExp1_slave_num))],
 134                     axiexp1.axi_slave); //
 135                 `endif
 136
 137     /*========== pinmux connections ============*/
 138 {7}
 139 {8}
 140
 141     /*=================== PLIC Connections ==================== */
 142 `ifdef PLIC
 143 {10}
 144
 145     rule rl_completion_msg_from_plic;
 146           let id <- plic.intrpt_completion;
 147       interrupt_id <= id;
 148       `ifdef verbose
 149         $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id);
 150        `endif
 151         endrule
 152
 153     for(Integer i=0; i <`INTERRUPT_PINS; i=i+1) begin
 154             rule deq_gateway_queue;
 155                     if(interrupt_id==fromInteger(i)) begin
 156                             ff_gateway_queue[i].deq;
 157           `ifdef verbose
 158             $display($time,"Dequeing the Interrupt request for ID: %d",i);
 159           `endif
 160         end
 161       endrule
 162     end
 163     /*TODO DMA interrupt need to be connected to the plic */
 164     for(Integer i=1; i<8; i=i+1) begin
 165       rule rl_connect_dma_interrupts_to_plic;
 166        `ifdef DMA
 167             if(dma.interrupt_to_processor[i-1]==1'b1) begin
 168                 ff_gateway_queue[i].enq(1);
 169                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 170             end
 171         `else
 172             ff_gateway_queue[i].enq(0);
 173         `endif
 174       endrule
 175     end
 176
 177 `endif // end PLIC
 178         /*======================================================= */
 179
 180                 /* ===== interface definition =======*/
 181                 interface axi_slave=bridge.axi_slave;
 182                 `ifdef PLIC method intrpt_note = plic.intrpt_note; `endif
 183                 `ifdef CLINT
 184                         method msip_int=clint.msip_int;
 185                         method mtip_int=clint.mtip_int;
 186                         method mtime=clint.mtime;
 187                 `endif
 188 `ifdef PLIC
 189 {12}
 190 `endif // end PLIC
 191                 interface SP_dedicated_ios slow_ios;
 192         /* template for dedicated peripherals
 193                         `ifdef UART0
 194                                 interface uart0_coe=uart0.coe_rs232;
 195                         `endif
 196                         `ifdef UART1
 197                                 interface uart1_coe=uart1.coe_rs232;
 198                         `endif
 199                         `ifdef I2C0
 200                                 interface i2c0_out=i2c0.out;
 201                         `endif
 202                         `ifdef I2C1
 203                                 interface i2c1_out=i2c1.out;
 204                         `endif
 205                         `ifdef QSPI0
 206                                 interface qspi0_out = qspi0.out;
 207                         `endif
 208                         `ifdef QSPI1
 209                                 interface qspi1_out = qspi1.out;
 210                         `endif
 211                         `ifdef AXIEXP
 212                                 interface axiexp1_out=axiexp1.slave_out;
 213                                 interface axiexp1_in=axiexp1.slave_in;
 214                         `endif
 215             `ifdef PWM_AXI4Lite
 216                 interface pwm_o = pwm_bus.pwm_io;
 217             `endif
 218        */
 219                 endinterface
 220         interface iocell_side=pinmux.iocell_side;
 221 {9}
 222 {13}
 223                 /*===================================*/
 224         endmodule
 225 endpackage