src/bsv/bsv_lib/slow_peripherals_template.bsv

   1 package slow_peripherals;
   2         /*===== Project imports =====*/
   3         import defined_types::*;
   4         import AXI4_Lite_Fabric::*;
   5         import AXI4_Lite_Types::*;
   6         import AXI4_Fabric::*;
   7         import AXI4_Types::*;
   8         import Semi_FIFOF::*;
   9         import AXI4Lite_AXI4_Bridge::*;
  10         import slow_memory_map::*;
  11         `include "instance_defines.bsv"
  12     /* ==== define the number of slow peripheral irqs ==== */
  13 {11}
  14         /*===========================*/
  15         /*=== package imports ===*/
  16         import Clocks::*;
  17         import ifc_sync:: *;
  18         import GetPut::*;
  19         import ClientServer::*;
  20         import Connectable::*;
  21         import Vector::*;
  22         import FIFO::*;
  23         /*=======================*/
  24         /*===== Import the slow peripherals ====*/
  25 {0}
  26     `ifdef CLINT
  27         import clint::*;
  28     `endif
  29     `ifdef PLIC
  30         import plic             ::*;
  31     `endif
  32         `ifdef AXIEXP
  33                 import axiexpansion     ::*;
  34         `endif
  35         /*=====================================*/
  36
  37         /*===== interface declaration =====*/
  38         interface SP_dedicated_ios;
  39                 `ifdef AXIEXP
  40                         interface Get#(Bit#(67)) axiexp1_out;
  41                         interface Put#(Bit#(67)) axiexp1_in;
  42                 `endif
  43         endinterface
  44         interface Ifc_slow_peripherals;
  45                 interface AXI4_Slave_IFC#(`PADDR,`DATA,`USERSPACE) axi_slave;
  46                 interface SP_dedicated_ios slow_ios;
  47                 `ifdef CLINT
  48                         method Bit#(1) msip_int;
  49                         method Bit#(1) mtip_int;
  50                         method Bit#(`DATA) mtime;
  51                 `endif
  52                 `ifdef PLIC method ActionValue#(Tuple2#(Bool,Bool)) intrpt_note;
  53         `endif
  54         interface IOCellSide iocell_side; // mandatory interface
  55         `ifdef PLIC
  56 {1}
  57         `endif
  58         endinterface
  59         /*================================*/
  60
  61         (*synthesize*)
  62         module mkslow_peripherals#(Clock fast_clock, Reset fast_reset,
  63                                Clock uart_clock, Reset uart_reset
  64                               `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif
  65                               )(Ifc_slow_peripherals);
  66                 Clock sp_clock <-exposeCurrentClock; // slow peripheral clock
  67                 Reset sp_reset <-exposeCurrentReset; // slow peripheral reset
  68
  69                 /*======= Module declarations for each peripheral =======*/
  70 {5}
  71                 `ifdef CLINT
  72                         Ifc_clint       clint <- mkclint();
  73                 `endif
  74                 `ifdef PLIC
  75                         Ifc_PLIC_AXI    plic <- mkplicperipheral();
  76             Wire#(Bit#(TLog#(`INTERRUPT_PINS))) interrupt_id <- mkWire();
  77             Vector#(`INTERRUPT_PINS, FIFO#(bit))
  78                             ff_gateway_queue <- replicateM(mkFIFO);
  79                 `endif
  80                 `ifdef AXIEXP
  81                         Ifc_AxiExpansion axiexp1 <- mkAxiExpansion();
  82                 `endif
  83         Ifc_pinmux pinmux <- mkpinmux; // mandatory
  84 {14}
  85
  86                 /*=======================================================*/
  87
  88             AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `PADDR, `DATA,`USERSPACE)
  89                 slow_fabric <- mkAXI4_Lite_Fabric(fn_slow_address_mapping);
  90                 Ifc_AXI4Lite_AXI4_Bridge
  91                 bridge<-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset);
  92
  93                 mkConnection (bridge.axi4_lite_master, slow_fabric.v_from_masters [0]);
  94                 /*======= Slave connections to AXI4Lite fabric =========*/
  95 {6}
  96                 `ifdef CLINT
  97                         mkConnection (slow_fabric.v_to_slaves
  98                     [fromInteger(valueOf(CLINT_slave_num))],
  99                     clint.axi4_slave);
 100                 `endif
 101                 `ifdef PLIC
 102                         mkConnection (slow_fabric.v_to_slaves
 103                     [fromInteger(valueOf(Plic_slave_num))],
 104                     plic.axi4_slave_plic); //
 105                 `endif
 106                 `ifdef AXIEXP
 107                 mkConnection (slow_fabric.v_to_slaves
 108                     [fromInteger(valueOf(AxiExp1_slave_num))],
 109                     axiexp1.axi_slave); //
 110                 `endif
 111
 112     /*========== pinmux connections ============*/
 113 {7}
 114 {8}
 115
 116     /*=================== PLIC Connections ==================== */
 117 `ifdef PLIC
 118 {10}
 119
 120     rule rl_completion_msg_from_plic;
 121           let id <- plic.intrpt_completion;
 122       interrupt_id <= id;
 123       `ifdef verbose
 124         $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id);
 125        `endif
 126         endrule
 127
 128     for(Integer i=0; i <`INTERRUPT_PINS; i=i+1) begin
 129             rule deq_gateway_queue;
 130                     if(interrupt_id==fromInteger(i)) begin
 131                             ff_gateway_queue[i].deq;
 132           `ifdef verbose
 133             $display($time,"Dequeing the Interrupt request for ID: %d",i);
 134           `endif
 135         end
 136       endrule
 137     end
 138     /*TODO DMA interrupt need to be connected to the plic */
 139     for(Integer i=1; i<8; i=i+1) begin
 140       rule rl_connect_dma_interrupts_to_plic;
 141        `ifdef DMA
 142             if(dma.interrupt_to_processor[i-1]==1'b1) begin
 143                 ff_gateway_queue[i].enq(1);
 144                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 145             end
 146         `else
 147             ff_gateway_queue[i].enq(0);
 148         `endif
 149       endrule
 150     end
 151
 152 `endif // end PLIC
 153         /*======================================================= */
 154
 155                 /* ===== interface definition =======*/
 156                 interface axi_slave=bridge.axi_slave;
 157                 `ifdef PLIC method intrpt_note = plic.intrpt_note; `endif
 158                 `ifdef CLINT
 159                         method msip_int=clint.msip_int;
 160                         method mtip_int=clint.mtip_int;
 161                         method mtime=clint.mtime;
 162                 `endif
 163 `ifdef PLIC
 164 {12}
 165 `endif // end PLIC
 166                 interface SP_dedicated_ios slow_ios;
 167         /* template for dedicated peripherals
 168                         `ifdef UART0
 169                                 interface uart0_coe=uart0.coe_rs232;
 170                         `endif
 171                         `ifdef UART1
 172                                 interface uart1_coe=uart1.coe_rs232;
 173                         `endif
 174                         `ifdef I2C0
 175                                 interface i2c0_out=i2c0.out;
 176                         `endif
 177                         `ifdef I2C1
 178                                 interface i2c1_out=i2c1.out;
 179                         `endif
 180                         `ifdef QSPI0
 181                                 interface qspi0_out = qspi0.out;
 182                         `endif
 183                         `ifdef QSPI1
 184                                 interface qspi1_out = qspi1.out;
 185                         `endif
 186                         `ifdef AXIEXP
 187                                 interface axiexp1_out=axiexp1.slave_out;
 188                                 interface axiexp1_in=axiexp1.slave_in;
 189                         `endif
 190             `ifdef PWM_AXI4Lite
 191                 interface pwm_o = pwm_bus.pwm_io;
 192             `endif
 193        */
 194                 endinterface
 195         interface iocell_side=pinmux.iocell_side;
 196 {9}
 197 {13}
 198                 /*===================================*/
 199         endmodule
 200 endpackage