src/bsv/bsv_lib/soc_template.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions
   7 are met:
   8
   9 *  Redistributions of source code must retain the above copyright notice,
  10    this list of conditions and the following disclaimer.
  11 *  Redistributions in binary form must reproduce the above copyright
  12    notice, this list of conditions and the following disclaimer in the
  13    documentation and/or other materials provided with the distribution.
  14 *  Neither the name of IIT Madras  nor the names of its contributors
  15    may be used to endorse or promote products derived from this software
  16    without specific prior written permission.
  17
  18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  20 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  21 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  22 HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
  24 TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  25 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  26 LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  27 NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29 -------------------------------------------------------------------
  30 */
  31 package socgen;
  32     /*====== Package imports === */
  33     import FIFO::*;
  34     import FIFOF::*;
  35     import SpecialFIFOs::*;
  36     import GetPut::*;
  37     import ClientServer::*;
  38     import Vector::*;
  39     import Connectable::*;
  40     import Clocks::*;
  41
  42     /*=== Project imports === */
  43     import ifc_sync:: *;
  44     import ConcatReg::*;
  45     import AXI4_Types::*;
  46     import AXI4_Fabric::*;
  47     import defined_types::*;
  48     import MemoryMap             :: *;
  49     import slow_peripherals::*;
  50     import fast_memory_map::*;
  51     import slow_memory_map::*;
  52 `ifdef DEBUG
  53     `include "defines.bsv"
  54 `endif
  55     `include "instance_defines.bsv"
  56     `include "core_parameters.bsv"
  57 {8}
  58
  59     `ifdef DMA
  60         import DMA                               :: *;
  61     `endif
  62     `ifdef BOOTROM
  63         import BootRom                  ::*;
  64     `endif
  65     `ifdef SDRAM
  66         import sdr_top                   :: *;
  67     `endif
  68     `ifdef BRAM
  69         import Memory_AXI4      ::*;
  70     `endif
  71     `ifdef TCMemory
  72         import TCM::*;
  73     `endif
  74     `ifdef Debug
  75         import DebugModule::*;
  76     `else
  77         import core::*;
  78     `endif
  79     `ifdef  VME
  80         import vme_top ::*;
  81     `endif
  82
  83     `ifdef VME
  84         import vme_master::*;
  85     `endif
  86     `ifdef FlexBus
  87         import FlexBus_Types::*;
  88     `endif
  89 {0}
  90
  91     /*========================= */
  92     interface Ifc_Soc;
  93         interface SP_dedicated_ios slow_ios;
  94         interface IOCellSide iocell_side;
  95         (*always_ready,always_enabled*)
  96         method Action boot_sequence(Bit#(1) bootseq);
  97
  98         `ifdef SDRAM
  99             (*always_ready*) interface Ifc_sdram_out sdram_out;
 100         `endif
 101         `ifdef DDR
 102             (*prefix="M_AXI"*) interface
 103                    AXI4_Master_IFC#(`PADDR, `DATA, `USERSPACE) master;
 104         `endif
 105         `ifdef HYPER
 106              (*always_ready,always_enabled*)
 107              interface Ifc_flash ifc_flash;
 108         `endif
 109         /*=============================================== */
 110         `ifdef VME
 111              interface Vme_out  proc_ifc;
 112              interface Data_bus_inf proc_dbus;
 113         `endif
 114 {1}
 115     endinterface
 116
 117     //============ mkSoc module =================
 118
 119     (*synthesize*)
 120     module mkSoc #(Bit#(`VADDR) reset_vector,
 121                  Clock slow_clock, Reset slow_reset, Clock uart_clock,
 122                  Reset uart_reset, Clock clk0, Clock tck, Reset trst
 123                  `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
 124         Clock core_clock <-exposeCurrentClock; // slow peripheral clock
 125         Reset core_reset <-exposeCurrentReset; // slow peripheral reset
 126 {2}
 127         `ifdef Debug
 128             Ifc_DebugModule core<-mkDebugModule(reset_vector);
 129         `else
 130             Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
 131         `endif
 132         `ifdef BOOTROM
 133             BootRom_IFC bootrom <-mkBootRom;
 134         `endif
 135         `ifdef SDRAM
 136             Ifc_sdr_slave sdram<- mksdr_axi4_slave(clk0);
 137         `endif
 138         `ifdef BRAM
 139             Memory_IFC#(`SDRAMMemBase,`Addr_space)main_memory <-
 140                         mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
 141         `endif
 142         `ifdef TCMemory
 143             Ifc_TCM                                     tcm                             <- mkTCM;
 144         `endif
 145         `ifdef DMA
 146             DmaC#(7,`NUM_DMACHANNELS) dma       <- mkDMA();
 147         `endif
 148             `ifdef VME
 149             Ifc_vme_top             vme             <-mkvme_top();
 150             `endif
 151         Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
 152                           core_clock, core_reset,
 153                           uart_clock, uart_reset,
 154                           clocked_by slow_clock, reset_by slow_reset
 155                           `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
 156
 157         // clock sync mkConnections
 158 {12}
 159
 160         // Fabric
 161         AXI4_Fabric_IFC #(Num_Masters, Num_Fast_Slaves,
 162                           `PADDR, `DATA,`USERSPACE)
 163                         fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
 164
 165         // Connect traffic generators to fabric
 166         mkConnection (core.dmem_master,fabric.v_from_masters
 167                               [fromInteger(valueOf(Dmem_master_num))]);
 168         mkConnection (core.imem_master, fabric.v_from_masters
 169                               [fromInteger(valueOf(Imem_master_num))]);
 170         `ifdef Debug
 171             mkConnection (core.debug_master, fabric.v_from_masters
 172                               [fromInteger(valueOf(Debug_master_num))]);
 173         `endif
 174         `ifdef DMA
 175          mkConnection (dma.mmu, fabric.v_from_masters
 176                               [fromInteger(valueOf(DMA_master_num))]);
 177         `endif
 178
 179
 180         // Connect fabric to memory slaves
 181             `ifdef Debug
 182                 mkConnection (fabric.v_to_slaves
 183                               [fromInteger(valueOf(Debug_slave_num))],
 184                               core.debug_slave);
 185             `endif
 186             `ifdef SDRAM
 187                 mkConnection (fabric.v_to_slaves
 188                               [fromInteger(valueOf(Sdram_slave_num))],
 189                               sdram.axi4_slave_sdram); //
 190             mkConnection (fabric.v_to_slaves
 191                               [fromInteger(valueOf(Sdram_cfg_slave_num))],
 192                               sdram.axi4_slave_cntrl_reg); //
 193       `endif
 194       `ifdef BRAM
 195                 mkConnection(fabric.v_to_slaves
 196                               [fromInteger(valueOf(Sdram_slave_num))],
 197                               main_memory.axi_slave);
 198             `endif
 199             `ifdef BOOTROM
 200                 mkConnection (fabric.v_to_slaves
 201                               [fromInteger(valueOf(BootRom_slave_num))],
 202                               bootrom.axi_slave);
 203             `endif
 204             `ifdef DMA
 205             mkConnection (fabric.v_to_slaves
 206                               [fromInteger(valueOf(Dma_slave_num))],
 207                               dma.cfg); //DMA slave
 208             `endif
 209             `ifdef TCMemory
 210                 mkConnection (fabric.v_to_slaves
 211                               [fromInteger(valueOf(TCM_slave_num))],
 212                               tcm.axi_slave);
 213             `endif
 214             mkConnection(fabric.v_to_slaves
 215                               [fromInteger(valueOf(SlowPeripheral_slave_num))],
 216                               slow_peripherals.axi_slave);
 217             `ifdef VME
 218                 mkConnection (fabric.v_to_slaves
 219                               [fromInteger(valueOf(VME_slave_num))],
 220                               vme.slave_axi_vme);
 221             `endif
 222
 223 //          pin connections
 224 {9}
 225
 226             // fabric connections
 227 {5}
 228
 229             `ifdef DMA
 230             // rule to connect all interrupt lines to the DMA
 231             // All the interrupt lines to DMA are active
 232             // HIGH. For peripherals that are not connected,
 233             // or those which do not
 234             // generate an interrupt (like TCM), drive a constant 1
 235             // on the corresponding interrupt line.
 236 {7}
 237             `endif
 238
 239
 240         /*==== Synchornization between the JTAG and the Debug Module ===== */
 241         `ifdef Debug
 242             SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-
 243                                         mkSyncFIFOToCC(1,tck,trst);
 244             SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-
 245                                         mkSyncFIFOFromCC(1,tck);
 246             rule connect_tap_request_to_syncfifo;
 247                 let x<-tap.request_to_dm;
 248                 sync_request_to_dm.enq(x);
 249             endrule
 250             rule read_synced_request_to_dm;
 251                 sync_request_to_dm.deq;
 252                 core.request_from_dtm(sync_request_to_dm.first);
 253             endrule
 254
 255             rule connect_debug_response_to_syncfifo;
 256                 let x<-core.response_to_dtm;
 257                 sync_response_from_dm.enq(x);
 258             endrule
 259             rule read_synced_response_from_dm;
 260                 sync_response_from_dm.deq;
 261                 tap.response_from_dm(sync_response_from_dm.first);
 262             endrule
 263         `endif
 264         /*============================================================ */
 265
 266         `ifdef FlexBus
 267             //rule drive_flexbus_inputs;
 268                //flexbus.flexbus_side.m_TAn(1'b1);
 269                //flexbus.flexbus_side.m_din(32'haaaaaaaa);
 270             //endrule
 271          `endif
 272
 273         `ifdef CLINT
 274             SyncBitIfc#(Bit#(1)) clint_mtip_int <-
 275                                         mkSyncBitToCC(slow_clock,slow_reset);
 276             SyncBitIfc#(Bit#(1)) clint_msip_int <-
 277                                         mkSyncBitToCC(slow_clock,slow_reset);
 278             Reg#(Bit#(`DATA)) clint_mtime_value <-
 279                                         mkSyncRegToCC(0,slow_clock,slow_reset);
 280             rule synchronize_clint_data;
 281                 clint_mtip_int.send(slow_peripherals.mtip_int);
 282                 clint_msip_int.send(slow_peripherals.msip_int);
 283                 clint_mtime_value<=slow_peripherals.mtime;
 284             endrule
 285             rule connect_msip_mtip_from_clint;
 286                 core.clint_msip(clint_msip_int.read);
 287                 core.clint_mtip(clint_mtip_int.read);
 288             core.clint_mtime(clint_mtime_value);
 289             endrule
 290         `endif
 291         `ifdef PLIC
 292             Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-
 293                                         mkSyncRegToCC(tuple2(False,False),
 294                                                       slow_clock,slow_reset);
 295             rule synchronize_interrupts;
 296                 let note <- slow_peripherals.intrpt_note;
 297                 plic_interrupt_note<=note;
 298             endrule
 299             rule rl_send_external_interrupt_to_csr;
 300                 core.set_external_interrupt(plic_interrupt_note);
 301             endrule
 302         `endif
 303
 304         `ifdef VME
 305             interface  proc_ifc = vme.proc_ifc;
 306             interface   proc_dbus = vme.proc_dbus;
 307         `endif
 308          method Action boot_sequence(Bit#(1) bootseq) =
 309                             core.boot_sequence(bootseq);
 310         `ifdef SDRAM
 311             interface sdram_out=sdram.ifc_sdram_out;
 312         `endif
 313         `ifdef DDR
 314           interface master=fabric.v_to_slaves
 315                                 [fromInteger(valueOf(Sdram_slave_num))];
 316         `endif
 317         interface slow_ios = slow_peripherals.slow_ios;
 318         interface iocell_side = slow_peripherals.iocell_side;
 319
 320 {6}
 321     endmodule
 322 endpackage