7 if isinstance(txt
, str):
12 line
= line
.split('\n')
17 res
.append(indent
+ line
)
24 def __init__(self
, name
):
27 def extifdecl(self
, name
, count
):
28 sname
= self
.get_iname(count
)
29 return "interface PeripheralSide%s %s;" % (name
.upper(), sname
)
31 def has_axi_master(self
):
37 def mk_dma_irq(self
, name
, count
):
38 if not self
.irq_name():
40 sname
= self
.get_iname(count
)
41 return "{0}_interrupt".format(sname
)
43 def mk_dma_rule(self
, name
, count
):
44 irqname
= self
.mk_dma_irq(name
, count
)
47 pirqname
= self
.irq_name().format(count
)
48 template
= " {0}.send(\n" + \
49 " slow_peripherals.{1});"
50 return template
.format(irqname
, pirqname
)
52 def get_clock_reset(self
, name
, count
):
53 return "slow_clock,slow_reset"
55 def mk_dma_sync(self
, name
, count
):
56 irqname
= self
.mk_dma_irq(name
, count
)
59 sname
= self
.peripheral
.iname().format(count
)
60 template
= "SyncBitIfc#(Bit#(1)) {0} <-\n" + \
61 " <-mkSyncBitToCC({1});"
62 return template
.format(irqname
, self
.get_clock_reset(name
, count
))
64 def mk_dma_connect(self
, name
, count
):
65 irqname
= self
.mk_dma_irq(name
, count
)
68 return "{0}.read".format(irqname
)
70 def fastifdecl(self
, name
, count
):
73 def slowifdeclmux(self
, name
, count
):
79 def num_axi_regs32(self
):
85 def get_iname(self
, inum
):
86 return "{0}{1}".format(self
.name
, self
.mksuffix(self
.name
, inum
))
88 def axibase(self
, name
, ifacenum
):
90 return "%(name)s%(ifacenum)dBase" % locals()
92 def axiend(self
, name
, ifacenum
):
94 return "%(name)s%(ifacenum)dEnd" % locals()
96 def axi_reg_def(self
, start
, name
, ifacenum
):
98 offs
= self
.num_axi_regs32() * 4 * 16
101 end
= start
+ offs
- 1
102 bname
= self
.axibase(name
, ifacenum
)
103 bend
= self
.axiend(name
, ifacenum
)
104 comment
= "%d 32-bit regs" % self
.num_axi_regs32()
105 return (" `define %(bname)s 'h%(start)08X\n"
106 " `define %(bend)s 'h%(end)08X // %(comment)s" % locals(),
109 def axi_master_name(self
, name
, ifacenum
, typ
=''):
111 return "{0}{1}_master_num".format(name
, ifacenum
)
113 def axi_slave_name(self
, name
, ifacenum
, typ
=''):
115 return "{0}{1}_{2}slave_num".format(name
, ifacenum
, typ
)
117 def axi_master_idx(self
, idx
, name
, ifacenum
, typ
):
118 name
= self
.axi_master_name(name
, ifacenum
, typ
)
119 return ("typedef {0} {1};".format(idx
, name
), 1)
121 def axi_slave_idx(self
, idx
, name
, ifacenum
, typ
):
122 name
= self
.axi_slave_name(name
, ifacenum
, typ
)
123 return ("typedef {0} {1};".format(idx
, name
), 1)
125 def axi_fastaddr_map(self
, name
, ifacenum
):
126 return self
.axi_addr_map(name
, ifacenum
, 'fast')
128 def axi_addr_map(self
, name
, ifacenum
, typ
=""):
129 bname
= self
.axibase(name
, ifacenum
)
130 bend
= self
.axiend(name
, ifacenum
)
131 name
= self
.axi_slave_name(name
, ifacenum
, typ
)
133 if(addr>=`{0} && addr<=`{1})
134 return tuple2(True,fromInteger(valueOf({2})));
136 return template
.format(bname
, bend
, name
)
138 def _mk_pincon(self
, name
, count
, ptyp
):
139 # TODO: really should be using bsv.interface_decl.Interfaces
140 # pin-naming rules.... logic here is hard-coded to duplicate
141 # it (see Interface.__init__ outen)
143 for p
in self
.peripheral
.pinspecs
:
146 #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
147 n
= name
# "{0}{1}".format(self.name, self.mksuffix(name, count))
148 ret
.append("//%s %s" % (n
, str(p
)))
150 sname
= self
.get_iname(count
)
151 sname
= "{0}.{1}".format(sname
, pname
)
152 ps
= "slow_peripherals.%s" % sname
154 sname
= self
.peripheral
.iname().format(count
)
155 sname
= "{0}.{1}".format(sname
, pname
)
156 ps
= "pinmux.peripheral_side.%s" % sname
157 if typ
== 'out' or typ
== 'inout':
158 fname
= self
.pinname_out(pname
)
159 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
160 n_
= "{0}{1}".format(n
, count
)
168 cn
= self
._mk
_actual
_connection
('out', name
,
170 pname
, ps_
, n_
, fname
)
174 fname
= self
.pinname_outen(pname
)
176 if isinstance(fname
, str):
177 fname
= "{0}.{1}".format(n_
, fname
)
178 fname
= self
.pinname_tweak(pname
, 'outen', fname
)
179 cn
= self
._mk
_actual
_connection
('outen', name
,
183 if typ
== 'in' or typ
== 'inout':
184 fname
= self
.pinname_in(pname
)
190 n_
= "{0}{1}".format(n
, count
)
191 n_
= '{0}.{1}'.format(n_
, fname
)
192 n_
= self
.ifname_tweak(pname
, 'in', n_
)
193 cn
= self
._mk
_actual
_connection
('in', name
,
195 pname
, ps_
, n_
, fname
)
197 return '\n'.join(ret
)
199 def _mk_vpincon(self
, name
, count
, ptyp
, typ
, pname
):
202 sname
= self
.get_iname(count
)
203 ps
= "slow_peripherals.%s" % sname
205 sname
= self
.peripheral
.iname().format(count
)
206 ps
= "pinmux.peripheral_side.%s" % sname
207 n
= self
.get_iname(count
)
208 ps_
= "{0}.{1}".format(ps
, pname
)
209 ret
+= self
._mk
_actual
_connection
(typ
, name
, count
, typ
,
210 pname
, ps_
, n
, pname
)
211 return '\n'.join(ret
)
213 def _mk_actual_connection(self
, ctype
, name
, count
, typ
,
214 pname
, ps
, n
, fname
):
216 ck
= self
.get_clock_reset(name
, count
)
218 if ck
== PBase
.get_clock_reset(self
, name
, count
):
219 ret
.append("mkConnection({0},\n\t\t\t{1}.{2});"
220 .format(ps
, n
, fname
))
222 n2
= "{0}{1}".format(name
, count
)
223 sync
= '{0}_{1}_sync'.format(n2
, pname
)
224 ret
.append("mkConnection({0},\n\t\t\t{1}.get);"
226 ret
.append("mkConnection({0}.put,\n\t\t\t{1}.{2});"
227 .format(sync
, n
, fname
))
228 elif ctype
== 'outen':
229 ret
.append("mkConnection({0}_outen,\n\t\t\t{1});"
232 if ck
== PBase
.get_clock_reset(self
, name
, count
):
233 ret
.append("mkConnection({1},\n\t\t\t{0});".format(
236 n2
= "{0}{1}".format(name
, count
)
237 sync
= '{0}_{1}_sync'.format(n2
, pname
)
238 ret
.append("mkConnection({1}.put,\n\t\t\t{0});".format(
240 ret
.append("mkConnection({1},\n\t\t\t{0}.get);".format(
245 def _mk_clk_con(self
, name
, count
, ctype
):
247 ck
= self
.get_clock_reset(name
, count
)
248 if ck
== PBase
.get_clock_reset(self
, name
, count
):
251 spc
= "sp_clock, sp_reset"
254 ck
= "core_clock, core_reset"
256 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
258 for p
in self
.peripheral
.pinspecs
:
262 if typ
== 'out' or typ
== 'inout':
263 fname
= self
.pinname_out(pname
)
266 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
267 n_
= "{0}{1}".format(n
, count
)
270 n_
= '{0}_{1}'.format(n_
, pname
)
271 ret
.append(template
.format("Bit#(1)", n_
, ck
, spc
))
272 if typ
== 'in' or typ
== 'inout':
273 fname
= self
.pinname_in(pname
)
276 #fname = self.pinname_in(pname)
277 n_
= "{0}{1}".format(n
, count
)
278 n_
= '{0}_{1}'.format(n_
, pname
)
279 #n_ = self.ifname_tweak(pname, 'in', n_)
280 ret
.append(template
.format("Bit#(1)", n_
, spc
, ck
))
281 return '\n'.join(ret
)
283 def _mk_clk_vcon(self
, name
, count
, ctype
, typ
, pname
, bitspec
):
284 ck
= self
.get_clock_reset(name
, count
)
285 if ck
== PBase
.get_clock_reset(self
, name
, count
):
288 spc
= "sp_clock, sp_reset"
291 ck
= "core_clock, core_reset"
293 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
296 n_
= "{0}{1}".format(name
, count
)
297 n_
= '{0}_{1}'.format(n_
, pname
)
298 return template
.format(bitspec
, n_
, ck
, spc
)
301 def mk_cellconn(self
, *args
):
304 def mkfast_peripheral(self
, size
=0):
307 def mkslow_peripheral(self
, size
=0):
310 def mksuffix(self
, name
, i
):
313 def __mk_connection(self
, con
, aname
, fabricname
):
314 txt
= "mkConnection ({2}.v_to_slaves\n" + \
315 " [fromInteger(valueOf({1}))],\n" + \
318 print "PBase __mk_connection", self
.name
, aname
321 return txt
.format(con
, aname
, fabricname
)
323 def __mk_master_connection(self
, con
, aname
):
324 txt
= "mkConnection (slow_fabric.v_to_slaves\n" + \
325 " [fromInteger(valueOf({1}))],\n" + \
328 print "PBase __mk_connection", self
.name
, aname
331 return txt
.format(con
, aname
)
333 def mk_connection(self
, count
, fabricname
, typ
, name
=None):
336 print "PBase mk_conn", self
.name
, count
337 aname
= self
.axi_slave_name(name
, count
, typ
)
338 #dname = self.mksuffix(name, count)
339 #dname = "{0}{1}".format(name, dname)
340 con
= self
._mk
_connection
(name
, count
).format(count
, aname
)
341 return self
.__mk
_connection
(con
, aname
, fabricname
)
343 def _mk_connection(self
, name
=None, count
=0):
346 def pinname_out(self
, pname
):
349 def pinname_in(self
, pname
):
352 def pinname_outen(self
, pname
):
355 def ifname_tweak(self
, pname
, typ
, txt
):
358 def pinname_tweak(self
, pname
, typ
, txt
):
364 def mk_plic(self
, inum
, irq_offs
):
366 print "mk_plic", self
.name
, inum
, irq_offs
367 niq
= self
.num_irqs()
369 return ('', irq_offs
)
370 name
= self
.get_iname(inum
)
371 res
.append("// PLIC rules for {0}".format(name
))
372 for idx
in range(niq
):
373 plic_obj
= self
.plic_object(name
, idx
)
374 print "plic_obj", name
, idx
, plic_obj
375 plic
= mkplic_rule
.format(name
, plic_obj
, irq_offs
)
377 irq_offs
+= 1 # increment to next irq
378 return ('\n'.join(res
), irq_offs
)
380 def mk_ext_ifacedef(self
, iname
, inum
):
383 def extfastifinstance(self
, name
, count
):
386 def _extifinstance(self
, name
, count
, suffix
, prefix
, samename
=False,
390 pname
= self
.get_iname(count
)
394 sname
= self
.peripheral
.iname().format(count
)
395 template
= "interface {0}{3} = {2}{1}{4};"
396 return template
.format(pname
, sname
, prefix
, suffix
, ifsuffix
)
398 def extifinstance2(self
, name
, count
):
401 def extifinstance(self
, name
, count
):
402 return self
._extifinstance
(name
, count
, "",
403 "pinmux.peripheral_side.")
407 rule rl_connect_{0}_to_plic_{2};
408 if({1} == 1'b1) begin
409 ff_gateway_queue[{2}].enq(1);
410 plic.ifc_external_irq[{2}].irq_frm_gateway(True);
415 axi_master_declarations
= """\
416 typedef 0 Dmem_master_num;
417 typedef 1 Imem_master_num;
419 typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif )
421 typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif )
423 typedef TAdd#(DMA_master_num,1)
427 axi_fastslave_declarations
= """\
429 typedef TAdd#(LastGen_fastslave_num,1) Sdram_slave_num;
430 typedef TAdd#(Sdram_slave_num ,`ifdef SDRAM 1 `else 0 `endif )
432 typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM 1 `else 0 `endif )
434 typedef TAdd#(BootRom_slave_num ,`ifdef Debug 1 `else 0 `endif )
436 typedef TAdd#(Debug_slave_num , `ifdef TCMemory 1 `else 0 `endif )
438 typedef TAdd#(TCM_slave_num ,`ifdef DMA 1 `else 0 `endif )
440 typedef TAdd#(Dma_slave_num ,1 ) SlowPeripheral_slave_num;
441 typedef TAdd#(SlowPeripheral_slave_num,`ifdef VME 1 `else 0 `endif )
443 typedef TAdd#(VME_slave_num,1) Num_Fast_Slaves;
446 axi_slave_declarations
= """\
447 typedef 0 SlowMaster;
449 typedef TAdd#(LastGen_slave_num,`ifdef CLINT 1 `else 0 `endif )
451 typedef TAdd#(CLINT_slave_num ,`ifdef PLIC 1 `else 0 `endif )
453 typedef TAdd#(Plic_slave_num ,`ifdef AXIEXP 1 `else 0 `endif )
455 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
458 pinmux_cellrule
= """\
459 rule connect_select_lines_pinmux;
465 class CallFn(object):
466 def __init__(self
, peripheral
, name
):
467 self
.peripheral
= peripheral
470 def __call__(self
, *args
):
471 #print "__call__", self.name, self.peripheral.slow, args
472 if not self
.peripheral
.slow
:
474 return getattr(self
.peripheral
.slow
, self
.name
)(*args
[1:])
477 class PeripheralIface(object):
478 def __init__(self
, ifacename
):
480 slow
= slowfactory
.getcls(ifacename
)
481 print "Iface", ifacename
, slow
483 self
.slow
= slow(ifacename
)
484 self
.slow
.peripheral
= self
485 for fname
in ['slowimport',
487 'extifinstance2', 'extifinstance', 'extifdecl',
488 'slowifdecl', 'slowifdeclmux',
491 'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule',
493 'mk_plic', 'mk_ext_ifacedef',
494 '_mk_clk_con', 'mk_ext_ifacedef',
495 'mk_connection', 'mk_cellconn', '_mk_pincon']:
496 fn
= CallFn(self
, fname
)
497 setattr(self
, fname
, types
.MethodType(fn
, self
))
499 #print "PeripheralIface"
502 def mksuffix(self
, name
, i
):
503 if self
.slow
is None:
505 return self
.slow
.mksuffix(name
, i
)
507 def axi_reg_def(self
, start
, count
):
510 return self
.slow
.axi_reg_def(start
, self
.ifacename
, count
)
512 def axi_master_idx(self
, start
, count
, typ
):
513 if not self
.slow
or not self
.slow
.has_axi_master():
515 return self
.slow
.axi_master_idx(start
, self
.ifacename
, count
, typ
)
517 def axi_slave_idx(self
, start
, count
, typ
):
520 return self
.slow
.axi_slave_idx(start
, self
.ifacename
, count
, typ
)
522 def axi_fastaddr_map(self
, count
):
525 return self
.slow
.axi_fastaddr_map(self
.ifacename
, count
)
527 def axi_addr_map(self
, count
):
530 return self
.slow
.axi_addr_map(self
.ifacename
, count
)
533 class PeripheralInterfaces(object):
535 self
.fastbusmode
= False
537 def slowimport(self
, *args
):
539 for (name
, count
) in self
.ifacecount
:
540 #print "slowimport", name, self.data[name].slowimport
541 ret
.append(self
.data
[name
].slowimport())
542 return '\n'.join(li(list(filter(None, ret
)), 4))
544 def extfastifinstance(self
, *args
):
546 for (name
, count
) in self
.ifacecount
:
547 for i
in range(count
):
548 iname
= self
.data
[name
].iname().format(i
)
549 print "extfast", iname
, self
.is_on_fastbus(name
, i
)
550 if self
.is_on_fastbus(name
, i
):
552 ret
.append(self
.data
[name
].extfastifinstance(name
, i
))
553 return '\n'.join(li(list(filter(None, ret
)), 8))
555 def extifinstance2(self
, *args
):
557 for (name
, count
) in self
.ifacecount
:
558 for i
in range(count
):
559 iname
= self
.data
[name
].iname().format(i
)
560 ret
.append(self
.data
[name
].extifinstance2(name
, i
))
561 return '\n'.join(li(list(filter(None, ret
)), 8))
563 def extifinstance(self
, *args
):
565 for (name
, count
) in self
.ifacecount
:
566 for i
in range(count
):
567 iname
= self
.data
[name
].iname().format(i
)
568 if not self
.is_on_fastbus(name
, i
):
570 ret
.append(self
.data
[name
].extifinstance(name
, i
))
571 return '\n'.join(li(list(filter(None, ret
)), 8))
573 def extifdecl(self
, *args
):
575 for (name
, count
) in self
.ifacecount
:
576 for i
in range(count
):
577 if not self
.is_on_fastbus(name
, i
):
579 ret
.append(self
.data
[name
].extifdecl(name
, i
))
580 return '\n'.join(li(list(filter(None, ret
)), 8))
582 def slowifdeclmux(self
, *args
):
584 for (name
, count
) in self
.ifacecount
:
585 for i
in range(count
):
586 ret
.append(self
.data
[name
].slowifdeclmux(name
, i
))
587 return '\n'.join(li(list(filter(None, ret
)), 8))
589 def fastifdecl(self
, *args
):
591 for (name
, count
) in self
.ifacecount
:
592 for i
in range(count
):
593 print "fastifdecl", name
, i
, self
.is_on_fastbus(name
, i
)
594 if self
.is_on_fastbus(name
, i
):
596 ret
.append(self
.data
[name
].fastifdecl(name
, i
))
597 return '\n'.join(li(list(filter(None, ret
)), 4))
599 def slowifdecl(self
, *args
):
601 for (name
, count
) in self
.ifacecount
:
602 for i
in range(count
):
603 if self
.is_on_fastbus(name
, i
):
605 ret
.append(self
.data
[name
].slowifdecl().format(i
, name
))
606 return '\n'.join(list(filter(None, ret
)))
608 def axi_fastmem_def(self
, *args
):
609 return self
._axi
_reg
_def
(0x50000000, *args
)
611 def axi_reg_def(self
, *args
):
612 return self
._axi
_reg
_def
(0x00011100, *args
)
614 def _axi_reg_def(self
, start
, *args
):
616 for (name
, count
) in self
.ifacecount
:
617 for i
in range(count
):
618 if self
.is_on_fastbus(name
, i
):
620 x
= self
.data
[name
].axi_reg_def(start
, i
)
621 #print ("ifc", name, x)
625 return '\n'.join(list(filter(None, ret
)))
627 def _axi_num_idx(self
, start
, template
, typ
, idxtype
, *args
):
629 for (name
, count
) in self
.ifacecount
:
630 for i
in range(count
):
631 if self
.is_on_fastbus(name
, i
):
634 fn
= self
.data
[name
].axi_master_idx
636 fn
= self
.data
[name
].axi_slave_idx
637 (rdef
, offs
) = fn(start
, i
, idxtype
)
638 #print ("ifc", name, rdef, offs)
641 ret
.append("typedef %d LastGen_%s_num;" % (start
- 1, typ
))
642 decls
= '\n'.join(list(filter(None, ret
)))
643 return template
.format(decls
)
645 def axi_slave_idx(self
, *args
):
646 return self
._axi
_num
_idx
(0, axi_slave_declarations
, 'slave',
649 def axi_fastslave_idx(self
, *args
):
650 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
653 def axi_master_idx(self
, *args
):
654 return self
._axi
_num
_idx
(2, axi_master_declarations
, 'master',
657 def axi_fastslave_idx(self
, *args
):
658 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
661 def axi_fastaddr_map(self
, *args
):
663 for (name
, count
) in self
.ifacecount
:
664 for i
in range(count
):
665 if self
.is_on_fastbus(name
, i
):
667 ret
.append(self
.data
[name
].axi_fastaddr_map(i
))
668 return '\n'.join(li(list(filter(None, ret
)), 8))
670 def axi_addr_map(self
, *args
):
672 for (name
, count
) in self
.ifacecount
:
673 for i
in range(count
):
674 if self
.is_on_fastbus(name
, i
):
676 ret
.append(self
.data
[name
].axi_addr_map(i
))
677 return '\n'.join(li(list(filter(None, ret
)), 8))
679 def mkfast_peripheral(self
, *args
):
681 for (name
, count
) in self
.ifacecount
:
682 for i
in range(count
):
683 if self
.is_on_fastbus(name
, i
):
685 #print "mkfast", name, count
686 x
= self
.data
[name
].mkfast_peripheral()
688 suffix
= self
.data
[name
].mksuffix(name
, i
)
689 ret
.append(x
.format(suffix
))
690 return '\n'.join(li(list(filter(None, ret
)), 8))
692 def mkslow_peripheral(self
, *args
):
694 for (name
, count
) in self
.ifacecount
:
695 for i
in range(count
):
696 if self
.is_on_fastbus(name
, i
):
698 #print "mkslow", name, count
699 x
= self
.data
[name
].mkslow_peripheral()
701 suffix
= self
.data
[name
].mksuffix(name
, i
)
702 ret
.append(x
.format(suffix
))
703 return '\n'.join(li(list(filter(None, ret
)), 8))
705 def mk_fast_connection(self
, *args
):
707 for (name
, count
) in self
.ifacecount
:
708 for i
in range(count
):
709 if self
.is_on_fastbus(name
, i
):
711 txt
= self
.data
[name
].mk_connection(i
, "fabric", "fast")
714 print self
.data
[name
].mk_connection
716 return '\n'.join(li(list(filter(None, ret
)), 12))
718 def mk_connection(self
, *args
):
720 for (name
, count
) in self
.ifacecount
:
721 for i
in range(count
):
722 if self
.is_on_fastbus(name
, i
):
724 txt
= self
.data
[name
].mk_connection(i
, "slow_fabric", "")
727 print self
.data
[name
].mk_connection
729 return '\n'.join(li(list(filter(None, ret
)), 8))
731 def mk_cellconn(self
):
734 for (name
, count
) in self
.ifacecount
:
735 for i
in range(count
):
736 if self
.is_on_fastbus(name
, i
):
738 res
= self
.data
[name
].mk_cellconn(cellcount
, name
, i
)
741 (txt
, cellcount
) = res
743 ret
= li('\n'.join(list(filter(None, ret
))), 4)
744 return li(pinmux_cellrule
.format(ret
), 4)
747 return self
._mk
_pincon
("slow")
749 def mk_fast_pincon(self
):
750 return self
._mk
_pincon
("fast")
752 def _mk_pincon(self
, typ
):
754 for (name
, count
) in self
.ifacecount
:
755 for i
in range(count
):
756 if self
.is_on_fastbus(name
, i
):
758 txt
= self
.data
[name
]._mk
_pincon
(name
, i
, typ
)
760 return '\n'.join(li(list(filter(None, ret
)), 4))
762 def mk_dma_irq(self
):
770 for (name
, count
) in self
.ifacecount
:
772 for i
in range(count
):
773 if not self
.is_on_fastbus(name
, i
):
775 txt
= self
.data
[name
].mk_dma_sync(name
, i
)
779 txt
= self
.data
[name
].mk_dma_rule(name
, i
)
780 ifacerules
.append(txt
)
781 txt
= self
.data
[name
].mk_dma_connect(name
, i
)
783 ifacerules
= list(filter(None, ifacerules
))
785 txt
= "rule synchronize_%s_interrupts;" % name
788 rules
.append("endrule")
790 cnct
= list(filter(None, cnct
))
792 _cnct
= ["rule rl_connect_interrupt_to_DMA;",
793 " Bit #(%d) lv_interrupt_to_DMA={" % ct
]
796 cnct
= _cnct
+ [spc
+ spcsep
.join(cnct
)]
798 cnct
.append(" dma.interrupt_from_peripherals(\n" +
799 " lv_interrupt_to_DMA);")
800 cnct
.append("endrule;")
802 ret
= list(filter(None, sync
+ rules
+ cnct
))
804 return '\n'.join(ret
)
806 def num_dmachannels(self
):
807 return "`define NUM_DMACHANNELS {0}".format(self
.dma_count
)
809 def mk_ext_ifacedef(self
):
811 for (name
, count
) in self
.ifacecount
:
812 for i
in range(count
):
813 if self
.is_on_fastbus(name
, i
):
815 txt
= self
.data
[name
].mk_ext_ifacedef(name
, i
)
817 return '\n'.join(li(list(filter(None, ret
)), 8))
821 irq_offs
= 8 # XXX: DMA scovers 0-7?
822 for (name
, count
) in self
.ifacecount
:
823 for i
in range(count
):
824 if self
.is_on_fastbus(name
, i
):
826 res
= self
.data
[name
].mk_plic(i
, irq_offs
)
829 (txt
, irq_offs
) = res
831 self
.num_slow_irqs
= irq_offs
832 return '\n'.join(li(list(filter(None, ret
)), 4))
834 def mk_sloirqsdef(self
):
835 return " `define NUM_SLOW_IRQS {0}".format(self
.num_slow_irqs
)
837 def mk_fastclk_con(self
):
838 return self
._mk
_clk
_con
("fast")
840 def mk_slowclk_con(self
):
841 return self
._mk
_clk
_con
("slow")
843 def _mk_clk_con(self
, ctype
):
845 for (name
, count
) in self
.ifacecount
:
846 for i
in range(count
):
847 if self
.is_on_fastbus(name
, i
):
849 txt
= self
.data
[name
]._mk
_clk
_con
(name
, i
, ctype
)
851 return '\n'.join(li(list(filter(None, ret
)), 8))
853 def is_on_fastbus(self
, name
, i
):
854 #print "fastbus mode", self.fastbusmode, name, i
855 iname
= self
.data
[name
].iname().format(i
)
857 return iname
not in self
.fastbus
858 return iname
in self
.fastbus
861 class PFactory(object):
862 def getcls(self
, name
):
863 from uart
import uart
864 from quart
import quart
865 from sdmmc
import sdmmc
867 from eint
import eint
868 from rs232
import rs232
870 from eint
import eint
871 from jtag
import jtag
872 from spi
import spi
, mspi
873 from qspi
import qspi
, mqspi
874 from gpio
import gpio
875 from rgbttl
import rgbttl
876 from flexbus
import flexbus
878 for k
, v
in {'uart': uart
,
894 if name
.startswith(k
):
899 slowfactory
= PFactory()
901 if __name__
== '__main__':
905 i
= PeripheralIface('uart')
907 i
= PeripheralIface('gpioa')