7 if isinstance(txt
, str):
12 line
= line
.split('\n')
17 res
.append(indent
+ line
)
24 def __init__(self
, name
):
27 def extifdecl(self
, name
, count
):
28 sname
= self
.get_iname(count
)
29 return "interface PeripheralSide%s %s;" % (name
.upper(), sname
)
31 def has_axi_master(self
):
37 def mk_dma_irq(self
, name
, count
):
38 if not self
.irq_name():
40 sname
= self
.get_iname(count
)
41 return "{0}_interrupt".format(sname
)
43 def mk_dma_rule(self
, name
, count
):
44 irqname
= self
.mk_dma_irq(name
, count
)
47 pirqname
= self
.irq_name().format(count
)
48 template
= " {0}.send(\n" + \
49 " slow_peripherals.{1});"
50 return template
.format(irqname
, pirqname
)
52 def get_clock_reset(self
, name
, count
):
53 return "slow_clock,slow_reset"
55 def mk_dma_sync(self
, name
, count
):
56 irqname
= self
.mk_dma_irq(name
, count
)
59 sname
= self
.peripheral
.iname().format(count
)
60 template
= "SyncBitIfc#(Bit#(1)) {0} <-\n" + \
61 " <-mkSyncBitToCC({1});"
62 return template
.format(irqname
, self
.get_clock_reset(name
, count
))
64 def mk_dma_connect(self
, name
, count
):
65 irqname
= self
.mk_dma_irq(name
, count
)
68 return "{0}.read".format(irqname
)
70 def fastifdecl(self
, name
, count
):
73 def slowifdeclmux(self
, name
, count
):
79 def num_axi_regs32(self
):
85 def get_iname(self
, inum
):
86 return "{0}{1}".format(self
.name
, self
.mksuffix(self
.name
, inum
))
88 def axibase(self
, name
, ifacenum
):
90 return "%(name)s%(ifacenum)dBase" % locals()
92 def axiend(self
, name
, ifacenum
):
94 return "%(name)s%(ifacenum)dEnd" % locals()
96 def axi_reg_def(self
, start
, name
, ifacenum
):
98 offs
= self
.num_axi_regs32() * 4 * 16
101 end
= start
+ offs
- 1
102 bname
= self
.axibase(name
, ifacenum
)
103 bend
= self
.axiend(name
, ifacenum
)
104 comment
= "%d 32-bit regs" % self
.num_axi_regs32()
105 return (" `define %(bname)s 'h%(start)08X\n"
106 " `define %(bend)s 'h%(end)08X // %(comment)s" % locals(),
109 def axi_master_name(self
, name
, ifacenum
, typ
=''):
111 return "{0}{1}_master_num".format(name
, ifacenum
)
113 def axi_slave_name(self
, name
, ifacenum
, typ
=''):
115 return "{0}{1}_{2}slave_num".format(name
, ifacenum
, typ
)
117 def axi_master_idx(self
, idx
, name
, ifacenum
, typ
):
118 name
= self
.axi_master_name(name
, ifacenum
, typ
)
119 return ("typedef {0} {1};".format(idx
, name
), 1)
121 def axi_slave_idx(self
, idx
, name
, ifacenum
, typ
):
122 name
= self
.axi_slave_name(name
, ifacenum
, typ
)
123 return ("typedef {0} {1};".format(idx
, name
), 1)
125 def axi_fastaddr_map(self
, name
, ifacenum
):
126 return self
.axi_addr_map(name
, ifacenum
, 'fast')
128 def axi_addr_map(self
, name
, ifacenum
, typ
=""):
129 bname
= self
.axibase(name
, ifacenum
)
130 bend
= self
.axiend(name
, ifacenum
)
131 name
= self
.axi_slave_name(name
, ifacenum
, typ
)
133 if(addr>=`{0} && addr<=`{1})
134 return tuple2(True,fromInteger(valueOf({2})));
136 return template
.format(bname
, bend
, name
)
138 def _mk_pincon(self
, name
, count
, ptyp
):
139 # TODO: really should be using bsv.interface_decl.Interfaces
140 # pin-naming rules.... logic here is hard-coded to duplicate
141 # it (see Interface.__init__ outen)
143 for p
in self
.peripheral
.pinspecs
:
146 #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
147 n
= name
# "{0}{1}".format(self.name, self.mksuffix(name, count))
148 ret
.append("//%s %s" % (n
, str(p
)))
150 sname
= self
.get_iname(count
)
151 sname
= "{0}.{1}".format(sname
, pname
)
152 ps
= "slow_peripherals.%s" % sname
154 sname
= self
.peripheral
.iname().format(count
)
155 sname
= "{0}.{1}".format(sname
, pname
)
156 ps
= "pinmux.peripheral_side.%s" % sname
157 if typ
== 'out' or typ
== 'inout':
158 fname
= self
.pinname_out(pname
)
159 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
160 n_
= "{0}{1}".format(n
, count
)
168 cn
= self
._mk
_actual
_connection
('out', name
,
170 pname
, ps_
, n_
, fname
)
174 fname
= self
.pinname_outen(pname
)
176 if isinstance(fname
, str):
177 fname
= "{0}.{1}".format(n_
, fname
)
178 fname
= self
.pinname_tweak(pname
, 'outen', fname
)
179 cn
= self
._mk
_actual
_connection
('outen', name
,
183 if typ
== 'in' or typ
== 'inout':
184 fname
= self
.pinname_in(pname
)
190 n_
= "{0}{1}".format(n
, count
)
191 n_
= '{0}.{1}'.format(n_
, fname
)
192 n_
= self
.ifname_tweak(pname
, 'in', n_
)
193 cn
= self
._mk
_actual
_connection
('in', name
,
195 pname
, ps_
, n_
, fname
)
197 return '\n'.join(ret
)
199 def _mk_vpincon(self
, name
, count
, ptyp
, typ
, pname
, stype
=None):
204 sname
= self
.get_iname(count
)
205 ps
= "slow_peripherals.%s" % sname
207 sname
= self
.peripheral
.iname().format(count
)
208 ps
= "pinmux.peripheral_side.%s" % sname
209 n
= self
.get_iname(count
)
210 ps_
= "{0}.{1}".format(ps
, pname
)
211 ret
+= self
._mk
_actual
_connection
(typ
, name
, count
, typ
,
212 pname
, ps_
, n
, stype
)
213 return '\n'.join(ret
)
215 def _mk_actual_connection(self
, ctype
, name
, count
, typ
,
216 pname
, ps
, n
, fname
):
218 ck
= self
.get_clock_reset(name
, count
)
220 if ck
== PBase
.get_clock_reset(self
, name
, count
):
221 ret
.append("mkConnection({0},\n\t\t\t{1}.{2});"
222 .format(ps
, n
, fname
))
224 n2
= "{0}{1}".format(name
, count
)
225 sync
= '{0}_{1}_sync'.format(n2
, pname
)
226 ret
.append("mkConnection({0},\n\t\t\t{1}.get);"
228 ret
.append("mkConnection({0}.put,\n\t\t\t{1}.{2});"
229 .format(sync
, n
, fname
))
230 elif ctype
== 'outen':
231 ret
.append("mkConnection({0}_outen,\n\t\t\t{1});"
234 if ck
== PBase
.get_clock_reset(self
, name
, count
):
235 ret
.append("mkConnection({1},\n\t\t\t{0});".format(
238 n2
= "{0}{1}".format(name
, count
)
239 sync
= '{0}_{1}_sync'.format(n2
, pname
)
240 n
= "{0}.{1}".format(n
, fname
)
241 ret
.append("mkConnection({1}.put,\n\t\t\t{0});".format(
243 ret
.append("mkConnection({1},\n\t\t\t{0}.get);".format(
248 def _mk_clk_con(self
, name
, count
, ctype
):
250 ck
= self
.get_clock_reset(name
, count
)
251 if ck
== PBase
.get_clock_reset(self
, name
, count
):
254 spc
= "sp_clock, sp_reset"
257 ck
= "core_clock, core_reset"
259 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
261 for p
in self
.peripheral
.pinspecs
:
265 if typ
== 'out' or typ
== 'inout':
266 fname
= self
.pinname_out(pname
)
269 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
270 n_
= "{0}{1}".format(n
, count
)
273 n_
= '{0}_{1}'.format(n_
, pname
)
274 ret
.append(template
.format("Bit#(1)", n_
, ck
, spc
))
275 if typ
== 'in' or typ
== 'inout':
276 fname
= self
.pinname_in(pname
)
279 #fname = self.pinname_in(pname)
280 n_
= "{0}{1}".format(n
, count
)
281 n_
= '{0}_{1}'.format(n_
, pname
)
282 #n_ = self.ifname_tweak(pname, 'in', n_)
283 ret
.append(template
.format("Bit#(1)", n_
, spc
, ck
))
284 return '\n'.join(ret
)
286 def _mk_clk_vcon(self
, name
, count
, ctype
, typ
, pname
, bitspec
):
287 ck
= self
.get_clock_reset(name
, count
)
288 if ck
== PBase
.get_clock_reset(self
, name
, count
):
291 spc
= "sp_clock, sp_reset"
294 ck
= "core_clock, core_reset"
296 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
299 n_
= "{0}{1}".format(name
, count
)
300 n_
= '{0}_{1}'.format(n_
, pname
)
301 return template
.format(bitspec
, n_
, ck
, spc
)
304 def mk_cellconn(self
, *args
):
307 def mkfast_peripheral(self
, size
=0):
310 def mkslow_peripheral(self
, size
=0):
313 def mksuffix(self
, name
, i
):
316 def __mk_connection(self
, con
, aname
, fabricname
):
317 txt
= "mkConnection ({2}.v_to_slaves\n" + \
318 " [fromInteger(valueOf({1}))],\n" + \
321 print "PBase __mk_connection", self
.name
, aname
324 return txt
.format(con
, aname
, fabricname
)
326 def __mk_master_connection(self
, con
, aname
):
327 txt
= "mkConnection (slow_fabric.v_to_slaves\n" + \
328 " [fromInteger(valueOf({1}))],\n" + \
331 print "PBase __mk_connection", self
.name
, aname
334 return txt
.format(con
, aname
)
336 def mk_connection(self
, count
, fabricname
, typ
, name
=None):
339 print "PBase mk_conn", self
.name
, count
340 aname
= self
.axi_slave_name(name
, count
, typ
)
341 #dname = self.mksuffix(name, count)
342 #dname = "{0}{1}".format(name, dname)
343 con
= self
._mk
_connection
(name
, count
).format(count
, aname
)
344 return self
.__mk
_connection
(con
, aname
, fabricname
)
346 def _mk_connection(self
, name
=None, count
=0):
349 def pinname_out(self
, pname
):
352 def pinname_in(self
, pname
):
355 def pinname_outen(self
, pname
):
358 def ifname_tweak(self
, pname
, typ
, txt
):
361 def pinname_tweak(self
, pname
, typ
, txt
):
367 def mk_plic(self
, inum
, irq_offs
):
369 print "mk_plic", self
.name
, inum
, irq_offs
370 niq
= self
.num_irqs()
372 return ('', irq_offs
)
373 name
= self
.get_iname(inum
)
374 res
.append("// PLIC rules for {0}".format(name
))
375 for idx
in range(niq
):
376 plic_obj
= self
.plic_object(name
, idx
)
377 print "plic_obj", name
, idx
, plic_obj
378 plic
= mkplic_rule
.format(name
, plic_obj
, irq_offs
)
380 irq_offs
+= 1 # increment to next irq
381 return ('\n'.join(res
), irq_offs
)
383 def mk_ext_ifacedef(self
, iname
, inum
):
386 def extfastifinstance(self
, name
, count
):
389 def _extifinstance(self
, name
, count
, suffix
, prefix
, samename
=False,
393 pname
= self
.get_iname(count
)
397 sname
= self
.peripheral
.iname().format(count
)
398 template
= "interface {0}{3} = {2}{1}{4};"
399 return template
.format(pname
, sname
, prefix
, suffix
, ifsuffix
)
401 def extifinstance2(self
, name
, count
):
404 def extifinstance(self
, name
, count
):
405 return self
._extifinstance
(name
, count
, "",
406 "pinmux.peripheral_side.")
410 rule rl_connect_{0}_to_plic_{2};
411 if({1} == 1'b1) begin
412 ff_gateway_queue[{2}].enq(1);
413 plic.ifc_external_irq[{2}].irq_frm_gateway(True);
418 axi_master_declarations
= """\
419 typedef 0 Dmem_master_num;
420 typedef 1 Imem_master_num;
422 typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif )
424 typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif )
426 typedef TAdd#(DMA_master_num,1)
430 axi_fastslave_declarations
= """\
432 typedef TAdd#(LastGen_fastslave_num,1) Sdram_slave_num;
433 typedef TAdd#(Sdram_slave_num ,`ifdef SDRAM 1 `else 0 `endif )
435 typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM 1 `else 0 `endif )
437 typedef TAdd#(BootRom_slave_num ,`ifdef Debug 1 `else 0 `endif )
439 typedef TAdd#(Debug_slave_num , `ifdef TCMemory 1 `else 0 `endif )
441 typedef TAdd#(TCM_slave_num ,`ifdef DMA 1 `else 0 `endif )
443 typedef TAdd#(Dma_slave_num ,1 ) SlowPeripheral_slave_num;
444 typedef TAdd#(SlowPeripheral_slave_num,`ifdef VME 1 `else 0 `endif )
446 typedef TAdd#(VME_slave_num,1) Num_Fast_Slaves;
449 axi_slave_declarations
= """\
450 typedef 0 SlowMaster;
452 typedef TAdd#(LastGen_slave_num,`ifdef CLINT 1 `else 0 `endif )
454 typedef TAdd#(CLINT_slave_num ,`ifdef PLIC 1 `else 0 `endif )
456 typedef TAdd#(Plic_slave_num ,`ifdef AXIEXP 1 `else 0 `endif )
458 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
461 pinmux_cellrule
= """\
462 rule connect_select_lines_pinmux;
468 class CallFn(object):
469 def __init__(self
, peripheral
, name
):
470 self
.peripheral
= peripheral
473 def __call__(self
, *args
):
474 #print "__call__", self.name, self.peripheral.slow, args
475 if not self
.peripheral
.slow
:
477 return getattr(self
.peripheral
.slow
, self
.name
)(*args
[1:])
480 class PeripheralIface(object):
481 def __init__(self
, ifacename
):
483 slow
= slowfactory
.getcls(ifacename
)
484 print "Iface", ifacename
, slow
486 self
.slow
= slow(ifacename
)
487 self
.slow
.peripheral
= self
488 for fname
in ['slowimport',
490 'extifinstance2', 'extifinstance', 'extifdecl',
491 'slowifdecl', 'slowifdeclmux',
494 'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule',
496 'mk_plic', 'mk_ext_ifacedef',
497 '_mk_clk_con', 'mk_ext_ifacedef',
498 'mk_connection', 'mk_cellconn', '_mk_pincon']:
499 fn
= CallFn(self
, fname
)
500 setattr(self
, fname
, types
.MethodType(fn
, self
))
502 #print "PeripheralIface"
505 def mksuffix(self
, name
, i
):
506 if self
.slow
is None:
508 return self
.slow
.mksuffix(name
, i
)
510 def axi_reg_def(self
, start
, count
):
513 return self
.slow
.axi_reg_def(start
, self
.ifacename
, count
)
515 def axi_master_idx(self
, start
, count
, typ
):
516 if not self
.slow
or not self
.slow
.has_axi_master():
518 return self
.slow
.axi_master_idx(start
, self
.ifacename
, count
, typ
)
520 def axi_slave_idx(self
, start
, count
, typ
):
523 return self
.slow
.axi_slave_idx(start
, self
.ifacename
, count
, typ
)
525 def axi_fastaddr_map(self
, count
):
528 return self
.slow
.axi_fastaddr_map(self
.ifacename
, count
)
530 def axi_addr_map(self
, count
):
533 return self
.slow
.axi_addr_map(self
.ifacename
, count
)
536 class PeripheralInterfaces(object):
538 self
.fastbusmode
= False
540 def slowimport(self
, *args
):
542 for (name
, count
) in self
.ifacecount
:
543 #print "slowimport", name, self.data[name].slowimport
544 ret
.append(self
.data
[name
].slowimport())
545 return '\n'.join(li(list(filter(None, ret
)), 4))
547 def extfastifinstance(self
, *args
):
549 for (name
, count
) in self
.ifacecount
:
550 for i
in range(count
):
551 iname
= self
.data
[name
].iname().format(i
)
552 print "extfast", iname
, self
.is_on_fastbus(name
, i
)
553 if self
.is_on_fastbus(name
, i
):
555 ret
.append(self
.data
[name
].extfastifinstance(name
, i
))
556 return '\n'.join(li(list(filter(None, ret
)), 8))
558 def extifinstance2(self
, *args
):
560 for (name
, count
) in self
.ifacecount
:
561 for i
in range(count
):
562 iname
= self
.data
[name
].iname().format(i
)
563 ret
.append(self
.data
[name
].extifinstance2(name
, i
))
564 return '\n'.join(li(list(filter(None, ret
)), 8))
566 def extifinstance(self
, *args
):
568 for (name
, count
) in self
.ifacecount
:
569 for i
in range(count
):
570 iname
= self
.data
[name
].iname().format(i
)
571 if not self
.is_on_fastbus(name
, i
):
573 ret
.append(self
.data
[name
].extifinstance(name
, i
))
574 return '\n'.join(li(list(filter(None, ret
)), 8))
576 def extifdecl(self
, *args
):
578 for (name
, count
) in self
.ifacecount
:
579 for i
in range(count
):
580 if not self
.is_on_fastbus(name
, i
):
582 ret
.append(self
.data
[name
].extifdecl(name
, i
))
583 return '\n'.join(li(list(filter(None, ret
)), 8))
585 def slowifdeclmux(self
, *args
):
587 for (name
, count
) in self
.ifacecount
:
588 for i
in range(count
):
589 ret
.append(self
.data
[name
].slowifdeclmux(name
, i
))
590 return '\n'.join(li(list(filter(None, ret
)), 8))
592 def fastifdecl(self
, *args
):
594 for (name
, count
) in self
.ifacecount
:
595 for i
in range(count
):
596 print "fastifdecl", name
, i
, self
.is_on_fastbus(name
, i
)
597 if self
.is_on_fastbus(name
, i
):
599 ret
.append(self
.data
[name
].fastifdecl(name
, i
))
600 return '\n'.join(li(list(filter(None, ret
)), 4))
602 def slowifdecl(self
, *args
):
604 for (name
, count
) in self
.ifacecount
:
605 for i
in range(count
):
606 if self
.is_on_fastbus(name
, i
):
608 ret
.append(self
.data
[name
].slowifdecl().format(i
, name
))
609 return '\n'.join(list(filter(None, ret
)))
611 def axi_fastmem_def(self
, *args
):
612 return self
._axi
_reg
_def
(0x50000000, *args
)
614 def axi_reg_def(self
, *args
):
615 return self
._axi
_reg
_def
(0x00011100, *args
)
617 def _axi_reg_def(self
, start
, *args
):
619 for (name
, count
) in self
.ifacecount
:
620 for i
in range(count
):
621 if self
.is_on_fastbus(name
, i
):
623 x
= self
.data
[name
].axi_reg_def(start
, i
)
624 #print ("ifc", name, x)
628 return '\n'.join(list(filter(None, ret
)))
630 def _axi_num_idx(self
, start
, template
, typ
, idxtype
, *args
):
632 for (name
, count
) in self
.ifacecount
:
633 for i
in range(count
):
634 if self
.is_on_fastbus(name
, i
):
637 fn
= self
.data
[name
].axi_master_idx
639 fn
= self
.data
[name
].axi_slave_idx
640 (rdef
, offs
) = fn(start
, i
, idxtype
)
641 #print ("ifc", name, rdef, offs)
644 ret
.append("typedef %d LastGen_%s_num;" % (start
- 1, typ
))
645 decls
= '\n'.join(list(filter(None, ret
)))
646 return template
.format(decls
)
648 def axi_slave_idx(self
, *args
):
649 return self
._axi
_num
_idx
(0, axi_slave_declarations
, 'slave',
652 def axi_fastslave_idx(self
, *args
):
653 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
656 def axi_master_idx(self
, *args
):
657 return self
._axi
_num
_idx
(2, axi_master_declarations
, 'master',
660 def axi_fastslave_idx(self
, *args
):
661 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
664 def axi_fastaddr_map(self
, *args
):
666 for (name
, count
) in self
.ifacecount
:
667 for i
in range(count
):
668 if self
.is_on_fastbus(name
, i
):
670 ret
.append(self
.data
[name
].axi_fastaddr_map(i
))
671 return '\n'.join(li(list(filter(None, ret
)), 8))
673 def axi_addr_map(self
, *args
):
675 for (name
, count
) in self
.ifacecount
:
676 for i
in range(count
):
677 if self
.is_on_fastbus(name
, i
):
679 ret
.append(self
.data
[name
].axi_addr_map(i
))
680 return '\n'.join(li(list(filter(None, ret
)), 8))
682 def mkfast_peripheral(self
, *args
):
684 for (name
, count
) in self
.ifacecount
:
685 for i
in range(count
):
686 if self
.is_on_fastbus(name
, i
):
688 #print "mkfast", name, count
689 x
= self
.data
[name
].mkfast_peripheral()
691 suffix
= self
.data
[name
].mksuffix(name
, i
)
692 ret
.append(x
.format(suffix
))
693 return '\n'.join(li(list(filter(None, ret
)), 8))
695 def mkslow_peripheral(self
, *args
):
697 for (name
, count
) in self
.ifacecount
:
698 for i
in range(count
):
699 if self
.is_on_fastbus(name
, i
):
701 #print "mkslow", name, count
702 x
= self
.data
[name
].mkslow_peripheral()
704 suffix
= self
.data
[name
].mksuffix(name
, i
)
705 ret
.append(x
.format(suffix
))
706 return '\n'.join(li(list(filter(None, ret
)), 8))
708 def mk_fast_connection(self
, *args
):
710 for (name
, count
) in self
.ifacecount
:
711 for i
in range(count
):
712 if self
.is_on_fastbus(name
, i
):
714 txt
= self
.data
[name
].mk_connection(i
, "fabric", "fast")
717 print self
.data
[name
].mk_connection
719 return '\n'.join(li(list(filter(None, ret
)), 12))
721 def mk_connection(self
, *args
):
723 for (name
, count
) in self
.ifacecount
:
724 for i
in range(count
):
725 if self
.is_on_fastbus(name
, i
):
727 txt
= self
.data
[name
].mk_connection(i
, "slow_fabric", "")
730 print self
.data
[name
].mk_connection
732 return '\n'.join(li(list(filter(None, ret
)), 8))
734 def mk_cellconn(self
):
737 for (name
, count
) in self
.ifacecount
:
738 for i
in range(count
):
739 if self
.is_on_fastbus(name
, i
):
741 res
= self
.data
[name
].mk_cellconn(cellcount
, name
, i
)
744 (txt
, cellcount
) = res
746 ret
= li('\n'.join(list(filter(None, ret
))), 4)
747 return li(pinmux_cellrule
.format(ret
), 4)
750 return self
._mk
_pincon
("slow")
752 def mk_fast_pincon(self
):
753 return self
._mk
_pincon
("fast")
755 def _mk_pincon(self
, typ
):
757 for (name
, count
) in self
.ifacecount
:
758 for i
in range(count
):
759 if self
.is_on_fastbus(name
, i
):
761 txt
= self
.data
[name
]._mk
_pincon
(name
, i
, typ
)
763 return '\n'.join(li(list(filter(None, ret
)), 4))
765 def mk_dma_irq(self
):
773 for (name
, count
) in self
.ifacecount
:
775 for i
in range(count
):
776 if not self
.is_on_fastbus(name
, i
):
778 txt
= self
.data
[name
].mk_dma_sync(name
, i
)
782 txt
= self
.data
[name
].mk_dma_rule(name
, i
)
783 ifacerules
.append(txt
)
784 txt
= self
.data
[name
].mk_dma_connect(name
, i
)
786 ifacerules
= list(filter(None, ifacerules
))
788 txt
= "rule synchronize_%s_interrupts;" % name
791 rules
.append("endrule")
793 cnct
= list(filter(None, cnct
))
795 _cnct
= ["rule rl_connect_interrupt_to_DMA;",
796 " Bit #(%d) lv_interrupt_to_DMA={" % ct
]
799 cnct
= _cnct
+ [spc
+ spcsep
.join(cnct
)]
801 cnct
.append(" dma.interrupt_from_peripherals(\n" +
802 " lv_interrupt_to_DMA);")
803 cnct
.append("endrule;")
805 ret
= list(filter(None, sync
+ rules
+ cnct
))
807 return '\n'.join(ret
)
809 def num_dmachannels(self
):
810 return "`define NUM_DMACHANNELS {0}".format(self
.dma_count
)
812 def mk_ext_ifacedef(self
):
814 for (name
, count
) in self
.ifacecount
:
815 for i
in range(count
):
816 if self
.is_on_fastbus(name
, i
):
818 txt
= self
.data
[name
].mk_ext_ifacedef(name
, i
)
820 return '\n'.join(li(list(filter(None, ret
)), 8))
824 irq_offs
= 8 # XXX: DMA scovers 0-7?
825 for (name
, count
) in self
.ifacecount
:
826 for i
in range(count
):
827 if self
.is_on_fastbus(name
, i
):
829 res
= self
.data
[name
].mk_plic(i
, irq_offs
)
832 (txt
, irq_offs
) = res
834 self
.num_slow_irqs
= irq_offs
835 return '\n'.join(li(list(filter(None, ret
)), 4))
837 def mk_sloirqsdef(self
):
838 return " `define NUM_SLOW_IRQS {0}".format(self
.num_slow_irqs
)
840 def mk_fastclk_con(self
):
841 return self
._mk
_clk
_con
("fast")
843 def mk_slowclk_con(self
):
844 return self
._mk
_clk
_con
("slow")
846 def _mk_clk_con(self
, ctype
):
848 for (name
, count
) in self
.ifacecount
:
849 for i
in range(count
):
850 if self
.is_on_fastbus(name
, i
):
852 txt
= self
.data
[name
]._mk
_clk
_con
(name
, i
, ctype
)
854 return '\n'.join(li(list(filter(None, ret
)), 8))
856 def is_on_fastbus(self
, name
, i
):
857 #print "fastbus mode", self.fastbusmode, name, i
858 iname
= self
.data
[name
].iname().format(i
)
860 return iname
not in self
.fastbus
861 return iname
in self
.fastbus
864 class PFactory(object):
865 def getcls(self
, name
):
866 from uart
import uart
867 from quart
import quart
868 from sdmmc
import sdmmc
870 from eint
import eint
871 from rs232
import rs232
873 from eint
import eint
874 from jtag
import jtag
875 from spi
import spi
, mspi
876 from qspi
import qspi
, mqspi
877 from gpio
import gpio
878 from rgbttl
import rgbttl
879 from flexbus
import flexbus
881 for k
, v
in {'uart': uart
,
897 if name
.startswith(k
):
902 slowfactory
= PFactory()
904 if __name__
== '__main__':
908 i
= PeripheralIface('uart')
910 i
= PeripheralIface('gpioa')