src/bsv/peripheral_gen/base.py

   1 import types
   2
   3 def li(txt, indent):
   4     indent = ' ' * indent
   5     istxt = False
   6     if isinstance(txt, str):
   7         istxt = True
   8         txt = txt.split('\n')
   9     res = []
  10     for line in txt:
  11         line = line.split('\n')
  12         res += line
  13     txt = res
  14     res = []
  15     for line in txt:
  16         res.append(indent + line)
  17     if istxt:
  18         res = '\n'.join(res)
  19     return res
  20
  21
  22 class PBase(object):
  23     def __init__(self, name):
  24         self.name = name
  25
  26     def extifdecl(self, name, count):
  27         sname = self.get_iname(count)
  28         return "interface PeripheralSide%s %s;" % (name.upper(), sname)
  29
  30     def has_axi_master(self):
  31         return False
  32
  33     def irq_name(self):
  34         return ""
  35
  36     def mk_dma_irq(self, name, count):
  37         if not self.irq_name():
  38             return ''
  39         sname = self.get_iname(count)
  40         return "{0}_interrupt".format(sname)
  41
  42     def mk_dma_rule(self, name, count):
  43         irqname = self.mk_dma_irq(name, count)
  44         if not irqname:
  45             return ''
  46         pirqname = self.irq_name().format(count)
  47         template = "   {0}_interrupt.send(\n" + \
  48                    "           slow_peripherals.{1});"
  49         return template.format(irqname, pirqname)
  50
  51     def get_clock_reset(self, name, count):
  52         return "slow_clock,slow_reset"
  53
  54     def mk_dma_sync(self, name, count):
  55         irqname = self.mk_dma_irq(name, count)
  56         if not irqname:
  57             return ''
  58         sname = self.peripheral.iname().format(count)
  59         template = "SyncBitIfc#(Bit#(1)) {0} <-\n" + \
  60                    "           <-mkSyncBitToCC({1});"
  61         return template.format(irqname, self.get_clock_reset(name, count))
  62
  63     def mk_dma_connect(self, name, count):
  64         irqname = self.mk_dma_irq(name, count)
  65         if not irqname:
  66             return ''
  67         return "{0}.read".format(irqname)
  68
  69     def fastifdecl(self, name, count):
  70         return ''
  71
  72     def slowifdeclmux(self, name, count):
  73         return ''
  74
  75     def slowimport(self):
  76         return ''
  77
  78     def num_axi_regs32(self):
  79         return 0
  80
  81     def slowifdecl(self):
  82         return ''
  83
  84     def get_iname(self, inum):
  85         return "{0}{1}".format(self.name, self.mksuffix(self.name, inum))
  86
  87     def axibase(self, name, ifacenum):
  88         name = name.upper()
  89         return "%(name)s%(ifacenum)dBase" % locals()
  90
  91     def axiend(self, name, ifacenum):
  92         name = name.upper()
  93         return "%(name)s%(ifacenum)dEnd" % locals()
  94
  95     def axi_reg_def(self, start, name, ifacenum):
  96         name = name.upper()
  97         offs = self.num_axi_regs32() * 4 * 16
  98         if offs == 0:
  99             return ('', 0)
 100         end = start + offs - 1
 101         bname = self.axibase(name, ifacenum)
 102         bend = self.axiend(name, ifacenum)
 103         comment = "%d 32-bit regs" % self.num_axi_regs32()
 104         return ("    `define %(bname)s 'h%(start)08X\n"
 105                 "    `define %(bend)s  'h%(end)08X // %(comment)s" % locals(),
 106                 offs)
 107
 108     def axi_master_name(self, name, ifacenum, typ=''):
 109         name = name.upper()
 110         return "{0}{1}_master_num".format(name, ifacenum)
 111
 112     def axi_slave_name(self, name, ifacenum, typ=''):
 113         name = name.upper()
 114         return "{0}{1}_{2}slave_num".format(name, ifacenum, typ)
 115
 116     def axi_master_idx(self, idx, name, ifacenum, typ):
 117         name = self.axi_master_name(name, ifacenum, typ)
 118         return ("typedef {0} {1};".format(idx, name), 1)
 119
 120     def axi_slave_idx(self, idx, name, ifacenum, typ):
 121         name = self.axi_slave_name(name, ifacenum, typ)
 122         return ("typedef {0} {1};".format(idx, name), 1)
 123
 124     def axi_addr_map(self, name, ifacenum):
 125         bname = self.axibase(name, ifacenum)
 126         bend = self.axiend(name, ifacenum)
 127         name = self.axi_slave_name(name, ifacenum)
 128         return """\
 129         if(addr>=`{0} && addr<=`{1})
 130             return tuple2(True,fromInteger(valueOf({2})));
 131         else""".format(bname, bend, name)
 132
 133     def mk_pincon(self, name, count):
 134         # TODO: really should be using bsv.interface_decl.Interfaces
 135         # pin-naming rules.... logic here is hard-coded to duplicate
 136         # it (see Interface.__init__ outen)
 137         ret = []
 138         for p in self.peripheral.pinspecs:
 139             typ = p['type']
 140             pname = p['name']
 141             #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
 142             n = name  # "{0}{1}".format(self.name, self.mksuffix(name, count))
 143             ret.append("    //%s %s" % (n, str(p)))
 144             sname = self.peripheral.iname().format(count)
 145             sname = "{0}.{1}".format(sname, pname)
 146             ps = "pinmux.peripheral_side.%s" % sname
 147             if typ == 'out' or typ == 'inout':
 148                 fname = self.pinname_out(pname)
 149                 if not n.startswith('gpio'):  # XXX EURGH! horrible hack
 150                     n_ = "{0}{1}".format(n, count)
 151                 else:
 152                     n_ = n
 153                 if fname:
 154                     if p.get('outen'):
 155                         ps_ = ps + '_out'
 156                     else:
 157                         ps_ = ps
 158                     ret.append("mkConnection({0},\n\t\t\t{1}.{2});"
 159                                .format(ps_, n_, fname))
 160                 fname = None
 161                 if p.get('outen'):
 162                     fname = self.pinname_outen(pname)
 163                 if fname:
 164                     if isinstance(fname, str):
 165                         fname = "{0}.{1}".format(n_, fname)
 166                     fname = self.pinname_tweak(pname, 'outen', fname)
 167                     ret.append("mkConnection({0}_outen,\n\t\t\t{1});"
 168                                .format(ps, fname))
 169             if typ == 'in' or typ == 'inout':
 170                 fname = self.pinname_in(pname)
 171                 if fname:
 172                     if p.get('outen'):
 173                         ps_ = ps + '_in'
 174                     else:
 175                         ps_ = ps
 176                     n_ = "{0}{1}".format(n, count)
 177                     n_ = '{0}.{1}'.format(n_, fname)
 178                     n_ = self.ifname_tweak(pname, 'in', n_)
 179                     ret.append("mkConnection({1}, {0});".format(ps_, n_))
 180         return '\n'.join(li(ret, 6))
 181
 182     def mk_cellconn(self, *args):
 183         return ''
 184
 185     def mkfast_peripheral(self, size=0):
 186         return ''
 187
 188     def mkslow_peripheral(self, size=0):
 189         return ''
 190
 191     def mksuffix(self, name, i):
 192         return i
 193
 194     def __mk_connection(self, con, aname, fabricname):
 195         txt = "mkConnection ({2}.v_to_slaves\n" + \
 196               "            [fromInteger(valueOf({1}))],\n" + \
 197               "            {0});"
 198
 199         print "PBase __mk_connection", self.name, aname
 200         if not con:
 201             return ''
 202         return li(txt.format(con, aname, fabricname), 8)
 203
 204     def __mk_master_connection(self, con, aname):
 205         txt = "mkConnection (slow_fabric.v_to_slaves\n" + \
 206               "            [fromInteger(valueOf({1}))],\n" + \
 207               "            {0});"
 208
 209         print "PBase __mk_connection", self.name, aname
 210         if not con:
 211             return ''
 212         return li(txt.format(con, aname), 8)
 213
 214     def mk_connection(self, count, fabricname, typ, name=None):
 215         if name is None:
 216             name = self.name
 217         print "PBase mk_conn", self.name, count
 218         aname = self.axi_slave_name(name, count, typ)
 219         #dname = self.mksuffix(name, count)
 220         #dname = "{0}{1}".format(name, dname)
 221         con = self._mk_connection(name, count).format(count, aname)
 222         return self.__mk_connection(con, aname, fabricname)
 223
 224     def _mk_connection(self, name=None, count=0):
 225         return ''
 226
 227     def pinname_out(self, pname):
 228         return ''
 229
 230     def pinname_in(self, pname):
 231         return ''
 232
 233     def pinname_outen(self, pname):
 234         return ''
 235
 236     def ifname_tweak(self, pname, typ, txt):
 237         return txt
 238
 239     def pinname_tweak(self, pname, typ, txt):
 240         return txt
 241
 242     def num_irqs(self):
 243         return 0
 244
 245     def mk_plic(self, inum, irq_offs):
 246         res = []
 247         print "mk_plic", self.name, inum, irq_offs
 248         niq = self.num_irqs()
 249         if niq == 0:
 250             return ('', irq_offs)
 251         name = self.get_iname(inum)
 252         res.append("// PLIC rules for {0}".format(name))
 253         for idx in range(niq):
 254             plic_obj = self.plic_object(name, idx)
 255             print "plic_obj", name, idx, plic_obj
 256             plic = mkplic_rule.format(name, plic_obj, irq_offs)
 257             res.append(plic)
 258             irq_offs += 1  # increment to next irq
 259         return ('\n'.join(li(res, 5)), irq_offs)
 260
 261     def mk_ext_ifacedef(self, iname, inum):
 262         return ''
 263
 264     def extfastifinstance(self, name, count):
 265         return ''
 266
 267     def _extifinstance(self, name, count, suffix, prefix, samename=False):
 268         pname = self.get_iname(count)
 269         if samename:
 270             sname = pname
 271         else:
 272             sname = self.peripheral.iname().format(count)
 273         template = "        interface {0}{3} = {2}{1};"
 274         return template.format(pname, sname, prefix, suffix)
 275
 276     def extifinstance2(self, name, count):
 277         return ''
 278
 279     def extifinstance(self, name, count):
 280         return self._extifinstance(name, count, "",
 281                                             "pinmux.peripheral_side.")
 282
 283
 284 mkplic_rule = """\
 285 rule rl_connect_{0}_to_plic_{2};
 286    if({1} == 1'b1) begin
 287        ff_gateway_queue[{2}].enq(1);
 288        plic.ifc_external_irq[{2}].irq_frm_gateway(True);
 289    end
 290 endrule
 291 """
 292
 293 axi_master_declarations= """\
 294 typedef 0 Dmem_master_num;
 295 typedef 1 Imem_master_num;
 296 {0}
 297 typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif )
 298                 Debug_master_num;
 299 typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif )
 300                 DMA_master_num;
 301 typedef TAdd#(DMA_master_num,1)
 302                 Num_Masters;
 303 """
 304
 305 axi_fastslave_declarations = """\
 306 {0}
 307 typedef  TAdd#(LastGen_fastslave_num,1)      Sdram_cfg_slave_num;
 308 typedef  TAdd#(Sdram_slave_num   ,`ifdef SDRAM      1 `else 0 `endif )
 309                       Sdram_cfg_slave_num;
 310 typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM    1 `else 0 `endif )
 311                 BootRom_slave_num   ;
 312 typedef TAdd#(BootRom_slave_num  ,`ifdef Debug      1 `else 0 `endif )
 313                 Debug_slave_num ;
 314 typedef  TAdd#(Debug_slave_num   , `ifdef TCMemory  1 `else 0 `endif )
 315                 TCM_slave_num;
 316 typedef  TAdd#(TCM_slave_num     ,`ifdef DMA            1 `else 0 `endif )
 317                 Dma_slave_num;
 318 typedef  TAdd#(Dma_slave_num      ,1 )      SlowPeripheral_slave_num;
 319 typedef  TAdd#(SlowPeripheral_slave_num,`ifdef VME  1 `else 0 `endif )
 320                 VME_slave_num;
 321 typedef  TAdd#(VME_slave_num,`ifdef FlexBus 1 `else 0 `endif )
 322                 FlexBus_slave_num;
 323 typedef TAdd#(FlexBus_slave_num,1)
 324                 Num_Slaves;
 325
 326 """
 327
 328 axi_slave_declarations = """\
 329 typedef  0  SlowMaster;
 330 {0}
 331 typedef  TAdd#(LastGen_slave_num,`ifdef CLINT       1 `else 0 `endif )
 332               CLINT_slave_num;
 333 typedef  TAdd#(CLINT_slave_num  ,`ifdef PLIC        1 `else 0 `endif )
 334               Plic_slave_num;
 335 typedef  TAdd#(Plic_slave_num   ,`ifdef AXIEXP      1 `else 0 `endif )
 336               AxiExp1_slave_num;
 337 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
 338 """
 339
 340 pinmux_cellrule = """\
 341     rule connect_select_lines_pinmux;
 342 {0}
 343     endrule
 344 """
 345
 346
 347 class CallFn(object):
 348     def __init__(self, peripheral, name):
 349         self.peripheral = peripheral
 350         self.name = name
 351
 352     def __call__(self, *args):
 353         #print "__call__", self.name, self.peripheral.slow, args
 354         if not self.peripheral.slow:
 355             return ''
 356         return getattr(self.peripheral.slow, self.name)(*args[1:])
 357
 358
 359 class PeripheralIface(object):
 360     def __init__(self, ifacename):
 361         self.slow = None
 362         slow = slowfactory.getcls(ifacename)
 363         print "Iface", ifacename, slow
 364         if slow:
 365             self.slow = slow(ifacename)
 366             self.slow.peripheral = self
 367         for fname in ['slowimport',
 368                       'extfastifinstance',
 369                       'extifinstance2', 'extifinstance', 'extifdecl',
 370                       'slowifdecl', 'slowifdeclmux',
 371                       'fastifdecl',
 372                       'mkslow_peripheral',
 373                       'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule',
 374                       'mkfast_peripheral',
 375                       'mk_plic', 'mk_ext_ifacedef',
 376                       'mk_connection', 'mk_cellconn', 'mk_pincon']:
 377             fn = CallFn(self, fname)
 378             setattr(self, fname, types.MethodType(fn, self))
 379
 380         #print "PeripheralIface"
 381         #print dir(self)
 382
 383     def mksuffix(self, name, i):
 384         if self.slow is None:
 385             return i
 386         return self.slow.mksuffix(name, i)
 387
 388     def axi_reg_def(self, start, count):
 389         if not self.slow:
 390             return ('', 0)
 391         return self.slow.axi_reg_def(start, self.ifacename, count)
 392
 393     def axi_master_idx(self, start, count, typ):
 394         if not self.slow or not self.slow.has_axi_master():
 395             return ('', 0)
 396         return self.slow.axi_master_idx(start, self.ifacename, count, typ)
 397
 398     def axi_slave_idx(self, start, count, typ):
 399         if not self.slow:
 400             return ('', 0)
 401         return self.slow.axi_slave_idx(start, self.ifacename, count, typ)
 402
 403     def axi_addr_map(self, count):
 404         if not self.slow:
 405             return ''
 406         return self.slow.axi_addr_map(self.ifacename, count)
 407
 408
 409 class PeripheralInterfaces(object):
 410     def __init__(self):
 411         self.fastbusmode = False
 412
 413     def slowimport(self, *args):
 414         ret = []
 415         for (name, count) in self.ifacecount:
 416             #print "slowimport", name, self.data[name].slowimport
 417             ret.append(self.data[name].slowimport())
 418         return '\n'.join(list(filter(None, ret)))
 419
 420     def extfastifinstance(self, *args):
 421         ret = []
 422         for (name, count) in self.ifacecount:
 423             for i in range(count):
 424                 iname = self.data[name].iname().format(i)
 425                 print "extfast", iname, self.is_on_fastbus(name, i)
 426                 if self.is_on_fastbus(name, i):
 427                     continue
 428                 ret.append(self.data[name].extfastifinstance(name, i))
 429         return '\n'.join(list(filter(None, ret)))
 430
 431     def extifinstance2(self, *args):
 432         ret = []
 433         for (name, count) in self.ifacecount:
 434             for i in range(count):
 435                 iname = self.data[name].iname().format(i)
 436                 ret.append(self.data[name].extifinstance2(name, i))
 437         return '\n'.join(list(filter(None, ret)))
 438
 439     def extifinstance(self, *args):
 440         ret = []
 441         for (name, count) in self.ifacecount:
 442             for i in range(count):
 443                 iname = self.data[name].iname().format(i)
 444                 if not self.is_on_fastbus(name, i):
 445                     continue
 446                 ret.append(self.data[name].extifinstance(name, i))
 447         return '\n'.join(list(filter(None, ret)))
 448
 449     def extifdecl(self, *args):
 450         ret = []
 451         for (name, count) in self.ifacecount:
 452             for i in range(count):
 453                 if not self.is_on_fastbus(name, i):
 454                     continue
 455                 ret.append(self.data[name].extifdecl(name, i))
 456         return '\n'.join(li(list(filter(None, ret)), 8))
 457
 458     def slowifdeclmux(self, *args):
 459         ret = []
 460         for (name, count) in self.ifacecount:
 461             for i in range(count):
 462                 ret.append(self.data[name].slowifdeclmux(name, i))
 463         return '\n'.join(list(filter(None, ret)))
 464
 465     def fastifdecl(self, *args):
 466         ret = []
 467         for (name, count) in self.ifacecount:
 468             for i in range(count):
 469                 print "fastifdecl", name, i, self.is_on_fastbus(name, i)
 470                 if self.is_on_fastbus(name, i):
 471                     continue
 472                 ret.append(self.data[name].fastifdecl(name, i))
 473         return '\n'.join(list(filter(None, ret)))
 474
 475     def slowifdecl(self, *args):
 476         ret = []
 477         for (name, count) in self.ifacecount:
 478             for i in range(count):
 479                 if self.is_on_fastbus(name, i):
 480                     continue
 481                 ret.append(self.data[name].slowifdecl().format(i, name))
 482         return '\n'.join(list(filter(None, ret)))
 483
 484     def axi_reg_def(self, *args):
 485         ret = []
 486         start = 0x00011100  # start of AXI peripherals address
 487         for (name, count) in self.ifacecount:
 488             for i in range(count):
 489                 if self.is_on_fastbus(name, i):
 490                     continue
 491                 x = self.data[name].axi_reg_def(start, i)
 492                 #print ("ifc", name, x)
 493                 (rdef, offs) = x
 494                 ret.append(rdef)
 495                 start += offs
 496         return '\n'.join(list(filter(None, ret)))
 497
 498     def _axi_num_idx(self, start, template, typ, idxtype, *args):
 499         ret = []
 500         for (name, count) in self.ifacecount:
 501             for i in range(count):
 502                 if self.is_on_fastbus(name, i):
 503                     continue
 504                 if typ == 'master':
 505                     fn = self.data[name].axi_master_idx
 506                 else:
 507                     fn = self.data[name].axi_slave_idx
 508                 (rdef, offs) = fn(start, i, idxtype)
 509                 #print ("ifc", name, rdef, offs)
 510                 ret.append(rdef)
 511                 start += offs
 512         ret.append("typedef %d LastGen_%s_num;" % (start - 1, typ))
 513         decls = '\n'.join(list(filter(None, ret)))
 514         return template.format(decls)
 515
 516     def axi_slave_idx(self, *args):
 517         return self._axi_num_idx(0, axi_slave_declarations, 'slave',
 518                                  '', *args)
 519
 520     def axi_fastslave_idx(self, *args):
 521         return self._axi_num_idx(0, axi_fastslave_declarations, 'fastslave',
 522                                  'fast', *args)
 523
 524     def axi_master_idx(self, *args):
 525         return self._axi_num_idx(2, axi_master_declarations, 'master',
 526                                  'master', *args)
 527
 528     def axi_fastslave_idx(self, *args):
 529         return self._axi_num_idx(0, axi_fastslave_declarations, 'fastslave',
 530                                  'fast', *args)
 531
 532     def axi_addr_map(self, *args):
 533         ret = []
 534         for (name, count) in self.ifacecount:
 535             for i in range(count):
 536                 if self.is_on_fastbus(name, i):
 537                     continue
 538                 ret.append(self.data[name].axi_addr_map(i))
 539         return '\n'.join(list(filter(None, ret)))
 540
 541     def mkfast_peripheral(self, *args):
 542         ret = []
 543         for (name, count) in self.ifacecount:
 544             for i in range(count):
 545                 if self.is_on_fastbus(name, i):
 546                     continue
 547                 #print "mkfast", name, count
 548                 x = self.data[name].mkfast_peripheral()
 549                 print name, count, x
 550                 suffix = self.data[name].mksuffix(name, i)
 551                 ret.append(x.format(suffix))
 552         return '\n'.join(list(filter(None, ret)))
 553
 554     def mkslow_peripheral(self, *args):
 555         ret = []
 556         for (name, count) in self.ifacecount:
 557             for i in range(count):
 558                 if self.is_on_fastbus(name, i):
 559                     continue
 560                 #print "mkslow", name, count
 561                 x = self.data[name].mkslow_peripheral()
 562                 print name, count, x
 563                 suffix = self.data[name].mksuffix(name, i)
 564                 ret.append(x.format(suffix))
 565         return '\n'.join(list(filter(None, ret)))
 566
 567     def mk_fast_connection(self, *args):
 568         ret = []
 569         for (name, count) in self.ifacecount:
 570             for i in range(count):
 571                 if self.is_on_fastbus(name, i):
 572                     continue
 573                 txt = self.data[name].mk_connection(i, "fabric", "fast")
 574                 if name == 'gpioa':
 575                     print "txt", txt
 576                     print self.data[name].mk_connection
 577                 ret.append(txt)
 578         return '\n'.join(list(filter(None, ret)))
 579
 580     def mk_connection(self, *args):
 581         ret = []
 582         for (name, count) in self.ifacecount:
 583             for i in range(count):
 584                 if self.is_on_fastbus(name, i):
 585                     continue
 586                 txt = self.data[name].mk_connection(i, "slow_fabric", "")
 587                 if name == 'gpioa':
 588                     print "txt", txt
 589                     print self.data[name].mk_connection
 590                 ret.append(txt)
 591         return '\n'.join(list(filter(None, ret)))
 592
 593     def mk_cellconn(self):
 594         ret = []
 595         cellcount = 0
 596         for (name, count) in self.ifacecount:
 597             for i in range(count):
 598                 if self.is_on_fastbus(name, i):
 599                     continue
 600                 res = self.data[name].mk_cellconn(cellcount, name, i)
 601                 if not res:
 602                     continue
 603                 (txt, cellcount) = res
 604                 ret.append(txt)
 605         ret = '\n'.join(list(filter(None, ret)))
 606         return pinmux_cellrule.format(ret)
 607
 608     def mk_pincon(self):
 609         ret = []
 610         for (name, count) in self.ifacecount:
 611             for i in range(count):
 612                 if self.is_on_fastbus(name, i):
 613                     continue
 614                 txt = self.data[name].mk_pincon(name, i)
 615                 ret.append(txt)
 616         return '\n'.join(list(filter(None, ret)))
 617
 618     def mk_dma_irq(self):
 619         ret = []
 620         sync = []
 621         rules = []
 622         cnct = []
 623
 624         self.dma_count = 0
 625
 626         for (name, count) in self.ifacecount:
 627             ifacerules = []
 628             for i in range(count):
 629                 if not self.is_on_fastbus(name, i):
 630                     continue
 631                 txt = self.data[name].mk_dma_sync(name, i)
 632                 if txt:
 633                     self.dma_count += 1
 634                 sync.append(txt)
 635                 txt = self.data[name].mk_dma_rule(name, i)
 636                 ifacerules.append(txt)
 637                 txt = self.data[name].mk_dma_connect(name, i)
 638                 cnct.append(txt)
 639             ifacerules = list(filter(None, ifacerules))
 640             if ifacerules:
 641                 txt = "rule synchronize_%s_interrupts;" % name
 642                 rules.append(txt)
 643                 rules += ifacerules
 644                 rules.append("endrule")
 645
 646         cnct = list(filter(None, cnct))
 647         ct = self.dma_count
 648         _cnct    = ["rule rl_connect_interrupt_to_DMA;",
 649                     "  Bit #(%d) lv_interrupt_to_DMA={" % ct]
 650         spc = "                      "
 651         spcsep = ",\n" + spc
 652         cnct = _cnct + [spc + spcsep.join(cnct)]
 653         cnct.append("   };")
 654         cnct.append("   dma.interrupt_from_peripherals(\n" + \
 655                     "       lv_interrupt_to_DMA);")
 656         cnct.append("endrule;")
 657
 658         ret = list(filter(None, sync + rules + cnct))
 659         ret = li(ret, 15)
 660         return '\n'.join(ret)
 661
 662     def num_dmachannels(self):
 663         return "`define NUM_DMACHANNELS {0}".format(self.dma_count)
 664
 665     def mk_ext_ifacedef(self):
 666         ret = []
 667         for (name, count) in self.ifacecount:
 668             for i in range(count):
 669                 if self.is_on_fastbus(name, i):
 670                     continue
 671                 txt = self.data[name].mk_ext_ifacedef(name, i)
 672                 ret.append(txt)
 673         return '\n'.join(list(filter(None, ret)))
 674
 675     def mk_plic(self):
 676         ret = []
 677         irq_offs = 8  # XXX: DMA scovers 0-7?
 678         for (name, count) in self.ifacecount:
 679             for i in range(count):
 680                 if self.is_on_fastbus(name, i):
 681                     continue
 682                 res = self.data[name].mk_plic(i, irq_offs)
 683                 if not res:
 684                     continue
 685                 (txt, irq_offs) = res
 686                 ret.append(txt)
 687         self.num_slow_irqs = irq_offs
 688         return '\n'.join(list(filter(None, ret)))
 689
 690     def mk_sloirqsdef(self):
 691         return "    `define NUM_SLOW_IRQS {0}".format(self.num_slow_irqs)
 692
 693     def is_on_fastbus(self, name, i):
 694         #print "fastbus mode", self.fastbusmode, name, i
 695         iname = self.data[name].iname().format(i)
 696         if self.fastbusmode:
 697             return iname not in self.fastbus
 698         return iname in self.fastbus
 699
 700
 701 class PFactory(object):
 702     def getcls(self, name):
 703         from uart import uart
 704         from quart import quart
 705         from sdmmc import sdmmc
 706         from pwm import pwm
 707         from eint import eint
 708         from rs232 import rs232
 709         from twi import twi
 710         from eint import eint
 711         from jtag import jtag
 712         from spi import spi, mspi
 713         from qspi import qspi, mqspi
 714         from gpio import gpio
 715         from rgbttl import rgbttl
 716
 717         for k, v in {'uart': uart,
 718                      'rs232': rs232,
 719                      'twi': twi,
 720                      'quart': quart,
 721                      'mqspi': mqspi,
 722                      'mspi': mspi,
 723                      'qspi': qspi,
 724                      'spi': spi,
 725                      'pwm': pwm,
 726                      'eint': eint,
 727                      'sd': sdmmc,
 728                      'jtag': jtag,
 729                      'lcd': rgbttl,
 730                      'gpio': gpio
 731                      }.items():
 732             if name.startswith(k):
 733                 return v
 734         return None
 735
 736
 737 slowfactory = PFactory()
 738
 739 if __name__ == '__main__':
 740     p = uart('uart')
 741     print p.slowimport()
 742     print p.slowifdecl()
 743     i = PeripheralIface('uart')
 744     print i, i.slow
 745     i = PeripheralIface('gpioa')
 746     print i, i.slow