7 if isinstance(txt
, str):
12 line
= line
.split('\n')
17 res
.append(indent
+ line
)
24 def __init__(self
, name
):
27 def extifdecl(self
, name
, count
):
28 sname
= self
.get_iname(count
)
29 return "interface PeripheralSide%s %s;" % (name
.upper(), sname
)
31 def has_axi_master(self
):
37 def mk_dma_irq(self
, name
, count
):
38 if not self
.irq_name():
40 sname
= self
.get_iname(count
)
41 return "{0}_interrupt".format(sname
)
43 def mk_dma_rule(self
, name
, count
):
44 irqname
= self
.mk_dma_irq(name
, count
)
47 pirqname
= self
.irq_name().format(count
)
48 template
= " {0}.send(\n" + \
49 " slow_peripherals.{1});"
50 return template
.format(irqname
, pirqname
)
52 def get_clock_reset(self
, name
, count
):
53 return "slow_clock,slow_reset"
55 def mk_dma_sync(self
, name
, count
):
56 irqname
= self
.mk_dma_irq(name
, count
)
59 sname
= self
.peripheral
.iname().format(count
)
60 template
= "SyncBitIfc#(Bit#(1)) {0} <-\n" + \
61 " <-mkSyncBitToCC({1});"
62 return template
.format(irqname
, self
.get_clock_reset(name
, count
))
64 def mk_dma_connect(self
, name
, count
):
65 irqname
= self
.mk_dma_irq(name
, count
)
68 return "{0}.read".format(irqname
)
70 def fastifdecl(self
, name
, count
):
73 def slowifdeclmux(self
, name
, count
):
79 def num_axi_regs32(self
):
85 def get_iname(self
, inum
):
86 return "{0}{1}".format(self
.name
, self
.mksuffix(self
.name
, inum
))
88 def axibase(self
, name
, ifacenum
, idx
):
90 return "%(name)s%(ifacenum)d%(idx)sBase" % locals()
92 def axiend(self
, name
, ifacenum
, idx
):
94 return "%(name)s%(ifacenum)d%(idx)sEnd" % locals()
96 def _axi_reg_def(self
, idx
, numregs
, start
, name
, ifacenum
):
98 offs
= numregs
* 4 * 16
101 end
= start
+ offs
- 1
102 bname
= self
.axibase(name
, ifacenum
, idx
)
103 bend
= self
.axiend(name
, ifacenum
, idx
)
104 comment
= "%d 32-bit regs" % numregs
105 return (" `define %(bname)s 'h%(start)08X\n"
106 " `define %(bend)s 'h%(end)08X // %(comment)s" % locals(),
109 def axi_reg_def(self
, start
, name
, ifacenum
):
110 offs
= self
.num_axi_regs32()
113 if not isinstance(offs
, list):
118 for (idx
, nregs
) in enumerate(offs
):
123 (txt
, off
) = self
._axi
_reg
_def
(idx
, nregs
, start
, name
, ifacenum
)
127 return ('\n'.join(res
), offstotal
)
129 def axi_master_name(self
, name
, ifacenum
, typ
=''):
131 return "{0}{1}_master_num".format(name
, ifacenum
)
133 def axi_slave_name(self
, idx
, name
, ifacenum
, typ
=''):
135 return "{0}{1}{3}_{2}slave_num".format(name
, ifacenum
, typ
, idx
)
137 def axi_master_idx(self
, idx
, name
, ifacenum
, typ
):
138 name
= self
.axi_master_name(name
, ifacenum
, typ
)
139 return ("typedef {0} {1};".format(idx
, name
), 1)
141 def axi_slave_idx(self
, idx
, name
, ifacenum
, typ
):
142 offs
= self
.num_axi_regs32()
145 if not isinstance(offs
, list):
148 for (i
, nregs
) in enumerate(offs
):
153 name_
= self
.axi_slave_name(idx_
, name
, ifacenum
, typ
)
154 res
.append("typedef {0} {1};".format(idx
+i
, name_
))
155 return ('\n'.join(res
), len(offs
))
157 def axi_fastaddr_map(self
, name
, ifacenum
):
158 return self
.axi_addr_map(name
, ifacenum
, 'fast')
160 def _axi_addr_map(self
, idx
, name
, ifacenum
, typ
=""):
161 bname
= self
.axibase(name
, ifacenum
, idx
)
162 bend
= self
.axiend(name
, ifacenum
, idx
)
163 name
= self
.axi_slave_name(idx
, name
, ifacenum
, typ
)
165 if(addr>=`{0} && addr<=`{1})
166 return tuple2(True,fromInteger(valueOf({2})));
168 return template
.format(bname
, bend
, name
)
170 def axi_addr_map(self
, name
, ifacenum
, typ
=""):
171 offs
= self
.num_axi_regs32()
174 if not isinstance(offs
, list):
177 for (idx
, nregs
) in enumerate(offs
):
182 res
.append(self
._axi
_addr
_map
(idx
, name
, ifacenum
, typ
))
183 return '\n'.join(res
)
185 def _mk_pincon(self
, name
, count
, ptyp
):
186 # TODO: really should be using bsv.interface_decl.Interfaces
187 # pin-naming rules.... logic here is hard-coded to duplicate
188 # it (see Interface.__init__ outen)
190 for p
in self
.peripheral
.pinspecs
:
193 #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
194 n
= name
# "{0}{1}".format(self.name, self.mksuffix(name, count))
195 ret
.append("//%s %s" % (n
, str(p
)))
197 sname
= self
.get_iname(count
)
198 sname
= "{0}.{1}".format(sname
, pname
)
199 ps
= "slow_peripherals.%s" % sname
201 sname
= self
.peripheral
.iname().format(count
)
202 sname
= "{0}.{1}".format(sname
, pname
)
203 ps
= "pinmux.peripheral_side.%s" % sname
204 if typ
== 'out' or typ
== 'inout':
205 fname
= self
.pinname_out(pname
)
206 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
207 n_
= "{0}{1}".format(n
, count
)
215 cn
= self
._mk
_actual
_connection
('out', name
,
217 pname
, ps_
, n_
, fname
)
221 fname
= self
.pinname_outen(pname
)
223 if isinstance(fname
, str):
224 fname
= "{0}.{1}".format(n_
, fname
)
225 fname
= self
.pinname_tweak(pname
, 'outen', fname
)
226 cn
= self
._mk
_actual
_connection
('outen', name
,
230 if typ
== 'in' or typ
== 'inout':
231 fname
= self
.pinname_in(pname
)
237 n_
= "{0}{1}".format(n
, count
)
238 n_
= '{0}.{1}'.format(n_
, fname
)
239 n_
= self
.ifname_tweak(pname
, 'in', n_
)
240 cn
= self
._mk
_actual
_connection
('in', name
,
242 pname
, ps_
, n_
, fname
)
244 return '\n'.join(ret
)
246 def _mk_vpincon(self
, name
, count
, ptyp
, typ
, pname
, stype
=None):
250 ret
.append("//%s %s %s %s %s" % (name
, ptyp
, typ
, pname
, stype
))
252 sname
= self
.get_iname(count
)
253 ps
= "slow_peripherals.%s" % sname
255 sname
= self
.peripheral
.iname().format(count
)
256 ps
= "pinmux.peripheral_side.%s" % sname
257 n
= self
.get_iname(count
)
259 n
= "{0}.{1}".format(n
, stype
)
260 ps_
= "{0}.{1}".format(ps
, pname
)
261 ret
+= self
._mk
_actual
_connection
(typ
, name
, count
, typ
,
262 pname
, ps_
, n
, stype
)
263 return '\n'.join(ret
)
265 def _mk_actual_connection(self
, ctype
, name
, count
, typ
,
266 pname
, ps
, n
, fname
):
268 ck
= self
.get_clock_reset(name
, count
)
270 if ck
== PBase
.get_clock_reset(self
, name
, count
):
271 ret
.append("mkConnection({0},\n\t\t\t{1}.{2});"
272 .format(ps
, n
, fname
))
274 n2
= "{0}{1}".format(name
, count
)
275 sync
= '{0}_{1}_sync'.format(n2
, pname
)
276 ret
.append("mkConnection({0},\n\t\t\t{1}.get);"
278 ret
.append("mkConnection({0}.put,\n\t\t\t{1}.{2});"
279 .format(sync
, n
, fname
))
280 elif ctype
== 'outen':
281 ret
.append("mkConnection({0}_outen,\n\t\t\t{1});"
284 if ck
== PBase
.get_clock_reset(self
, name
, count
):
285 ret
.append("mkConnection({1},\n\t\t\t{0});".format(
288 n2
= "{0}{1}".format(name
, count
)
289 sync
= '{0}_{1}_sync'.format(n2
, pname
)
290 ret
.append("mkConnection({1}.put,\n\t\t\t{0});".format(
292 ret
.append("mkConnection({1},\n\t\t\t{0}.get);".format(
297 def _mk_clk_con(self
, name
, count
, ctype
):
299 ck
= self
.get_clock_reset(name
, count
)
300 if ck
== PBase
.get_clock_reset(self
, name
, count
):
303 spc
= self
.get_clk_spc(ctype
)
306 ck
= self
.get_clk_spc(ctype
)
308 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
310 for p
in self
.peripheral
.pinspecs
:
314 if typ
== 'out' or typ
== 'inout':
315 fname
= self
.pinname_out(pname
)
318 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
319 n_
= "{0}{1}".format(n
, count
)
322 n_
= '{0}_{1}'.format(n_
, pname
)
323 ret
.append(template
.format("Bit#(1)", n_
, ck
, spc
))
324 if typ
== 'in' or typ
== 'inout':
325 fname
= self
.pinname_in(pname
)
328 #fname = self.pinname_in(pname)
329 n_
= "{0}{1}".format(n
, count
)
330 n_
= '{0}_{1}'.format(n_
, pname
)
331 #n_ = self.ifname_tweak(pname, 'in', n_)
332 ret
.append(template
.format("Bit#(1)", n_
, spc
, ck
))
333 return '\n'.join(ret
)
335 def get_clk_spc(self
, ctype
):
337 return "sp_clock, sp_reset"
339 return "core_clock, core_reset"
341 def _mk_clk_vcon(self
, name
, count
, ctype
, typ
, pname
, bitspec
):
342 ck
= self
.get_clock_reset(name
, count
)
343 if ck
== PBase
.get_clock_reset(self
, name
, count
):
346 spc
= self
.get_clk_spc(ctype
)
349 ck
= self
.get_clk_spc(ctype
)
351 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
354 n_
= "{0}{1}".format(name
, count
)
355 n_
= '{0}_{1}'.format(n_
, pname
)
356 if typ
== 'in' or typ
== 'inout':
358 return template
.format(bitspec
, n_
, ck
, spc
)
361 def mk_cellconn(self
, *args
):
364 def mkfast_peripheral(self
, size
=0):
367 def mkslow_peripheral(self
, size
=0):
370 def mksuffix(self
, name
, i
):
373 def __mk_connection(self
, con
, aname
, count
, fabricname
):
374 txt
= "mkConnection ({2}.v_to_slaves\n" + \
375 " [fromInteger(valueOf({1}))],\n" + \
378 print "PBase __mk_connection", self
.name
, aname
381 con
= con
.format(count
, aname
)
382 return txt
.format(con
, aname
, fabricname
)
384 def __mk_master_connection(self
, con
, aname
, count
, fabricname
):
385 txt
= "mkConnection ({0}, {2}.v_from_masters\n" + \
386 " [fromInteger(valueOf({1}))]);\n"
388 print "PBase __mk_master_connection", self
.name
, aname
391 con
= con
.format(count
, aname
)
392 return txt
.format(con
, aname
, fabricname
)
394 def mk_master_connection(self
, count
, fabricname
, typ
, name
=None):
395 if not self
.has_axi_master():
399 print "PBase mk_master_conn", self
.name
, count
400 aname
= self
.axi_master_name(name
, count
, typ
)
402 connections
= self
._mk
_connection
(name
, count
, True)
403 if not isinstance(connections
, list):
404 connections
= [connections
]
405 for con
in connections
:
406 ret
.append(self
.__mk
_master
_connection
(con
, aname
, count
,
408 return '\n'.join(ret
)
410 def mk_connection(self
, count
, fabricname
, typ
, name
=None):
413 print "PBase mk_conn", self
.name
, count
415 connections
= self
._mk
_connection
(name
, count
)
416 if not isinstance(connections
, list):
417 connections
= [connections
]
418 for (idx
, con
) in enumerate(connections
):
419 aname
= self
.axi_slave_name(idx
, name
, count
, typ
)
420 ret
.append(self
.__mk
_connection
(con
, aname
, count
, fabricname
))
421 return '\n'.join(ret
)
423 def _mk_connection(self
, name
=None, count
=0):
426 def pinname_out(self
, pname
):
429 def pinname_in(self
, pname
):
432 def pinname_outen(self
, pname
):
435 def ifname_tweak(self
, pname
, typ
, txt
):
438 def pinname_tweak(self
, pname
, typ
, txt
):
444 def mk_plic(self
, inum
, irq_offs
):
446 print "mk_plic", self
.name
, inum
, irq_offs
447 niq
= self
.num_irqs()
449 return ('', irq_offs
)
450 name
= self
.get_iname(inum
)
451 res
.append("// PLIC rules for {0}".format(name
))
452 for idx
in range(niq
):
453 plic_obj
= self
.plic_object(name
, idx
)
454 print "plic_obj", name
, idx
, plic_obj
455 plic
= mkplic_rule
.format(name
, plic_obj
, irq_offs
)
457 irq_offs
+= 1 # increment to next irq
458 return ('\n'.join(res
), irq_offs
)
460 def mk_ext_ifacedef(self
, iname
, inum
):
463 def extfastifinstance(self
, name
, count
):
466 def _extifinstance(self
, name
, count
, suffix
, prefix
, samename
=False,
470 pname
= self
.get_iname(count
)
474 sname
= self
.peripheral
.iname().format(count
)
475 template
= "interface {0}{3} = {2}{1}{4};"
476 return template
.format(pname
, sname
, prefix
, suffix
, ifsuffix
)
478 def extifinstance2(self
, name
, count
):
481 def extifinstance(self
, name
, count
):
482 return self
._extifinstance
(name
, count
, "",
483 "pinmux.peripheral_side.")
487 rule rl_connect_{0}_to_plic_{2};
488 if({1} == 1'b1) begin
489 ff_gateway_queue[{2}].enq(1);
490 plic.ifc_external_irq[{2}].irq_frm_gateway(True);
495 axi_master_declarations
= """\
496 typedef 0 Dmem_master_num;
497 typedef 1 Imem_master_num;
499 typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif )
501 typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif )
503 typedef TAdd#(DMA_master_num,1)
507 axi_fastslave_declarations
= """\
509 typedef TAdd#(LastGen_fastslave_num,1) Sdram_slave_num;
510 typedef TAdd#(Sdram_slave_num ,`ifdef SDRAM 1 `else 0 `endif )
512 typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM 1 `else 0 `endif )
514 typedef TAdd#(BootRom_slave_num ,`ifdef Debug 1 `else 0 `endif )
516 typedef TAdd#(Debug_slave_num , `ifdef TCMemory 1 `else 0 `endif )
518 typedef TAdd#(TCM_slave_num ,`ifdef DMA 1 `else 0 `endif )
520 typedef TAdd#(Dma_slave_num ,1 ) SlowPeripheral_slave_num;
521 typedef TAdd#(SlowPeripheral_slave_num,`ifdef VME 1 `else 0 `endif )
523 typedef TAdd#(VME_slave_num,1) Num_Fast_Slaves;
526 axi_slave_declarations
= """\
527 typedef 0 SlowMaster;
529 typedef TAdd#(LastGen_slave_num,`ifdef CLINT 1 `else 0 `endif )
531 typedef TAdd#(CLINT_slave_num ,`ifdef PLIC 1 `else 0 `endif )
533 typedef TAdd#(Plic_slave_num ,`ifdef AXIEXP 1 `else 0 `endif )
535 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
538 pinmux_cellrule
= """\
539 rule connect_select_lines_pinmux;
545 class CallFn(object):
546 def __init__(self
, peripheral
, name
):
547 self
.peripheral
= peripheral
550 def __call__(self
, *args
):
551 #print "__call__", self.name, self.peripheral.slow, args
552 if not self
.peripheral
.slow
:
554 return getattr(self
.peripheral
.slow
, self
.name
)(*args
[1:])
557 class PeripheralIface(object):
558 def __init__(self
, ifacename
):
560 slow
= slowfactory
.getcls(ifacename
)
561 print "Iface", ifacename
, slow
563 self
.slow
= slow(ifacename
)
564 self
.slow
.peripheral
= self
565 for fname
in ['slowimport',
567 'extifinstance2', 'extifinstance', 'extifdecl',
568 'slowifdecl', 'slowifdeclmux',
571 'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule',
573 'mk_plic', 'mk_ext_ifacedef',
574 '_mk_clk_con', 'mk_ext_ifacedef',
575 'mk_connection', 'mk_master_connection',
576 'mk_cellconn', '_mk_pincon']:
577 fn
= CallFn(self
, fname
)
578 setattr(self
, fname
, types
.MethodType(fn
, self
))
580 #print "PeripheralIface"
583 def mksuffix(self
, name
, i
):
584 if self
.slow
is None:
586 return self
.slow
.mksuffix(name
, i
)
588 def axi_reg_def(self
, start
, count
):
591 return self
.slow
.axi_reg_def(start
, self
.ifacename
, count
)
593 def axi_master_idx(self
, start
, count
, typ
):
594 if not self
.slow
or not self
.slow
.has_axi_master():
596 return self
.slow
.axi_master_idx(start
, self
.ifacename
, count
, typ
)
598 def axi_slave_idx(self
, start
, count
, typ
):
601 return self
.slow
.axi_slave_idx(start
, self
.ifacename
, count
, typ
)
603 def axi_fastaddr_map(self
, count
):
606 return self
.slow
.axi_fastaddr_map(self
.ifacename
, count
)
608 def axi_addr_map(self
, count
):
611 return self
.slow
.axi_addr_map(self
.ifacename
, count
)
614 class PeripheralInterfaces(object):
616 self
.fastbusmode
= False
618 def slowimport(self
, *args
):
620 for (name
, count
) in self
.ifacecount
:
621 #print "slowimport", name, self.data[name].slowimport
622 ret
.append(self
.data
[name
].slowimport())
623 return '\n'.join(li(list(filter(None, ret
)), 4))
625 def extfastifinstance(self
, *args
):
627 for (name
, count
) in self
.ifacecount
:
628 for i
in range(count
):
629 iname
= self
.data
[name
].iname().format(i
)
630 print "extfast", iname
, self
.is_on_fastbus(name
, i
)
631 if self
.is_on_fastbus(name
, i
):
633 ret
.append(self
.data
[name
].extfastifinstance(name
, i
))
634 return '\n'.join(li(list(filter(None, ret
)), 8))
636 def extifinstance2(self
, *args
):
638 for (name
, count
) in self
.ifacecount
:
639 for i
in range(count
):
640 iname
= self
.data
[name
].iname().format(i
)
641 ret
.append(self
.data
[name
].extifinstance2(name
, i
))
642 return '\n'.join(li(list(filter(None, ret
)), 8))
644 def extifinstance(self
, *args
):
646 for (name
, count
) in self
.ifacecount
:
647 for i
in range(count
):
648 iname
= self
.data
[name
].iname().format(i
)
649 if not self
.is_on_fastbus(name
, i
):
651 ret
.append(self
.data
[name
].extifinstance(name
, i
))
652 return '\n'.join(li(list(filter(None, ret
)), 8))
654 def extifdecl(self
, *args
):
656 for (name
, count
) in self
.ifacecount
:
657 for i
in range(count
):
658 if not self
.is_on_fastbus(name
, i
):
660 ret
.append(self
.data
[name
].extifdecl(name
, i
))
661 return '\n'.join(li(list(filter(None, ret
)), 8))
663 def slowifdeclmux(self
, *args
):
665 for (name
, count
) in self
.ifacecount
:
666 for i
in range(count
):
667 ret
.append(self
.data
[name
].slowifdeclmux(name
, i
))
668 return '\n'.join(li(list(filter(None, ret
)), 8))
670 def fastifdecl(self
, *args
):
672 for (name
, count
) in self
.ifacecount
:
673 for i
in range(count
):
674 print "fastifdecl", name
, i
, self
.is_on_fastbus(name
, i
)
675 if self
.is_on_fastbus(name
, i
):
677 ret
.append(self
.data
[name
].fastifdecl(name
, i
))
678 return '\n'.join(li(list(filter(None, ret
)), 4))
680 def slowifdecl(self
, *args
):
682 for (name
, count
) in self
.ifacecount
:
683 for i
in range(count
):
684 if self
.is_on_fastbus(name
, i
):
686 ret
.append(self
.data
[name
].slowifdecl().format(i
, name
))
687 return '\n'.join(list(filter(None, ret
)))
689 def axi_fastmem_def(self
, *args
):
690 return self
._axi
_reg
_def
(0x50000000, *args
)
692 def axi_reg_def(self
, *args
):
693 return self
._axi
_reg
_def
(0x00011100, *args
)
695 def _axi_reg_def(self
, start
, *args
):
697 for (name
, count
) in self
.ifacecount
:
698 for i
in range(count
):
699 if self
.is_on_fastbus(name
, i
):
701 x
= self
.data
[name
].axi_reg_def(start
, i
)
702 #print ("ifc", name, x)
706 return '\n'.join(list(filter(None, ret
)))
708 def _axi_num_idx(self
, start
, template
, typ
, idxtype
, *args
):
710 for (name
, count
) in self
.ifacecount
:
711 for i
in range(count
):
712 if self
.is_on_fastbus(name
, i
):
715 fn
= self
.data
[name
].axi_master_idx
717 fn
= self
.data
[name
].axi_slave_idx
718 (rdef
, offs
) = fn(start
, i
, idxtype
)
719 #print ("ifc", name, rdef, offs)
722 ret
.append("typedef %d LastGen_%s_num;" % (start
- 1, typ
))
723 decls
= '\n'.join(list(filter(None, ret
)))
724 return template
.format(decls
)
726 def axi_slave_idx(self
, *args
):
727 return self
._axi
_num
_idx
(0, axi_slave_declarations
, 'slave',
730 def axi_fastslave_idx(self
, *args
):
731 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
734 def axi_master_idx(self
, *args
):
735 return self
._axi
_num
_idx
(2, axi_master_declarations
, 'master',
738 def axi_fastslave_idx(self
, *args
):
739 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
742 def axi_fastaddr_map(self
, *args
):
744 for (name
, count
) in self
.ifacecount
:
745 for i
in range(count
):
746 if self
.is_on_fastbus(name
, i
):
748 ret
.append(self
.data
[name
].axi_fastaddr_map(i
))
749 return '\n'.join(li(list(filter(None, ret
)), 8))
751 def axi_addr_map(self
, *args
):
753 for (name
, count
) in self
.ifacecount
:
754 for i
in range(count
):
755 if self
.is_on_fastbus(name
, i
):
757 ret
.append(self
.data
[name
].axi_addr_map(i
))
758 return '\n'.join(li(list(filter(None, ret
)), 8))
760 def mkfast_peripheral(self
, *args
):
762 for (name
, count
) in self
.ifacecount
:
763 for i
in range(count
):
764 if self
.is_on_fastbus(name
, i
):
766 #print "mkfast", name, count
767 x
= self
.data
[name
].mkfast_peripheral()
769 suffix
= self
.data
[name
].mksuffix(name
, i
)
770 ret
.append(x
.format(suffix
))
771 return '\n'.join(li(list(filter(None, ret
)), 8))
773 def mkslow_peripheral(self
, *args
):
775 for (name
, count
) in self
.ifacecount
:
776 for i
in range(count
):
777 if self
.is_on_fastbus(name
, i
):
779 #print "mkslow", name, count
780 x
= self
.data
[name
].mkslow_peripheral()
782 suffix
= self
.data
[name
].mksuffix(name
, i
)
783 ret
.append(x
.format(suffix
))
784 return '\n'.join(li(list(filter(None, ret
)), 8))
786 def _mk_connection(self
, fabric
, typ
, indent
, master
, *args
):
788 for (name
, count
) in self
.ifacecount
:
789 for i
in range(count
):
790 if self
.is_on_fastbus(name
, i
):
793 txt
= self
.data
[name
].mk_master_connection(i
, fabric
, typ
)
795 txt
= self
.data
[name
].mk_connection(i
, fabric
, typ
)
799 return '\n'.join(li(list(filter(None, ret
)), indent
))
801 def mk_master_connection(self
, *args
):
802 return self
._mk
_connection
("fabric", "fast", 8, True, *args
)
804 def mk_fast_connection(self
, *args
):
805 return self
._mk
_connection
("fabric", "fast", 12, False, *args
)
807 def mk_connection(self
, *args
):
808 return self
._mk
_connection
("slow_fabric", "", 8, False, *args
)
810 def mk_cellconn(self
):
813 for (name
, count
) in self
.ifacecount
:
814 for i
in range(count
):
815 if self
.is_on_fastbus(name
, i
):
817 res
= self
.data
[name
].mk_cellconn(cellcount
, name
, i
)
820 (txt
, cellcount
) = res
822 ret
= li('\n'.join(list(filter(None, ret
))), 4)
823 return li(pinmux_cellrule
.format(ret
), 4)
826 return self
._mk
_pincon
("slow")
828 def mk_fast_pincon(self
):
829 return self
._mk
_pincon
("fast")
831 def _mk_pincon(self
, typ
):
833 for (name
, count
) in self
.ifacecount
:
834 for i
in range(count
):
835 if self
.is_on_fastbus(name
, i
):
837 txt
= self
.data
[name
]._mk
_pincon
(name
, i
, typ
)
839 return '\n'.join(li(list(filter(None, ret
)), 4))
841 def mk_dma_irq(self
):
849 for (name
, count
) in self
.ifacecount
:
851 for i
in range(count
):
852 if not self
.is_on_fastbus(name
, i
):
854 txt
= self
.data
[name
].mk_dma_sync(name
, i
)
858 txt
= self
.data
[name
].mk_dma_rule(name
, i
)
859 ifacerules
.append(txt
)
860 txt
= self
.data
[name
].mk_dma_connect(name
, i
)
862 ifacerules
= list(filter(None, ifacerules
))
864 txt
= "rule synchronize_%s_interrupts;" % name
867 rules
.append("endrule")
869 cnct
= list(filter(None, cnct
))
871 _cnct
= ["rule rl_connect_interrupt_to_DMA;",
872 " Bit #(%d) lv_interrupt_to_DMA={" % ct
]
875 cnct
= _cnct
+ [spc
+ spcsep
.join(cnct
)]
877 cnct
.append(" dma.interrupt_from_peripherals(\n" +
878 " lv_interrupt_to_DMA);")
879 cnct
.append("endrule;")
881 ret
= list(filter(None, sync
+ rules
+ cnct
))
883 return '\n'.join(ret
)
885 def num_dmachannels(self
):
886 return "`define NUM_DMACHANNELS {0}".format(self
.dma_count
)
888 def mk_ext_ifacedef(self
):
890 for (name
, count
) in self
.ifacecount
:
891 for i
in range(count
):
892 if self
.is_on_fastbus(name
, i
):
894 txt
= self
.data
[name
].mk_ext_ifacedef(name
, i
)
896 return '\n'.join(li(list(filter(None, ret
)), 8))
900 irq_offs
= 8 # XXX: DMA scovers 0-7?
901 for (name
, count
) in self
.ifacecount
:
902 for i
in range(count
):
903 if self
.is_on_fastbus(name
, i
):
905 res
= self
.data
[name
].mk_plic(i
, irq_offs
)
908 (txt
, irq_offs
) = res
910 self
.num_slow_irqs
= irq_offs
911 return '\n'.join(li(list(filter(None, ret
)), 4))
913 def mk_sloirqsdef(self
):
914 return " `define NUM_SLOW_IRQS {0}".format(self
.num_slow_irqs
)
916 def mk_fastclk_con(self
):
917 return self
._mk
_clk
_con
("fast")
919 def mk_slowclk_con(self
):
920 return self
._mk
_clk
_con
("slow")
922 def _mk_clk_con(self
, ctype
):
924 for (name
, count
) in self
.ifacecount
:
925 for i
in range(count
):
926 if self
.is_on_fastbus(name
, i
):
928 txt
= self
.data
[name
]._mk
_clk
_con
(name
, i
, ctype
)
930 return '\n'.join(li(list(filter(None, ret
)), 8))
932 def is_on_fastbus(self
, name
, i
):
933 #print "fastbus mode", self.fastbusmode, name, i
934 iname
= self
.data
[name
].iname().format(i
)
936 return iname
not in self
.fastbus
937 return iname
in self
.fastbus
940 class PFactory(object):
941 def getcls(self
, name
):
942 from uart
import uart
943 from quart
import quart
944 from sdmmc
import sdmmc
946 from eint
import eint
947 from rs232
import rs232
949 from eint
import eint
950 from jtag
import jtag
951 from spi
import spi
, mspi
952 from qspi
import qspi
, mqspi
953 from gpio
import gpio
954 from rgbttl
import rgbttl
955 from flexbus
import flexbus
956 from sdram
import sdram
958 for k
, v
in {'uart': uart
,
975 if name
.startswith(k
):
980 slowfactory
= PFactory()
982 if __name__
== '__main__':
986 i
= PeripheralIface('uart')
988 i
= PeripheralIface('gpioa')