7 if isinstance(txt
, str):
12 line
= line
.split('\n')
17 res
.append(indent
+ line
)
24 def __init__(self
, name
):
27 def extifdecl(self
, name
, count
):
28 sname
= self
.get_iname(count
)
29 return "interface PeripheralSide%s %s;" % (name
.upper(), sname
)
31 def has_axi_master(self
):
37 def mk_dma_irq(self
, name
, count
):
38 if not self
.irq_name():
40 sname
= self
.get_iname(count
)
41 return "{0}_interrupt".format(sname
)
43 def mk_dma_rule(self
, name
, count
):
44 irqname
= self
.mk_dma_irq(name
, count
)
47 pirqname
= self
.irq_name().format(count
)
48 template
= " {0}.send(\n" + \
49 " slow_peripherals.{1});"
50 return template
.format(irqname
, pirqname
)
52 def get_clock_reset(self
, name
, count
):
53 return "slow_clock,slow_reset"
55 def mk_dma_sync(self
, name
, count
):
56 irqname
= self
.mk_dma_irq(name
, count
)
59 sname
= self
.peripheral
.iname().format(count
)
60 template
= "SyncBitIfc#(Bit#(1)) {0} <-\n" + \
61 " <-mkSyncBitToCC({1});"
62 return template
.format(irqname
, self
.get_clock_reset(name
, count
))
64 def mk_dma_connect(self
, name
, count
):
65 irqname
= self
.mk_dma_irq(name
, count
)
68 return "{0}.read".format(irqname
)
70 def fastifdecl(self
, name
, count
):
73 def slowifdeclmux(self
, name
, count
):
79 def num_axi_regs32(self
):
85 def get_iname(self
, inum
):
86 return "{0}{1}".format(self
.name
, self
.mksuffix(self
.name
, inum
))
88 def axibase(self
, name
, ifacenum
):
90 return "%(name)s%(ifacenum)dBase" % locals()
92 def axiend(self
, name
, ifacenum
):
94 return "%(name)s%(ifacenum)dEnd" % locals()
96 def axi_reg_def(self
, start
, name
, ifacenum
):
98 offs
= self
.num_axi_regs32() * 4 * 16
101 end
= start
+ offs
- 1
102 bname
= self
.axibase(name
, ifacenum
)
103 bend
= self
.axiend(name
, ifacenum
)
104 comment
= "%d 32-bit regs" % self
.num_axi_regs32()
105 return (" `define %(bname)s 'h%(start)08X\n"
106 " `define %(bend)s 'h%(end)08X // %(comment)s" % locals(),
109 def axi_master_name(self
, name
, ifacenum
, typ
=''):
111 return "{0}{1}_master_num".format(name
, ifacenum
)
113 def axi_slave_name(self
, name
, ifacenum
, typ
=''):
115 return "{0}{1}_{2}slave_num".format(name
, ifacenum
, typ
)
117 def axi_master_idx(self
, idx
, name
, ifacenum
, typ
):
118 name
= self
.axi_master_name(name
, ifacenum
, typ
)
119 return ("typedef {0} {1};".format(idx
, name
), 1)
121 def axi_slave_idx(self
, idx
, name
, ifacenum
, typ
):
122 name
= self
.axi_slave_name(name
, ifacenum
, typ
)
123 return ("typedef {0} {1};".format(idx
, name
), 1)
125 def axi_fastaddr_map(self
, name
, ifacenum
):
126 return self
.axi_addr_map(name
, ifacenum
, 'fast')
128 def axi_addr_map(self
, name
, ifacenum
, typ
=""):
129 bname
= self
.axibase(name
, ifacenum
)
130 bend
= self
.axiend(name
, ifacenum
)
131 name
= self
.axi_slave_name(name
, ifacenum
, typ
)
133 if(addr>=`{0} && addr<=`{1})
134 return tuple2(True,fromInteger(valueOf({2})));
136 return template
.format(bname
, bend
, name
)
138 def _mk_pincon(self
, name
, count
, ptyp
):
139 # TODO: really should be using bsv.interface_decl.Interfaces
140 # pin-naming rules.... logic here is hard-coded to duplicate
141 # it (see Interface.__init__ outen)
143 for p
in self
.peripheral
.pinspecs
:
146 #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
147 n
= name
# "{0}{1}".format(self.name, self.mksuffix(name, count))
148 ret
.append("//%s %s" % (n
, str(p
)))
150 sname
= self
.get_iname(count
)
151 sname
= "{0}.{1}".format(sname
, pname
)
152 ps
= "slow_peripherals.%s" % sname
154 sname
= self
.peripheral
.iname().format(count
)
155 sname
= "{0}.{1}".format(sname
, pname
)
156 ps
= "pinmux.peripheral_side.%s" % sname
157 if typ
== 'out' or typ
== 'inout':
158 fname
= self
.pinname_out(pname
)
159 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
160 n_
= "{0}{1}".format(n
, count
)
168 cn
= self
._mk
_actual
_connection
('out', name
,
170 pname
, ps_
, n_
, fname
)
174 fname
= self
.pinname_outen(pname
)
176 if isinstance(fname
, str):
177 fname
= "{0}.{1}".format(n_
, fname
)
178 fname
= self
.pinname_tweak(pname
, 'outen', fname
)
179 cn
= self
._mk
_actual
_connection
('outen', name
,
183 if typ
== 'in' or typ
== 'inout':
184 fname
= self
.pinname_in(pname
)
190 n_
= "{0}{1}".format(n
, count
)
191 n_
= '{0}.{1}'.format(n_
, fname
)
192 n_
= self
.ifname_tweak(pname
, 'in', n_
)
193 cn
= self
._mk
_actual
_connection
('in', name
,
195 pname
, ps_
, n_
, fname
)
197 return '\n'.join(ret
)
199 def _mk_vpincon(self
, name
, count
, ptyp
, typ
, pname
, stype
=None):
203 ret
.append("//%s %s %s %s %s" % (name
, ptyp
, typ
, pname
, stype
))
205 sname
= self
.get_iname(count
)
206 ps
= "slow_peripherals.%s" % sname
208 sname
= self
.peripheral
.iname().format(count
)
209 ps
= "pinmux.peripheral_side.%s" % sname
210 n
= self
.get_iname(count
)
212 n
= "{0}.{1}".format(n
, stype
)
213 ps_
= "{0}.{1}".format(ps
, pname
)
214 ret
+= self
._mk
_actual
_connection
(typ
, name
, count
, typ
,
215 pname
, ps_
, n
, stype
)
216 return '\n'.join(ret
)
218 def _mk_actual_connection(self
, ctype
, name
, count
, typ
,
219 pname
, ps
, n
, fname
):
221 ck
= self
.get_clock_reset(name
, count
)
223 if ck
== PBase
.get_clock_reset(self
, name
, count
):
224 ret
.append("mkConnection({0},\n\t\t\t{1}.{2});"
225 .format(ps
, n
, fname
))
227 n2
= "{0}{1}".format(name
, count
)
228 sync
= '{0}_{1}_sync'.format(n2
, pname
)
229 ret
.append("mkConnection({0},\n\t\t\t{1}.get);"
231 ret
.append("mkConnection({0}.put,\n\t\t\t{1}.{2});"
232 .format(sync
, n
, fname
))
233 elif ctype
== 'outen':
234 ret
.append("mkConnection({0}_outen,\n\t\t\t{1});"
237 if ck
== PBase
.get_clock_reset(self
, name
, count
):
238 ret
.append("mkConnection({1},\n\t\t\t{0});".format(
241 n2
= "{0}{1}".format(name
, count
)
242 sync
= '{0}_{1}_sync'.format(n2
, pname
)
243 ret
.append("mkConnection({1}.put,\n\t\t\t{0});".format(
245 ret
.append("mkConnection({1},\n\t\t\t{0}.get);".format(
250 def _mk_clk_con(self
, name
, count
, ctype
):
252 ck
= self
.get_clock_reset(name
, count
)
253 if ck
== PBase
.get_clock_reset(self
, name
, count
):
256 spc
= self
.get_clk_spc(ctype
)
259 ck
= self
.get_clk_spc(ctype
)
261 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
263 for p
in self
.peripheral
.pinspecs
:
267 if typ
== 'out' or typ
== 'inout':
268 fname
= self
.pinname_out(pname
)
271 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
272 n_
= "{0}{1}".format(n
, count
)
275 n_
= '{0}_{1}'.format(n_
, pname
)
276 ret
.append(template
.format("Bit#(1)", n_
, ck
, spc
))
277 if typ
== 'in' or typ
== 'inout':
278 fname
= self
.pinname_in(pname
)
281 #fname = self.pinname_in(pname)
282 n_
= "{0}{1}".format(n
, count
)
283 n_
= '{0}_{1}'.format(n_
, pname
)
284 #n_ = self.ifname_tweak(pname, 'in', n_)
285 ret
.append(template
.format("Bit#(1)", n_
, spc
, ck
))
286 return '\n'.join(ret
)
288 def get_clk_spc(self
, ctype
):
290 return "sp_clock, sp_reset"
292 return "core_clock, core_reset"
294 def _mk_clk_vcon(self
, name
, count
, ctype
, typ
, pname
, bitspec
):
295 ck
= self
.get_clock_reset(name
, count
)
296 if ck
== PBase
.get_clock_reset(self
, name
, count
):
299 spc
= self
.get_clk_spc(ctype
)
302 ck
= self
.get_clk_spc(ctype
)
304 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
307 n_
= "{0}{1}".format(name
, count
)
308 n_
= '{0}_{1}'.format(n_
, pname
)
309 if typ
== 'in' or typ
== 'inout':
311 return template
.format(bitspec
, n_
, ck
, spc
)
314 def mk_cellconn(self
, *args
):
317 def mkfast_peripheral(self
, size
=0):
320 def mkslow_peripheral(self
, size
=0):
323 def mksuffix(self
, name
, i
):
326 def __mk_connection(self
, con
, aname
, fabricname
):
327 txt
= "mkConnection ({2}.v_to_slaves\n" + \
328 " [fromInteger(valueOf({1}))],\n" + \
331 print "PBase __mk_connection", self
.name
, aname
334 return txt
.format(con
, aname
, fabricname
)
336 def __mk_master_connection(self
, con
, aname
, fabricname
):
337 txt
= "mkConnection ({0}, {2}.v_from_masters\n" + \
338 " [fromInteger(valueOf({1}))]);\n"
340 print "PBase __mk_master_connection", self
.name
, aname
343 return txt
.format(con
, aname
, fabricname
)
345 def mk_master_connection(self
, count
, fabricname
, typ
, name
=None):
346 if not self
.has_axi_master():
350 print "PBase mk_master_conn", self
.name
, count
351 aname
= self
.axi_master_name(name
, count
, typ
)
353 connections
= self
._mk
_connection
(name
, count
, True)
354 if not isinstance(connections
, list):
355 connections
= [connections
]
356 for con
in connections
:
357 con
= con
.format(count
, aname
)
358 ret
.append(self
.__mk
_master
_connection
(con
, aname
, fabricname
))
359 return '\n'.join(ret
)
361 def mk_connection(self
, count
, fabricname
, typ
, name
=None):
364 print "PBase mk_conn", self
.name
, count
365 aname
= self
.axi_slave_name(name
, count
, typ
)
367 connections
= self
._mk
_connection
(name
, count
)
368 if not isinstance(connections
, list):
369 connections
= [connections
]
370 for con
in connections
:
371 con
= con
.format(count
, aname
)
372 ret
.append(self
.__mk
_connection
(con
, aname
, fabricname
))
373 return '\n'.join(ret
)
375 def _mk_connection(self
, name
=None, count
=0):
378 def pinname_out(self
, pname
):
381 def pinname_in(self
, pname
):
384 def pinname_outen(self
, pname
):
387 def ifname_tweak(self
, pname
, typ
, txt
):
390 def pinname_tweak(self
, pname
, typ
, txt
):
396 def mk_plic(self
, inum
, irq_offs
):
398 print "mk_plic", self
.name
, inum
, irq_offs
399 niq
= self
.num_irqs()
401 return ('', irq_offs
)
402 name
= self
.get_iname(inum
)
403 res
.append("// PLIC rules for {0}".format(name
))
404 for idx
in range(niq
):
405 plic_obj
= self
.plic_object(name
, idx
)
406 print "plic_obj", name
, idx
, plic_obj
407 plic
= mkplic_rule
.format(name
, plic_obj
, irq_offs
)
409 irq_offs
+= 1 # increment to next irq
410 return ('\n'.join(res
), irq_offs
)
412 def mk_ext_ifacedef(self
, iname
, inum
):
415 def extfastifinstance(self
, name
, count
):
418 def _extifinstance(self
, name
, count
, suffix
, prefix
, samename
=False,
422 pname
= self
.get_iname(count
)
426 sname
= self
.peripheral
.iname().format(count
)
427 template
= "interface {0}{3} = {2}{1}{4};"
428 return template
.format(pname
, sname
, prefix
, suffix
, ifsuffix
)
430 def extifinstance2(self
, name
, count
):
433 def extifinstance(self
, name
, count
):
434 return self
._extifinstance
(name
, count
, "",
435 "pinmux.peripheral_side.")
439 rule rl_connect_{0}_to_plic_{2};
440 if({1} == 1'b1) begin
441 ff_gateway_queue[{2}].enq(1);
442 plic.ifc_external_irq[{2}].irq_frm_gateway(True);
447 axi_master_declarations
= """\
448 typedef 0 Dmem_master_num;
449 typedef 1 Imem_master_num;
451 typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif )
453 typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif )
455 typedef TAdd#(DMA_master_num,1)
459 axi_fastslave_declarations
= """\
461 typedef TAdd#(LastGen_fastslave_num,1) Sdram_slave_num;
462 typedef TAdd#(Sdram_slave_num ,`ifdef SDRAM 1 `else 0 `endif )
464 typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM 1 `else 0 `endif )
466 typedef TAdd#(BootRom_slave_num ,`ifdef Debug 1 `else 0 `endif )
468 typedef TAdd#(Debug_slave_num , `ifdef TCMemory 1 `else 0 `endif )
470 typedef TAdd#(TCM_slave_num ,`ifdef DMA 1 `else 0 `endif )
472 typedef TAdd#(Dma_slave_num ,1 ) SlowPeripheral_slave_num;
473 typedef TAdd#(SlowPeripheral_slave_num,`ifdef VME 1 `else 0 `endif )
475 typedef TAdd#(VME_slave_num,1) Num_Fast_Slaves;
478 axi_slave_declarations
= """\
479 typedef 0 SlowMaster;
481 typedef TAdd#(LastGen_slave_num,`ifdef CLINT 1 `else 0 `endif )
483 typedef TAdd#(CLINT_slave_num ,`ifdef PLIC 1 `else 0 `endif )
485 typedef TAdd#(Plic_slave_num ,`ifdef AXIEXP 1 `else 0 `endif )
487 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
490 pinmux_cellrule
= """\
491 rule connect_select_lines_pinmux;
497 class CallFn(object):
498 def __init__(self
, peripheral
, name
):
499 self
.peripheral
= peripheral
502 def __call__(self
, *args
):
503 #print "__call__", self.name, self.peripheral.slow, args
504 if not self
.peripheral
.slow
:
506 return getattr(self
.peripheral
.slow
, self
.name
)(*args
[1:])
509 class PeripheralIface(object):
510 def __init__(self
, ifacename
):
512 slow
= slowfactory
.getcls(ifacename
)
513 print "Iface", ifacename
, slow
515 self
.slow
= slow(ifacename
)
516 self
.slow
.peripheral
= self
517 for fname
in ['slowimport',
519 'extifinstance2', 'extifinstance', 'extifdecl',
520 'slowifdecl', 'slowifdeclmux',
523 'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule',
525 'mk_plic', 'mk_ext_ifacedef',
526 '_mk_clk_con', 'mk_ext_ifacedef',
527 'mk_connection', 'mk_master_connection',
528 'mk_cellconn', '_mk_pincon']:
529 fn
= CallFn(self
, fname
)
530 setattr(self
, fname
, types
.MethodType(fn
, self
))
532 #print "PeripheralIface"
535 def mksuffix(self
, name
, i
):
536 if self
.slow
is None:
538 return self
.slow
.mksuffix(name
, i
)
540 def axi_reg_def(self
, start
, count
):
543 return self
.slow
.axi_reg_def(start
, self
.ifacename
, count
)
545 def axi_master_idx(self
, start
, count
, typ
):
546 if not self
.slow
or not self
.slow
.has_axi_master():
548 return self
.slow
.axi_master_idx(start
, self
.ifacename
, count
, typ
)
550 def axi_slave_idx(self
, start
, count
, typ
):
553 return self
.slow
.axi_slave_idx(start
, self
.ifacename
, count
, typ
)
555 def axi_fastaddr_map(self
, count
):
558 return self
.slow
.axi_fastaddr_map(self
.ifacename
, count
)
560 def axi_addr_map(self
, count
):
563 return self
.slow
.axi_addr_map(self
.ifacename
, count
)
566 class PeripheralInterfaces(object):
568 self
.fastbusmode
= False
570 def slowimport(self
, *args
):
572 for (name
, count
) in self
.ifacecount
:
573 #print "slowimport", name, self.data[name].slowimport
574 ret
.append(self
.data
[name
].slowimport())
575 return '\n'.join(li(list(filter(None, ret
)), 4))
577 def extfastifinstance(self
, *args
):
579 for (name
, count
) in self
.ifacecount
:
580 for i
in range(count
):
581 iname
= self
.data
[name
].iname().format(i
)
582 print "extfast", iname
, self
.is_on_fastbus(name
, i
)
583 if self
.is_on_fastbus(name
, i
):
585 ret
.append(self
.data
[name
].extfastifinstance(name
, i
))
586 return '\n'.join(li(list(filter(None, ret
)), 8))
588 def extifinstance2(self
, *args
):
590 for (name
, count
) in self
.ifacecount
:
591 for i
in range(count
):
592 iname
= self
.data
[name
].iname().format(i
)
593 ret
.append(self
.data
[name
].extifinstance2(name
, i
))
594 return '\n'.join(li(list(filter(None, ret
)), 8))
596 def extifinstance(self
, *args
):
598 for (name
, count
) in self
.ifacecount
:
599 for i
in range(count
):
600 iname
= self
.data
[name
].iname().format(i
)
601 if not self
.is_on_fastbus(name
, i
):
603 ret
.append(self
.data
[name
].extifinstance(name
, i
))
604 return '\n'.join(li(list(filter(None, ret
)), 8))
606 def extifdecl(self
, *args
):
608 for (name
, count
) in self
.ifacecount
:
609 for i
in range(count
):
610 if not self
.is_on_fastbus(name
, i
):
612 ret
.append(self
.data
[name
].extifdecl(name
, i
))
613 return '\n'.join(li(list(filter(None, ret
)), 8))
615 def slowifdeclmux(self
, *args
):
617 for (name
, count
) in self
.ifacecount
:
618 for i
in range(count
):
619 ret
.append(self
.data
[name
].slowifdeclmux(name
, i
))
620 return '\n'.join(li(list(filter(None, ret
)), 8))
622 def fastifdecl(self
, *args
):
624 for (name
, count
) in self
.ifacecount
:
625 for i
in range(count
):
626 print "fastifdecl", name
, i
, self
.is_on_fastbus(name
, i
)
627 if self
.is_on_fastbus(name
, i
):
629 ret
.append(self
.data
[name
].fastifdecl(name
, i
))
630 return '\n'.join(li(list(filter(None, ret
)), 4))
632 def slowifdecl(self
, *args
):
634 for (name
, count
) in self
.ifacecount
:
635 for i
in range(count
):
636 if self
.is_on_fastbus(name
, i
):
638 ret
.append(self
.data
[name
].slowifdecl().format(i
, name
))
639 return '\n'.join(list(filter(None, ret
)))
641 def axi_fastmem_def(self
, *args
):
642 return self
._axi
_reg
_def
(0x50000000, *args
)
644 def axi_reg_def(self
, *args
):
645 return self
._axi
_reg
_def
(0x00011100, *args
)
647 def _axi_reg_def(self
, start
, *args
):
649 for (name
, count
) in self
.ifacecount
:
650 for i
in range(count
):
651 if self
.is_on_fastbus(name
, i
):
653 x
= self
.data
[name
].axi_reg_def(start
, i
)
654 #print ("ifc", name, x)
658 return '\n'.join(list(filter(None, ret
)))
660 def _axi_num_idx(self
, start
, template
, typ
, idxtype
, *args
):
662 for (name
, count
) in self
.ifacecount
:
663 for i
in range(count
):
664 if self
.is_on_fastbus(name
, i
):
667 fn
= self
.data
[name
].axi_master_idx
669 fn
= self
.data
[name
].axi_slave_idx
670 (rdef
, offs
) = fn(start
, i
, idxtype
)
671 #print ("ifc", name, rdef, offs)
674 ret
.append("typedef %d LastGen_%s_num;" % (start
- 1, typ
))
675 decls
= '\n'.join(list(filter(None, ret
)))
676 return template
.format(decls
)
678 def axi_slave_idx(self
, *args
):
679 return self
._axi
_num
_idx
(0, axi_slave_declarations
, 'slave',
682 def axi_fastslave_idx(self
, *args
):
683 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
686 def axi_master_idx(self
, *args
):
687 return self
._axi
_num
_idx
(2, axi_master_declarations
, 'master',
690 def axi_fastslave_idx(self
, *args
):
691 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
694 def axi_fastaddr_map(self
, *args
):
696 for (name
, count
) in self
.ifacecount
:
697 for i
in range(count
):
698 if self
.is_on_fastbus(name
, i
):
700 ret
.append(self
.data
[name
].axi_fastaddr_map(i
))
701 return '\n'.join(li(list(filter(None, ret
)), 8))
703 def axi_addr_map(self
, *args
):
705 for (name
, count
) in self
.ifacecount
:
706 for i
in range(count
):
707 if self
.is_on_fastbus(name
, i
):
709 ret
.append(self
.data
[name
].axi_addr_map(i
))
710 return '\n'.join(li(list(filter(None, ret
)), 8))
712 def mkfast_peripheral(self
, *args
):
714 for (name
, count
) in self
.ifacecount
:
715 for i
in range(count
):
716 if self
.is_on_fastbus(name
, i
):
718 #print "mkfast", name, count
719 x
= self
.data
[name
].mkfast_peripheral()
721 suffix
= self
.data
[name
].mksuffix(name
, i
)
722 ret
.append(x
.format(suffix
))
723 return '\n'.join(li(list(filter(None, ret
)), 8))
725 def mkslow_peripheral(self
, *args
):
727 for (name
, count
) in self
.ifacecount
:
728 for i
in range(count
):
729 if self
.is_on_fastbus(name
, i
):
731 #print "mkslow", name, count
732 x
= self
.data
[name
].mkslow_peripheral()
734 suffix
= self
.data
[name
].mksuffix(name
, i
)
735 ret
.append(x
.format(suffix
))
736 return '\n'.join(li(list(filter(None, ret
)), 8))
738 def _mk_connection(self
, fabric
, typ
, indent
, master
, *args
):
740 for (name
, count
) in self
.ifacecount
:
741 for i
in range(count
):
742 if self
.is_on_fastbus(name
, i
):
745 txt
= self
.data
[name
].mk_master_connection(i
, fabric
, typ
)
747 txt
= self
.data
[name
].mk_connection(i
, fabric
, typ
)
751 return '\n'.join(li(list(filter(None, ret
)), indent
))
753 def mk_master_connection(self
, *args
):
754 return self
._mk
_connection
("fabric", "fast", 8, True, *args
)
756 def mk_fast_connection(self
, *args
):
757 return self
._mk
_connection
("fabric", "fast", 12, False, *args
)
759 def mk_connection(self
, *args
):
760 return self
._mk
_connection
("slow_fabric", "", 8, False, *args
)
762 def mk_cellconn(self
):
765 for (name
, count
) in self
.ifacecount
:
766 for i
in range(count
):
767 if self
.is_on_fastbus(name
, i
):
769 res
= self
.data
[name
].mk_cellconn(cellcount
, name
, i
)
772 (txt
, cellcount
) = res
774 ret
= li('\n'.join(list(filter(None, ret
))), 4)
775 return li(pinmux_cellrule
.format(ret
), 4)
778 return self
._mk
_pincon
("slow")
780 def mk_fast_pincon(self
):
781 return self
._mk
_pincon
("fast")
783 def _mk_pincon(self
, typ
):
785 for (name
, count
) in self
.ifacecount
:
786 for i
in range(count
):
787 if self
.is_on_fastbus(name
, i
):
789 txt
= self
.data
[name
]._mk
_pincon
(name
, i
, typ
)
791 return '\n'.join(li(list(filter(None, ret
)), 4))
793 def mk_dma_irq(self
):
801 for (name
, count
) in self
.ifacecount
:
803 for i
in range(count
):
804 if not self
.is_on_fastbus(name
, i
):
806 txt
= self
.data
[name
].mk_dma_sync(name
, i
)
810 txt
= self
.data
[name
].mk_dma_rule(name
, i
)
811 ifacerules
.append(txt
)
812 txt
= self
.data
[name
].mk_dma_connect(name
, i
)
814 ifacerules
= list(filter(None, ifacerules
))
816 txt
= "rule synchronize_%s_interrupts;" % name
819 rules
.append("endrule")
821 cnct
= list(filter(None, cnct
))
823 _cnct
= ["rule rl_connect_interrupt_to_DMA;",
824 " Bit #(%d) lv_interrupt_to_DMA={" % ct
]
827 cnct
= _cnct
+ [spc
+ spcsep
.join(cnct
)]
829 cnct
.append(" dma.interrupt_from_peripherals(\n" +
830 " lv_interrupt_to_DMA);")
831 cnct
.append("endrule;")
833 ret
= list(filter(None, sync
+ rules
+ cnct
))
835 return '\n'.join(ret
)
837 def num_dmachannels(self
):
838 return "`define NUM_DMACHANNELS {0}".format(self
.dma_count
)
840 def mk_ext_ifacedef(self
):
842 for (name
, count
) in self
.ifacecount
:
843 for i
in range(count
):
844 if self
.is_on_fastbus(name
, i
):
846 txt
= self
.data
[name
].mk_ext_ifacedef(name
, i
)
848 return '\n'.join(li(list(filter(None, ret
)), 8))
852 irq_offs
= 8 # XXX: DMA scovers 0-7?
853 for (name
, count
) in self
.ifacecount
:
854 for i
in range(count
):
855 if self
.is_on_fastbus(name
, i
):
857 res
= self
.data
[name
].mk_plic(i
, irq_offs
)
860 (txt
, irq_offs
) = res
862 self
.num_slow_irqs
= irq_offs
863 return '\n'.join(li(list(filter(None, ret
)), 4))
865 def mk_sloirqsdef(self
):
866 return " `define NUM_SLOW_IRQS {0}".format(self
.num_slow_irqs
)
868 def mk_fastclk_con(self
):
869 return self
._mk
_clk
_con
("fast")
871 def mk_slowclk_con(self
):
872 return self
._mk
_clk
_con
("slow")
874 def _mk_clk_con(self
, ctype
):
876 for (name
, count
) in self
.ifacecount
:
877 for i
in range(count
):
878 if self
.is_on_fastbus(name
, i
):
880 txt
= self
.data
[name
]._mk
_clk
_con
(name
, i
, ctype
)
882 return '\n'.join(li(list(filter(None, ret
)), 8))
884 def is_on_fastbus(self
, name
, i
):
885 #print "fastbus mode", self.fastbusmode, name, i
886 iname
= self
.data
[name
].iname().format(i
)
888 return iname
not in self
.fastbus
889 return iname
in self
.fastbus
892 class PFactory(object):
893 def getcls(self
, name
):
894 from uart
import uart
895 from quart
import quart
896 from sdmmc
import sdmmc
898 from eint
import eint
899 from rs232
import rs232
901 from eint
import eint
902 from jtag
import jtag
903 from spi
import spi
, mspi
904 from qspi
import qspi
, mqspi
905 from gpio
import gpio
906 from rgbttl
import rgbttl
907 from flexbus
import flexbus
908 from sdram
import sdram
910 for k
, v
in {'uart': uart
,
927 if name
.startswith(k
):
932 slowfactory
= PFactory()
934 if __name__
== '__main__':
938 i
= PeripheralIface('uart')
940 i
= PeripheralIface('gpioa')