src/bsv/peripheral_gen/base.py

   1 import types
   2
   3
   4 def li(txt, indent):
   5     indent = ' ' * indent
   6     istxt = False
   7     if isinstance(txt, str):
   8         istxt = True
   9         txt = txt.split('\n')
  10     res = []
  11     for line in txt:
  12         line = line.split('\n')
  13         res += line
  14     txt = res
  15     res = []
  16     for line in txt:
  17         res.append(indent + line)
  18     if istxt:
  19         res = '\n'.join(res)
  20     return res
  21
  22
  23 class PBase(object):
  24     def __init__(self, name):
  25         self.name = name
  26
  27     def extifdecl(self, name, count):
  28         sname = self.get_iname(count)
  29         return "interface PeripheralSide%s %s;" % (name.upper(), sname)
  30
  31     def has_axi_master(self):
  32         return False
  33
  34     def irq_name(self):
  35         return ""
  36
  37     def mk_dma_irq(self, name, count):
  38         if not self.irq_name():
  39             return ''
  40         sname = self.get_iname(count)
  41         return "{0}_interrupt".format(sname)
  42
  43     def mk_dma_rule(self, name, count):
  44         irqname = self.mk_dma_irq(name, count)
  45         if not irqname:
  46             return ''
  47         pirqname = self.irq_name().format(count)
  48         template = "   {0}_interrupt.send(\n" + \
  49                    "           slow_peripherals.{1});"
  50         return template.format(irqname, pirqname)
  51
  52     def get_clock_reset(self, name, count):
  53         return "slow_clock,slow_reset"
  54
  55     def mk_dma_sync(self, name, count):
  56         irqname = self.mk_dma_irq(name, count)
  57         if not irqname:
  58             return ''
  59         sname = self.peripheral.iname().format(count)
  60         template = "SyncBitIfc#(Bit#(1)) {0} <-\n" + \
  61                    "           <-mkSyncBitToCC({1});"
  62         return template.format(irqname, self.get_clock_reset(name, count))
  63
  64     def mk_dma_connect(self, name, count):
  65         irqname = self.mk_dma_irq(name, count)
  66         if not irqname:
  67             return ''
  68         return "{0}.read".format(irqname)
  69
  70     def fastifdecl(self, name, count):
  71         return ''
  72
  73     def slowifdeclmux(self, name, count):
  74         return ''
  75
  76     def slowimport(self):
  77         return ''
  78
  79     def num_axi_regs32(self):
  80         return 0
  81
  82     def slowifdecl(self):
  83         return ''
  84
  85     def get_iname(self, inum):
  86         return "{0}{1}".format(self.name, self.mksuffix(self.name, inum))
  87
  88     def axibase(self, name, ifacenum):
  89         name = name.upper()
  90         return "%(name)s%(ifacenum)dBase" % locals()
  91
  92     def axiend(self, name, ifacenum):
  93         name = name.upper()
  94         return "%(name)s%(ifacenum)dEnd" % locals()
  95
  96     def axi_reg_def(self, start, name, ifacenum):
  97         name = name.upper()
  98         offs = self.num_axi_regs32() * 4 * 16
  99         if offs == 0:
 100             return ('', 0)
 101         end = start + offs - 1
 102         bname = self.axibase(name, ifacenum)
 103         bend = self.axiend(name, ifacenum)
 104         comment = "%d 32-bit regs" % self.num_axi_regs32()
 105         return ("    `define %(bname)s 'h%(start)08X\n"
 106                 "    `define %(bend)s  'h%(end)08X // %(comment)s" % locals(),
 107                 offs)
 108
 109     def axi_master_name(self, name, ifacenum, typ=''):
 110         name = name.upper()
 111         return "{0}{1}_master_num".format(name, ifacenum)
 112
 113     def axi_slave_name(self, name, ifacenum, typ=''):
 114         name = name.upper()
 115         return "{0}{1}_{2}slave_num".format(name, ifacenum, typ)
 116
 117     def axi_master_idx(self, idx, name, ifacenum, typ):
 118         name = self.axi_master_name(name, ifacenum, typ)
 119         return ("typedef {0} {1};".format(idx, name), 1)
 120
 121     def axi_slave_idx(self, idx, name, ifacenum, typ):
 122         name = self.axi_slave_name(name, ifacenum, typ)
 123         return ("typedef {0} {1};".format(idx, name), 1)
 124
 125     def axi_addr_map(self, name, ifacenum):
 126         bname = self.axibase(name, ifacenum)
 127         bend = self.axiend(name, ifacenum)
 128         name = self.axi_slave_name(name, ifacenum)
 129         template = """\
 130 if(addr>=`{0} && addr<=`{1})
 131     return tuple2(True,fromInteger(valueOf({2})));
 132 else"""
 133         return template.format(bname, bend, name)
 134
 135     def mk_pincon(self, name, count):
 136         # TODO: really should be using bsv.interface_decl.Interfaces
 137         # pin-naming rules.... logic here is hard-coded to duplicate
 138         # it (see Interface.__init__ outen)
 139         ret = []
 140         for p in self.peripheral.pinspecs:
 141             typ = p['type']
 142             pname = p['name']
 143             #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
 144             n = name  # "{0}{1}".format(self.name, self.mksuffix(name, count))
 145             ret.append("//%s %s" % (n, str(p)))
 146             sname = self.peripheral.iname().format(count)
 147             sname = "{0}.{1}".format(sname, pname)
 148             ps = "pinmux.peripheral_side.%s" % sname
 149             if typ == 'out' or typ == 'inout':
 150                 fname = self.pinname_out(pname)
 151                 if not n.startswith('gpio'):  # XXX EURGH! horrible hack
 152                     n_ = "{0}{1}".format(n, count)
 153                 else:
 154                     n_ = n
 155                 if fname:
 156                     if p.get('outen'):
 157                         ps_ = ps + '_out'
 158                     else:
 159                         ps_ = ps
 160                     ret.append("mkConnection({0},\n\t\t\t{1}.{2});"
 161                                .format(ps_, n_, fname))
 162                 fname = None
 163                 if p.get('outen'):
 164                     fname = self.pinname_outen(pname)
 165                 if fname:
 166                     if isinstance(fname, str):
 167                         fname = "{0}.{1}".format(n_, fname)
 168                     fname = self.pinname_tweak(pname, 'outen', fname)
 169                     ret.append("mkConnection({0}_outen,\n\t\t\t{1});"
 170                                .format(ps, fname))
 171             if typ == 'in' or typ == 'inout':
 172                 fname = self.pinname_in(pname)
 173                 if fname:
 174                     if p.get('outen'):
 175                         ps_ = ps + '_in'
 176                     else:
 177                         ps_ = ps
 178                     n_ = "{0}{1}".format(n, count)
 179                     n_ = '{0}.{1}'.format(n_, fname)
 180                     n_ = self.ifname_tweak(pname, 'in', n_)
 181                     ret.append("mkConnection({1},\n\t\t\t{0});".format(ps_, n_))
 182         return '\n'.join(ret)
 183
 184     def mk_cellconn(self, *args):
 185         return ''
 186
 187     def mkfast_peripheral(self, size=0):
 188         return ''
 189
 190     def mkslow_peripheral(self, size=0):
 191         return ''
 192
 193     def mksuffix(self, name, i):
 194         return i
 195
 196     def __mk_connection(self, con, aname, fabricname):
 197         txt = "mkConnection ({2}.v_to_slaves\n" + \
 198               "            [fromInteger(valueOf({1}))],\n" + \
 199               "            {0});"
 200
 201         print "PBase __mk_connection", self.name, aname
 202         if not con:
 203             return ''
 204         return txt.format(con, aname, fabricname)
 205
 206     def __mk_master_connection(self, con, aname):
 207         txt = "mkConnection (slow_fabric.v_to_slaves\n" + \
 208               "            [fromInteger(valueOf({1}))],\n" + \
 209               "            {0});"
 210
 211         print "PBase __mk_connection", self.name, aname
 212         if not con:
 213             return ''
 214         return txt.format(con, aname)
 215
 216     def mk_connection(self, count, fabricname, typ, name=None):
 217         if name is None:
 218             name = self.name
 219         print "PBase mk_conn", self.name, count
 220         aname = self.axi_slave_name(name, count, typ)
 221         #dname = self.mksuffix(name, count)
 222         #dname = "{0}{1}".format(name, dname)
 223         con = self._mk_connection(name, count).format(count, aname)
 224         return self.__mk_connection(con, aname, fabricname)
 225
 226     def _mk_connection(self, name=None, count=0):
 227         return ''
 228
 229     def pinname_out(self, pname):
 230         return ''
 231
 232     def pinname_in(self, pname):
 233         return ''
 234
 235     def pinname_outen(self, pname):
 236         return ''
 237
 238     def ifname_tweak(self, pname, typ, txt):
 239         return txt
 240
 241     def pinname_tweak(self, pname, typ, txt):
 242         return txt
 243
 244     def num_irqs(self):
 245         return 0
 246
 247     def mk_plic(self, inum, irq_offs):
 248         res = []
 249         print "mk_plic", self.name, inum, irq_offs
 250         niq = self.num_irqs()
 251         if niq == 0:
 252             return ('', irq_offs)
 253         name = self.get_iname(inum)
 254         res.append("// PLIC rules for {0}".format(name))
 255         for idx in range(niq):
 256             plic_obj = self.plic_object(name, idx)
 257             print "plic_obj", name, idx, plic_obj
 258             plic = mkplic_rule.format(name, plic_obj, irq_offs)
 259             res.append(plic)
 260             irq_offs += 1  # increment to next irq
 261         return ('\n'.join(res), irq_offs)
 262
 263     def mk_ext_ifacedef(self, iname, inum):
 264         return ''
 265
 266     def extfastifinstance(self, name, count):
 267         return ''
 268
 269     def _extifinstance(self, name, count, suffix, prefix, samename=False,
 270                        ifsuffix=None):
 271         if ifsuffix is None:
 272             ifsuffix = ''
 273         pname = self.get_iname(count)
 274         if samename:
 275             sname = pname
 276         else:
 277             sname = self.peripheral.iname().format(count)
 278         template = "interface {0}{3} = {2}{1}{4};"
 279         return template.format(pname, sname, prefix, suffix, ifsuffix)
 280
 281     def extifinstance2(self, name, count):
 282         return ''
 283
 284     def extifinstance(self, name, count):
 285         return self._extifinstance(name, count, "",
 286                                    "pinmux.peripheral_side.")
 287
 288
 289 mkplic_rule = """\
 290 rule rl_connect_{0}_to_plic_{2};
 291    if({1} == 1'b1) begin
 292        ff_gateway_queue[{2}].enq(1);
 293        plic.ifc_external_irq[{2}].irq_frm_gateway(True);
 294    end
 295 endrule
 296 """
 297
 298 axi_master_declarations = """\
 299 typedef 0 Dmem_master_num;
 300 typedef 1 Imem_master_num;
 301 {0}
 302 typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif )
 303                 Debug_master_num;
 304 typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif )
 305                 DMA_master_num;
 306 typedef TAdd#(DMA_master_num,1)
 307                 Num_Masters;
 308 """
 309
 310 axi_fastslave_declarations = """\
 311 {0}
 312 typedef  TAdd#(LastGen_fastslave_num,1)      Sdram_cfg_slave_num;
 313 typedef  TAdd#(Sdram_slave_num   ,`ifdef SDRAM      1 `else 0 `endif )
 314                       Sdram_cfg_slave_num;
 315 typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM    1 `else 0 `endif )
 316                 BootRom_slave_num   ;
 317 typedef TAdd#(BootRom_slave_num  ,`ifdef Debug      1 `else 0 `endif )
 318                 Debug_slave_num ;
 319 typedef  TAdd#(Debug_slave_num   , `ifdef TCMemory  1 `else 0 `endif )
 320                 TCM_slave_num;
 321 typedef  TAdd#(TCM_slave_num     ,`ifdef DMA            1 `else 0 `endif )
 322                 Dma_slave_num;
 323 typedef  TAdd#(Dma_slave_num      ,1 )      SlowPeripheral_slave_num;
 324 typedef  TAdd#(SlowPeripheral_slave_num,`ifdef VME  1 `else 0 `endif )
 325                 VME_slave_num;
 326 typedef  TAdd#(VME_slave_num,`ifdef FlexBus 1 `else 0 `endif )
 327                 FlexBus_slave_num;
 328 typedef TAdd#(FlexBus_slave_num,1)
 329                 Num_Slaves;
 330
 331 """
 332
 333 axi_slave_declarations = """\
 334 typedef  0  SlowMaster;
 335 {0}
 336 typedef  TAdd#(LastGen_slave_num,`ifdef CLINT       1 `else 0 `endif )
 337               CLINT_slave_num;
 338 typedef  TAdd#(CLINT_slave_num  ,`ifdef PLIC        1 `else 0 `endif )
 339               Plic_slave_num;
 340 typedef  TAdd#(Plic_slave_num   ,`ifdef AXIEXP      1 `else 0 `endif )
 341               AxiExp1_slave_num;
 342 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
 343 """
 344
 345 pinmux_cellrule = """\
 346 rule connect_select_lines_pinmux;
 347 {0}
 348 endrule
 349 """
 350
 351
 352 class CallFn(object):
 353     def __init__(self, peripheral, name):
 354         self.peripheral = peripheral
 355         self.name = name
 356
 357     def __call__(self, *args):
 358         #print "__call__", self.name, self.peripheral.slow, args
 359         if not self.peripheral.slow:
 360             return ''
 361         return getattr(self.peripheral.slow, self.name)(*args[1:])
 362
 363
 364 class PeripheralIface(object):
 365     def __init__(self, ifacename):
 366         self.slow = None
 367         slow = slowfactory.getcls(ifacename)
 368         print "Iface", ifacename, slow
 369         if slow:
 370             self.slow = slow(ifacename)
 371             self.slow.peripheral = self
 372         for fname in ['slowimport',
 373                       'extfastifinstance',
 374                       'extifinstance2', 'extifinstance', 'extifdecl',
 375                       'slowifdecl', 'slowifdeclmux',
 376                       'fastifdecl',
 377                       'mkslow_peripheral',
 378                       'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule',
 379                       'mkfast_peripheral',
 380                       'mk_plic', 'mk_ext_ifacedef',
 381                       'mk_connection', 'mk_cellconn', 'mk_pincon']:
 382             fn = CallFn(self, fname)
 383             setattr(self, fname, types.MethodType(fn, self))
 384
 385         #print "PeripheralIface"
 386         #print dir(self)
 387
 388     def mksuffix(self, name, i):
 389         if self.slow is None:
 390             return i
 391         return self.slow.mksuffix(name, i)
 392
 393     def axi_reg_def(self, start, count):
 394         if not self.slow:
 395             return ('', 0)
 396         return self.slow.axi_reg_def(start, self.ifacename, count)
 397
 398     def axi_master_idx(self, start, count, typ):
 399         if not self.slow or not self.slow.has_axi_master():
 400             return ('', 0)
 401         return self.slow.axi_master_idx(start, self.ifacename, count, typ)
 402
 403     def axi_slave_idx(self, start, count, typ):
 404         if not self.slow:
 405             return ('', 0)
 406         return self.slow.axi_slave_idx(start, self.ifacename, count, typ)
 407
 408     def axi_addr_map(self, count):
 409         if not self.slow:
 410             return ''
 411         return self.slow.axi_addr_map(self.ifacename, count)
 412
 413
 414 class PeripheralInterfaces(object):
 415     def __init__(self):
 416         self.fastbusmode = False
 417
 418     def slowimport(self, *args):
 419         ret = []
 420         for (name, count) in self.ifacecount:
 421             #print "slowimport", name, self.data[name].slowimport
 422             ret.append(self.data[name].slowimport())
 423         return '\n'.join(li(list(filter(None, ret)), 4))
 424
 425     def extfastifinstance(self, *args):
 426         ret = []
 427         for (name, count) in self.ifacecount:
 428             for i in range(count):
 429                 iname = self.data[name].iname().format(i)
 430                 print "extfast", iname, self.is_on_fastbus(name, i)
 431                 if self.is_on_fastbus(name, i):
 432                     continue
 433                 ret.append(self.data[name].extfastifinstance(name, i))
 434         return '\n'.join(li(list(filter(None, ret)), 8))
 435
 436     def extifinstance2(self, *args):
 437         ret = []
 438         for (name, count) in self.ifacecount:
 439             for i in range(count):
 440                 iname = self.data[name].iname().format(i)
 441                 ret.append(self.data[name].extifinstance2(name, i))
 442         return '\n'.join(li(list(filter(None, ret)), 8))
 443
 444     def extifinstance(self, *args):
 445         ret = []
 446         for (name, count) in self.ifacecount:
 447             for i in range(count):
 448                 iname = self.data[name].iname().format(i)
 449                 if not self.is_on_fastbus(name, i):
 450                     continue
 451                 ret.append(self.data[name].extifinstance(name, i))
 452         return '\n'.join(li(list(filter(None, ret)), 8))
 453
 454     def extifdecl(self, *args):
 455         ret = []
 456         for (name, count) in self.ifacecount:
 457             for i in range(count):
 458                 if not self.is_on_fastbus(name, i):
 459                     continue
 460                 ret.append(self.data[name].extifdecl(name, i))
 461         return '\n'.join(li(list(filter(None, ret)), 8))
 462
 463     def slowifdeclmux(self, *args):
 464         ret = []
 465         for (name, count) in self.ifacecount:
 466             for i in range(count):
 467                 ret.append(self.data[name].slowifdeclmux(name, i))
 468         return '\n'.join(li(list(filter(None, ret)), 8))
 469
 470     def fastifdecl(self, *args):
 471         ret = []
 472         for (name, count) in self.ifacecount:
 473             for i in range(count):
 474                 print "fastifdecl", name, i, self.is_on_fastbus(name, i)
 475                 if self.is_on_fastbus(name, i):
 476                     continue
 477                 ret.append(self.data[name].fastifdecl(name, i))
 478         return '\n'.join(li(list(filter(None, ret)), 4))
 479
 480     def slowifdecl(self, *args):
 481         ret = []
 482         for (name, count) in self.ifacecount:
 483             for i in range(count):
 484                 if self.is_on_fastbus(name, i):
 485                     continue
 486                 ret.append(self.data[name].slowifdecl().format(i, name))
 487         return '\n'.join(list(filter(None, ret)))
 488
 489     def axi_reg_def(self, *args):
 490         ret = []
 491         start = 0x00011100  # start of AXI peripherals address
 492         for (name, count) in self.ifacecount:
 493             for i in range(count):
 494                 if self.is_on_fastbus(name, i):
 495                     continue
 496                 x = self.data[name].axi_reg_def(start, i)
 497                 #print ("ifc", name, x)
 498                 (rdef, offs) = x
 499                 ret.append(rdef)
 500                 start += offs
 501         return '\n'.join(list(filter(None, ret)))
 502
 503     def _axi_num_idx(self, start, template, typ, idxtype, *args):
 504         ret = []
 505         for (name, count) in self.ifacecount:
 506             for i in range(count):
 507                 if self.is_on_fastbus(name, i):
 508                     continue
 509                 if typ == 'master':
 510                     fn = self.data[name].axi_master_idx
 511                 else:
 512                     fn = self.data[name].axi_slave_idx
 513                 (rdef, offs) = fn(start, i, idxtype)
 514                 #print ("ifc", name, rdef, offs)
 515                 ret.append(rdef)
 516                 start += offs
 517         ret.append("typedef %d LastGen_%s_num;" % (start - 1, typ))
 518         decls = '\n'.join(list(filter(None, ret)))
 519         return template.format(decls)
 520
 521     def axi_slave_idx(self, *args):
 522         return self._axi_num_idx(0, axi_slave_declarations, 'slave',
 523                                  '', *args)
 524
 525     def axi_fastslave_idx(self, *args):
 526         return self._axi_num_idx(0, axi_fastslave_declarations, 'fastslave',
 527                                  'fast', *args)
 528
 529     def axi_master_idx(self, *args):
 530         return self._axi_num_idx(2, axi_master_declarations, 'master',
 531                                  'master', *args)
 532
 533     def axi_fastslave_idx(self, *args):
 534         return self._axi_num_idx(0, axi_fastslave_declarations, 'fastslave',
 535                                  'fast', *args)
 536
 537     def axi_addr_map(self, *args):
 538         ret = []
 539         for (name, count) in self.ifacecount:
 540             for i in range(count):
 541                 if self.is_on_fastbus(name, i):
 542                     continue
 543                 ret.append(self.data[name].axi_addr_map(i))
 544         return '\n'.join(li(list(filter(None, ret)), 8))
 545
 546     def mkfast_peripheral(self, *args):
 547         ret = []
 548         for (name, count) in self.ifacecount:
 549             for i in range(count):
 550                 if self.is_on_fastbus(name, i):
 551                     continue
 552                 #print "mkfast", name, count
 553                 x = self.data[name].mkfast_peripheral()
 554                 print name, count, x
 555                 suffix = self.data[name].mksuffix(name, i)
 556                 ret.append(x.format(suffix))
 557         return '\n'.join(li(list(filter(None, ret)), 8))
 558
 559     def mkslow_peripheral(self, *args):
 560         ret = []
 561         for (name, count) in self.ifacecount:
 562             for i in range(count):
 563                 if self.is_on_fastbus(name, i):
 564                     continue
 565                 #print "mkslow", name, count
 566                 x = self.data[name].mkslow_peripheral()
 567                 print name, count, x
 568                 suffix = self.data[name].mksuffix(name, i)
 569                 ret.append(x.format(suffix))
 570         return '\n'.join(li(list(filter(None, ret)), 8))
 571
 572     def mk_fast_connection(self, *args):
 573         ret = []
 574         for (name, count) in self.ifacecount:
 575             for i in range(count):
 576                 if self.is_on_fastbus(name, i):
 577                     continue
 578                 txt = self.data[name].mk_connection(i, "fabric", "fast")
 579                 if name == 'gpioa':
 580                     print "txt", txt
 581                     print self.data[name].mk_connection
 582                 ret.append(txt)
 583         return '\n'.join(li(list(filter(None, ret)), 12))
 584
 585     def mk_connection(self, *args):
 586         ret = []
 587         for (name, count) in self.ifacecount:
 588             for i in range(count):
 589                 if self.is_on_fastbus(name, i):
 590                     continue
 591                 txt = self.data[name].mk_connection(i, "slow_fabric", "")
 592                 if name == 'gpioa':
 593                     print "txt", txt
 594                     print self.data[name].mk_connection
 595                 ret.append(txt)
 596         return '\n'.join(li(list(filter(None, ret)), 8))
 597
 598     def mk_cellconn(self):
 599         ret = []
 600         cellcount = 0
 601         for (name, count) in self.ifacecount:
 602             for i in range(count):
 603                 if self.is_on_fastbus(name, i):
 604                     continue
 605                 res = self.data[name].mk_cellconn(cellcount, name, i)
 606                 if not res:
 607                     continue
 608                 (txt, cellcount) = res
 609                 ret.append(txt)
 610         ret = li('\n'.join(list(filter(None, ret))), 4)
 611         return li(pinmux_cellrule.format(ret), 4)
 612
 613     def mk_pincon(self):
 614         ret = []
 615         for (name, count) in self.ifacecount:
 616             for i in range(count):
 617                 if self.is_on_fastbus(name, i):
 618                     continue
 619                 txt = self.data[name].mk_pincon(name, i)
 620                 ret.append(txt)
 621         return '\n'.join(li(list(filter(None, ret)), 4))
 622
 623     def mk_dma_irq(self):
 624         ret = []
 625         sync = []
 626         rules = []
 627         cnct = []
 628
 629         self.dma_count = 0
 630
 631         for (name, count) in self.ifacecount:
 632             ifacerules = []
 633             for i in range(count):
 634                 if not self.is_on_fastbus(name, i):
 635                     continue
 636                 txt = self.data[name].mk_dma_sync(name, i)
 637                 if txt:
 638                     self.dma_count += 1
 639                 sync.append(txt)
 640                 txt = self.data[name].mk_dma_rule(name, i)
 641                 ifacerules.append(txt)
 642                 txt = self.data[name].mk_dma_connect(name, i)
 643                 cnct.append(txt)
 644             ifacerules = list(filter(None, ifacerules))
 645             if ifacerules:
 646                 txt = "rule synchronize_%s_interrupts;" % name
 647                 rules.append(txt)
 648                 rules += ifacerules
 649                 rules.append("endrule")
 650
 651         cnct = list(filter(None, cnct))
 652         ct = self.dma_count
 653         _cnct = ["rule rl_connect_interrupt_to_DMA;",
 654                  "  Bit #(%d) lv_interrupt_to_DMA={" % ct]
 655         spc = "                      "
 656         spcsep = ",\n" + spc
 657         cnct = _cnct + [spc + spcsep.join(cnct)]
 658         cnct.append("   };")
 659         cnct.append("   dma.interrupt_from_peripherals(\n" +
 660                     "       lv_interrupt_to_DMA);")
 661         cnct.append("endrule;")
 662
 663         ret = list(filter(None, sync + rules + cnct))
 664         ret = li(ret, 15)
 665         return '\n'.join(ret)
 666
 667     def num_dmachannels(self):
 668         return "`define NUM_DMACHANNELS {0}".format(self.dma_count)
 669
 670     def mk_ext_ifacedef(self):
 671         ret = []
 672         for (name, count) in self.ifacecount:
 673             for i in range(count):
 674                 if self.is_on_fastbus(name, i):
 675                     continue
 676                 txt = self.data[name].mk_ext_ifacedef(name, i)
 677                 ret.append(txt)
 678         return '\n'.join(li(list(filter(None, ret)), 8))
 679
 680     def mk_plic(self):
 681         ret = []
 682         irq_offs = 8  # XXX: DMA scovers 0-7?
 683         for (name, count) in self.ifacecount:
 684             for i in range(count):
 685                 if self.is_on_fastbus(name, i):
 686                     continue
 687                 res = self.data[name].mk_plic(i, irq_offs)
 688                 if not res:
 689                     continue
 690                 (txt, irq_offs) = res
 691                 ret.append(txt)
 692         self.num_slow_irqs = irq_offs
 693         return '\n'.join(li(list(filter(None, ret)), 4))
 694
 695     def mk_sloirqsdef(self):
 696         return "    `define NUM_SLOW_IRQS {0}".format(self.num_slow_irqs)
 697
 698     def is_on_fastbus(self, name, i):
 699         #print "fastbus mode", self.fastbusmode, name, i
 700         iname = self.data[name].iname().format(i)
 701         if self.fastbusmode:
 702             return iname not in self.fastbus
 703         return iname in self.fastbus
 704
 705
 706 class PFactory(object):
 707     def getcls(self, name):
 708         from uart import uart
 709         from quart import quart
 710         from sdmmc import sdmmc
 711         from pwm import pwm
 712         from eint import eint
 713         from rs232 import rs232
 714         from twi import twi
 715         from eint import eint
 716         from jtag import jtag
 717         from spi import spi, mspi
 718         from qspi import qspi, mqspi
 719         from gpio import gpio
 720         from rgbttl import rgbttl
 721         from flexbus import flexbus
 722
 723         for k, v in {'uart': uart,
 724                      'rs232': rs232,
 725                      'twi': twi,
 726                      'quart': quart,
 727                      'mqspi': mqspi,
 728                      'mspi': mspi,
 729                      'qspi': qspi,
 730                      'spi': spi,
 731                      'pwm': pwm,
 732                      'eint': eint,
 733                      'sd': sdmmc,
 734                      'jtag': jtag,
 735                      'lcd': rgbttl,
 736                      'fb': flexbus,
 737                      'gpio': gpio
 738                      }.items():
 739             if name.startswith(k):
 740                 return v
 741         return None
 742
 743
 744 slowfactory = PFactory()
 745
 746 if __name__ == '__main__':
 747     p = uart('uart')
 748     print p.slowimport()
 749     print p.slowifdecl()
 750     i = PeripheralIface('uart')
 751     print i, i.slow
 752     i = PeripheralIface('gpioa')
 753     print i, i.slow