7 if isinstance(txt
, str):
12 line
= line
.split('\n')
17 res
.append(indent
+ line
)
24 def __init__(self
, name
):
27 def extifdecl(self
, name
, count
):
28 sname
= self
.get_iname(count
)
29 return "interface PeripheralSide%s %s;" % (name
.upper(), sname
)
31 def has_axi_master(self
):
37 def mk_dma_irq(self
, name
, count
):
38 if not self
.irq_name():
40 sname
= self
.get_iname(count
)
41 return "{0}_interrupt".format(sname
)
43 def mk_dma_rule(self
, name
, count
):
44 irqname
= self
.mk_dma_irq(name
, count
)
47 pirqname
= self
.irq_name().format(count
)
48 template
= " {0}.send(\n" + \
49 " slow_peripherals.{1});"
50 return template
.format(irqname
, pirqname
)
52 def get_clock_reset(self
, name
, count
):
53 return "slow_clock,slow_reset"
55 def mk_dma_sync(self
, name
, count
):
56 irqname
= self
.mk_dma_irq(name
, count
)
59 sname
= self
.peripheral
.iname().format(count
)
60 template
= "SyncBitIfc#(Bit#(1)) {0} <-\n" + \
61 " <-mkSyncBitToCC({1});"
62 return template
.format(irqname
, self
.get_clock_reset(name
, count
))
64 def mk_dma_connect(self
, name
, count
):
65 irqname
= self
.mk_dma_irq(name
, count
)
68 return "{0}.read".format(irqname
)
70 def fastifdecl(self
, name
, count
):
73 def slowifdeclmux(self
, name
, count
):
79 def num_axi_regs32(self
):
85 def get_iname(self
, inum
):
86 return "{0}{1}".format(self
.name
, self
.mksuffix(self
.name
, inum
))
88 def axibase(self
, name
, ifacenum
):
90 return "%(name)s%(ifacenum)dBase" % locals()
92 def axiend(self
, name
, ifacenum
):
94 return "%(name)s%(ifacenum)dEnd" % locals()
96 def axi_reg_def(self
, start
, name
, ifacenum
):
98 offs
= self
.num_axi_regs32() * 4 * 16
101 end
= start
+ offs
- 1
102 bname
= self
.axibase(name
, ifacenum
)
103 bend
= self
.axiend(name
, ifacenum
)
104 comment
= "%d 32-bit regs" % self
.num_axi_regs32()
105 return (" `define %(bname)s 'h%(start)08X\n"
106 " `define %(bend)s 'h%(end)08X // %(comment)s" % locals(),
109 def axi_master_name(self
, name
, ifacenum
, typ
=''):
111 return "{0}{1}_master_num".format(name
, ifacenum
)
113 def axi_slave_name(self
, name
, ifacenum
, typ
=''):
115 return "{0}{1}_{2}slave_num".format(name
, ifacenum
, typ
)
117 def axi_master_idx(self
, idx
, name
, ifacenum
, typ
):
118 name
= self
.axi_master_name(name
, ifacenum
, typ
)
119 return ("typedef {0} {1};".format(idx
, name
), 1)
121 def axi_slave_idx(self
, idx
, name
, ifacenum
, typ
):
122 name
= self
.axi_slave_name(name
, ifacenum
, typ
)
123 return ("typedef {0} {1};".format(idx
, name
), 1)
125 def axi_fastaddr_map(self
, name
, ifacenum
):
126 return self
.axi_addr_map(name
, ifacenum
, 'fast')
128 def axi_addr_map(self
, name
, ifacenum
, typ
=""):
129 bname
= self
.axibase(name
, ifacenum
)
130 bend
= self
.axiend(name
, ifacenum
)
131 name
= self
.axi_slave_name(name
, ifacenum
, typ
)
133 if(addr>=`{0} && addr<=`{1})
134 return tuple2(True,fromInteger(valueOf({2})));
136 return template
.format(bname
, bend
, name
)
138 def _mk_pincon(self
, name
, count
, ptyp
):
139 # TODO: really should be using bsv.interface_decl.Interfaces
140 # pin-naming rules.... logic here is hard-coded to duplicate
141 # it (see Interface.__init__ outen)
143 for p
in self
.peripheral
.pinspecs
:
146 #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
147 n
= name
# "{0}{1}".format(self.name, self.mksuffix(name, count))
148 ret
.append("//%s %s" % (n
, str(p
)))
150 sname
= self
.get_iname(count
)
151 sname
= "{0}.{1}".format(sname
, pname
)
152 ps
= "slow_peripherals.%s" % sname
154 sname
= self
.peripheral
.iname().format(count
)
155 sname
= "{0}.{1}".format(sname
, pname
)
156 ps
= "pinmux.peripheral_side.%s" % sname
157 if typ
== 'out' or typ
== 'inout':
158 fname
= self
.pinname_out(pname
)
159 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
160 n_
= "{0}{1}".format(n
, count
)
168 cn
= self
._mk
_actual
_connection
('out', name
,
170 pname
, ps_
, n_
, fname
)
174 fname
= self
.pinname_outen(pname
)
176 if isinstance(fname
, str):
177 fname
= "{0}.{1}".format(n_
, fname
)
178 fname
= self
.pinname_tweak(pname
, 'outen', fname
)
179 cn
= self
._mk
_actual
_connection
('outen', name
,
183 if typ
== 'in' or typ
== 'inout':
184 fname
= self
.pinname_in(pname
)
190 n_
= "{0}{1}".format(n
, count
)
191 n_
= '{0}.{1}'.format(n_
, fname
)
192 n_
= self
.ifname_tweak(pname
, 'in', n_
)
193 cn
= self
._mk
_actual
_connection
('in', name
,
195 pname
, ps_
, n_
, fname
)
197 return '\n'.join(ret
)
199 def _mk_vpincon(self
, name
, count
, ptyp
, typ
, pname
, stype
=None):
203 ret
.append("//%s %s %s %s %s" % (name
, ptyp
, typ
, pname
, stype
))
205 sname
= self
.get_iname(count
)
206 ps
= "slow_peripherals.%s" % sname
208 sname
= self
.peripheral
.iname().format(count
)
209 ps
= "pinmux.peripheral_side.%s" % sname
210 n
= self
.get_iname(count
)
212 n
= "{0}.{1}".format(n
, stype
)
213 ps_
= "{0}.{1}".format(ps
, pname
)
214 ret
+= self
._mk
_actual
_connection
(typ
, name
, count
, typ
,
215 pname
, ps_
, n
, stype
)
216 return '\n'.join(ret
)
218 def _mk_actual_connection(self
, ctype
, name
, count
, typ
,
219 pname
, ps
, n
, fname
):
221 ck
= self
.get_clock_reset(name
, count
)
223 if ck
== PBase
.get_clock_reset(self
, name
, count
):
224 ret
.append("mkConnection({0},\n\t\t\t{1}.{2});"
225 .format(ps
, n
, fname
))
227 n2
= "{0}{1}".format(name
, count
)
228 sync
= '{0}_{1}_sync'.format(n2
, pname
)
229 ret
.append("mkConnection({0},\n\t\t\t{1}.get);"
231 ret
.append("mkConnection({0}.put,\n\t\t\t{1}.{2});"
232 .format(sync
, n
, fname
))
233 elif ctype
== 'outen':
234 ret
.append("mkConnection({0}_outen,\n\t\t\t{1});"
237 if ck
== PBase
.get_clock_reset(self
, name
, count
):
238 ret
.append("mkConnection({1},\n\t\t\t{0});".format(
241 n2
= "{0}{1}".format(name
, count
)
242 sync
= '{0}_{1}_sync'.format(n2
, pname
)
243 ret
.append("mkConnection({1}.put,\n\t\t\t{0});".format(
245 ret
.append("mkConnection({1},\n\t\t\t{0}.get);".format(
250 def _mk_clk_con(self
, name
, count
, ctype
):
252 ck
= self
.get_clock_reset(name
, count
)
253 if ck
== PBase
.get_clock_reset(self
, name
, count
):
256 spc
= "sp_clock, sp_reset"
259 ck
= "core_clock, core_reset"
261 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
263 for p
in self
.peripheral
.pinspecs
:
267 if typ
== 'out' or typ
== 'inout':
268 fname
= self
.pinname_out(pname
)
271 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
272 n_
= "{0}{1}".format(n
, count
)
275 n_
= '{0}_{1}'.format(n_
, pname
)
276 ret
.append(template
.format("Bit#(1)", n_
, ck
, spc
))
277 if typ
== 'in' or typ
== 'inout':
278 fname
= self
.pinname_in(pname
)
281 #fname = self.pinname_in(pname)
282 n_
= "{0}{1}".format(n
, count
)
283 n_
= '{0}_{1}'.format(n_
, pname
)
284 #n_ = self.ifname_tweak(pname, 'in', n_)
285 ret
.append(template
.format("Bit#(1)", n_
, spc
, ck
))
286 return '\n'.join(ret
)
288 def _mk_clk_vcon(self
, name
, count
, ctype
, typ
, pname
, bitspec
):
289 ck
= self
.get_clock_reset(name
, count
)
290 if ck
== PBase
.get_clock_reset(self
, name
, count
):
293 spc
= "sp_clock, sp_reset"
296 ck
= "core_clock, core_reset"
298 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
301 n_
= "{0}{1}".format(name
, count
)
302 n_
= '{0}_{1}'.format(n_
, pname
)
303 if typ
== 'in' or typ
== 'inout':
305 return template
.format(bitspec
, n_
, ck
, spc
)
308 def mk_cellconn(self
, *args
):
311 def mkfast_peripheral(self
, size
=0):
314 def mkslow_peripheral(self
, size
=0):
317 def mksuffix(self
, name
, i
):
320 def __mk_connection(self
, con
, aname
, fabricname
):
321 txt
= "mkConnection ({2}.v_to_slaves\n" + \
322 " [fromInteger(valueOf({1}))],\n" + \
325 print "PBase __mk_connection", self
.name
, aname
328 return txt
.format(con
, aname
, fabricname
)
330 def __mk_master_connection(self
, con
, aname
):
331 txt
= "mkConnection (slow_fabric.v_to_slaves\n" + \
332 " [fromInteger(valueOf({1}))],\n" + \
335 print "PBase __mk_connection", self
.name
, aname
338 return txt
.format(con
, aname
)
340 def mk_connection(self
, count
, fabricname
, typ
, name
=None):
343 print "PBase mk_conn", self
.name
, count
344 aname
= self
.axi_slave_name(name
, count
, typ
)
345 #dname = self.mksuffix(name, count)
346 #dname = "{0}{1}".format(name, dname)
347 con
= self
._mk
_connection
(name
, count
).format(count
, aname
)
348 return self
.__mk
_connection
(con
, aname
, fabricname
)
350 def _mk_connection(self
, name
=None, count
=0):
353 def pinname_out(self
, pname
):
356 def pinname_in(self
, pname
):
359 def pinname_outen(self
, pname
):
362 def ifname_tweak(self
, pname
, typ
, txt
):
365 def pinname_tweak(self
, pname
, typ
, txt
):
371 def mk_plic(self
, inum
, irq_offs
):
373 print "mk_plic", self
.name
, inum
, irq_offs
374 niq
= self
.num_irqs()
376 return ('', irq_offs
)
377 name
= self
.get_iname(inum
)
378 res
.append("// PLIC rules for {0}".format(name
))
379 for idx
in range(niq
):
380 plic_obj
= self
.plic_object(name
, idx
)
381 print "plic_obj", name
, idx
, plic_obj
382 plic
= mkplic_rule
.format(name
, plic_obj
, irq_offs
)
384 irq_offs
+= 1 # increment to next irq
385 return ('\n'.join(res
), irq_offs
)
387 def mk_ext_ifacedef(self
, iname
, inum
):
390 def extfastifinstance(self
, name
, count
):
393 def _extifinstance(self
, name
, count
, suffix
, prefix
, samename
=False,
397 pname
= self
.get_iname(count
)
401 sname
= self
.peripheral
.iname().format(count
)
402 template
= "interface {0}{3} = {2}{1}{4};"
403 return template
.format(pname
, sname
, prefix
, suffix
, ifsuffix
)
405 def extifinstance2(self
, name
, count
):
408 def extifinstance(self
, name
, count
):
409 return self
._extifinstance
(name
, count
, "",
410 "pinmux.peripheral_side.")
414 rule rl_connect_{0}_to_plic_{2};
415 if({1} == 1'b1) begin
416 ff_gateway_queue[{2}].enq(1);
417 plic.ifc_external_irq[{2}].irq_frm_gateway(True);
422 axi_master_declarations
= """\
423 typedef 0 Dmem_master_num;
424 typedef 1 Imem_master_num;
426 typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif )
428 typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif )
430 typedef TAdd#(DMA_master_num,1)
434 axi_fastslave_declarations
= """\
436 typedef TAdd#(LastGen_fastslave_num,1) Sdram_slave_num;
437 typedef TAdd#(Sdram_slave_num ,`ifdef SDRAM 1 `else 0 `endif )
439 typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM 1 `else 0 `endif )
441 typedef TAdd#(BootRom_slave_num ,`ifdef Debug 1 `else 0 `endif )
443 typedef TAdd#(Debug_slave_num , `ifdef TCMemory 1 `else 0 `endif )
445 typedef TAdd#(TCM_slave_num ,`ifdef DMA 1 `else 0 `endif )
447 typedef TAdd#(Dma_slave_num ,1 ) SlowPeripheral_slave_num;
448 typedef TAdd#(SlowPeripheral_slave_num,`ifdef VME 1 `else 0 `endif )
450 typedef TAdd#(VME_slave_num,1) Num_Fast_Slaves;
453 axi_slave_declarations
= """\
454 typedef 0 SlowMaster;
456 typedef TAdd#(LastGen_slave_num,`ifdef CLINT 1 `else 0 `endif )
458 typedef TAdd#(CLINT_slave_num ,`ifdef PLIC 1 `else 0 `endif )
460 typedef TAdd#(Plic_slave_num ,`ifdef AXIEXP 1 `else 0 `endif )
462 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
465 pinmux_cellrule
= """\
466 rule connect_select_lines_pinmux;
472 class CallFn(object):
473 def __init__(self
, peripheral
, name
):
474 self
.peripheral
= peripheral
477 def __call__(self
, *args
):
478 #print "__call__", self.name, self.peripheral.slow, args
479 if not self
.peripheral
.slow
:
481 return getattr(self
.peripheral
.slow
, self
.name
)(*args
[1:])
484 class PeripheralIface(object):
485 def __init__(self
, ifacename
):
487 slow
= slowfactory
.getcls(ifacename
)
488 print "Iface", ifacename
, slow
490 self
.slow
= slow(ifacename
)
491 self
.slow
.peripheral
= self
492 for fname
in ['slowimport',
494 'extifinstance2', 'extifinstance', 'extifdecl',
495 'slowifdecl', 'slowifdeclmux',
498 'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule',
500 'mk_plic', 'mk_ext_ifacedef',
501 '_mk_clk_con', 'mk_ext_ifacedef',
502 'mk_connection', 'mk_cellconn', '_mk_pincon']:
503 fn
= CallFn(self
, fname
)
504 setattr(self
, fname
, types
.MethodType(fn
, self
))
506 #print "PeripheralIface"
509 def mksuffix(self
, name
, i
):
510 if self
.slow
is None:
512 return self
.slow
.mksuffix(name
, i
)
514 def axi_reg_def(self
, start
, count
):
517 return self
.slow
.axi_reg_def(start
, self
.ifacename
, count
)
519 def axi_master_idx(self
, start
, count
, typ
):
520 if not self
.slow
or not self
.slow
.has_axi_master():
522 return self
.slow
.axi_master_idx(start
, self
.ifacename
, count
, typ
)
524 def axi_slave_idx(self
, start
, count
, typ
):
527 return self
.slow
.axi_slave_idx(start
, self
.ifacename
, count
, typ
)
529 def axi_fastaddr_map(self
, count
):
532 return self
.slow
.axi_fastaddr_map(self
.ifacename
, count
)
534 def axi_addr_map(self
, count
):
537 return self
.slow
.axi_addr_map(self
.ifacename
, count
)
540 class PeripheralInterfaces(object):
542 self
.fastbusmode
= False
544 def slowimport(self
, *args
):
546 for (name
, count
) in self
.ifacecount
:
547 #print "slowimport", name, self.data[name].slowimport
548 ret
.append(self
.data
[name
].slowimport())
549 return '\n'.join(li(list(filter(None, ret
)), 4))
551 def extfastifinstance(self
, *args
):
553 for (name
, count
) in self
.ifacecount
:
554 for i
in range(count
):
555 iname
= self
.data
[name
].iname().format(i
)
556 print "extfast", iname
, self
.is_on_fastbus(name
, i
)
557 if self
.is_on_fastbus(name
, i
):
559 ret
.append(self
.data
[name
].extfastifinstance(name
, i
))
560 return '\n'.join(li(list(filter(None, ret
)), 8))
562 def extifinstance2(self
, *args
):
564 for (name
, count
) in self
.ifacecount
:
565 for i
in range(count
):
566 iname
= self
.data
[name
].iname().format(i
)
567 ret
.append(self
.data
[name
].extifinstance2(name
, i
))
568 return '\n'.join(li(list(filter(None, ret
)), 8))
570 def extifinstance(self
, *args
):
572 for (name
, count
) in self
.ifacecount
:
573 for i
in range(count
):
574 iname
= self
.data
[name
].iname().format(i
)
575 if not self
.is_on_fastbus(name
, i
):
577 ret
.append(self
.data
[name
].extifinstance(name
, i
))
578 return '\n'.join(li(list(filter(None, ret
)), 8))
580 def extifdecl(self
, *args
):
582 for (name
, count
) in self
.ifacecount
:
583 for i
in range(count
):
584 if not self
.is_on_fastbus(name
, i
):
586 ret
.append(self
.data
[name
].extifdecl(name
, i
))
587 return '\n'.join(li(list(filter(None, ret
)), 8))
589 def slowifdeclmux(self
, *args
):
591 for (name
, count
) in self
.ifacecount
:
592 for i
in range(count
):
593 ret
.append(self
.data
[name
].slowifdeclmux(name
, i
))
594 return '\n'.join(li(list(filter(None, ret
)), 8))
596 def fastifdecl(self
, *args
):
598 for (name
, count
) in self
.ifacecount
:
599 for i
in range(count
):
600 print "fastifdecl", name
, i
, self
.is_on_fastbus(name
, i
)
601 if self
.is_on_fastbus(name
, i
):
603 ret
.append(self
.data
[name
].fastifdecl(name
, i
))
604 return '\n'.join(li(list(filter(None, ret
)), 4))
606 def slowifdecl(self
, *args
):
608 for (name
, count
) in self
.ifacecount
:
609 for i
in range(count
):
610 if self
.is_on_fastbus(name
, i
):
612 ret
.append(self
.data
[name
].slowifdecl().format(i
, name
))
613 return '\n'.join(list(filter(None, ret
)))
615 def axi_fastmem_def(self
, *args
):
616 return self
._axi
_reg
_def
(0x50000000, *args
)
618 def axi_reg_def(self
, *args
):
619 return self
._axi
_reg
_def
(0x00011100, *args
)
621 def _axi_reg_def(self
, start
, *args
):
623 for (name
, count
) in self
.ifacecount
:
624 for i
in range(count
):
625 if self
.is_on_fastbus(name
, i
):
627 x
= self
.data
[name
].axi_reg_def(start
, i
)
628 #print ("ifc", name, x)
632 return '\n'.join(list(filter(None, ret
)))
634 def _axi_num_idx(self
, start
, template
, typ
, idxtype
, *args
):
636 for (name
, count
) in self
.ifacecount
:
637 for i
in range(count
):
638 if self
.is_on_fastbus(name
, i
):
641 fn
= self
.data
[name
].axi_master_idx
643 fn
= self
.data
[name
].axi_slave_idx
644 (rdef
, offs
) = fn(start
, i
, idxtype
)
645 #print ("ifc", name, rdef, offs)
648 ret
.append("typedef %d LastGen_%s_num;" % (start
- 1, typ
))
649 decls
= '\n'.join(list(filter(None, ret
)))
650 return template
.format(decls
)
652 def axi_slave_idx(self
, *args
):
653 return self
._axi
_num
_idx
(0, axi_slave_declarations
, 'slave',
656 def axi_fastslave_idx(self
, *args
):
657 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
660 def axi_master_idx(self
, *args
):
661 return self
._axi
_num
_idx
(2, axi_master_declarations
, 'master',
664 def axi_fastslave_idx(self
, *args
):
665 return self
._axi
_num
_idx
(0, axi_fastslave_declarations
, 'fastslave',
668 def axi_fastaddr_map(self
, *args
):
670 for (name
, count
) in self
.ifacecount
:
671 for i
in range(count
):
672 if self
.is_on_fastbus(name
, i
):
674 ret
.append(self
.data
[name
].axi_fastaddr_map(i
))
675 return '\n'.join(li(list(filter(None, ret
)), 8))
677 def axi_addr_map(self
, *args
):
679 for (name
, count
) in self
.ifacecount
:
680 for i
in range(count
):
681 if self
.is_on_fastbus(name
, i
):
683 ret
.append(self
.data
[name
].axi_addr_map(i
))
684 return '\n'.join(li(list(filter(None, ret
)), 8))
686 def mkfast_peripheral(self
, *args
):
688 for (name
, count
) in self
.ifacecount
:
689 for i
in range(count
):
690 if self
.is_on_fastbus(name
, i
):
692 #print "mkfast", name, count
693 x
= self
.data
[name
].mkfast_peripheral()
695 suffix
= self
.data
[name
].mksuffix(name
, i
)
696 ret
.append(x
.format(suffix
))
697 return '\n'.join(li(list(filter(None, ret
)), 8))
699 def mkslow_peripheral(self
, *args
):
701 for (name
, count
) in self
.ifacecount
:
702 for i
in range(count
):
703 if self
.is_on_fastbus(name
, i
):
705 #print "mkslow", name, count
706 x
= self
.data
[name
].mkslow_peripheral()
708 suffix
= self
.data
[name
].mksuffix(name
, i
)
709 ret
.append(x
.format(suffix
))
710 return '\n'.join(li(list(filter(None, ret
)), 8))
712 def mk_fast_connection(self
, *args
):
714 for (name
, count
) in self
.ifacecount
:
715 for i
in range(count
):
716 if self
.is_on_fastbus(name
, i
):
718 txt
= self
.data
[name
].mk_connection(i
, "fabric", "fast")
721 print self
.data
[name
].mk_connection
723 return '\n'.join(li(list(filter(None, ret
)), 12))
725 def mk_connection(self
, *args
):
727 for (name
, count
) in self
.ifacecount
:
728 for i
in range(count
):
729 if self
.is_on_fastbus(name
, i
):
731 txt
= self
.data
[name
].mk_connection(i
, "slow_fabric", "")
734 print self
.data
[name
].mk_connection
736 return '\n'.join(li(list(filter(None, ret
)), 8))
738 def mk_cellconn(self
):
741 for (name
, count
) in self
.ifacecount
:
742 for i
in range(count
):
743 if self
.is_on_fastbus(name
, i
):
745 res
= self
.data
[name
].mk_cellconn(cellcount
, name
, i
)
748 (txt
, cellcount
) = res
750 ret
= li('\n'.join(list(filter(None, ret
))), 4)
751 return li(pinmux_cellrule
.format(ret
), 4)
754 return self
._mk
_pincon
("slow")
756 def mk_fast_pincon(self
):
757 return self
._mk
_pincon
("fast")
759 def _mk_pincon(self
, typ
):
761 for (name
, count
) in self
.ifacecount
:
762 for i
in range(count
):
763 if self
.is_on_fastbus(name
, i
):
765 txt
= self
.data
[name
]._mk
_pincon
(name
, i
, typ
)
767 return '\n'.join(li(list(filter(None, ret
)), 4))
769 def mk_dma_irq(self
):
777 for (name
, count
) in self
.ifacecount
:
779 for i
in range(count
):
780 if not self
.is_on_fastbus(name
, i
):
782 txt
= self
.data
[name
].mk_dma_sync(name
, i
)
786 txt
= self
.data
[name
].mk_dma_rule(name
, i
)
787 ifacerules
.append(txt
)
788 txt
= self
.data
[name
].mk_dma_connect(name
, i
)
790 ifacerules
= list(filter(None, ifacerules
))
792 txt
= "rule synchronize_%s_interrupts;" % name
795 rules
.append("endrule")
797 cnct
= list(filter(None, cnct
))
799 _cnct
= ["rule rl_connect_interrupt_to_DMA;",
800 " Bit #(%d) lv_interrupt_to_DMA={" % ct
]
803 cnct
= _cnct
+ [spc
+ spcsep
.join(cnct
)]
805 cnct
.append(" dma.interrupt_from_peripherals(\n" +
806 " lv_interrupt_to_DMA);")
807 cnct
.append("endrule;")
809 ret
= list(filter(None, sync
+ rules
+ cnct
))
811 return '\n'.join(ret
)
813 def num_dmachannels(self
):
814 return "`define NUM_DMACHANNELS {0}".format(self
.dma_count
)
816 def mk_ext_ifacedef(self
):
818 for (name
, count
) in self
.ifacecount
:
819 for i
in range(count
):
820 if self
.is_on_fastbus(name
, i
):
822 txt
= self
.data
[name
].mk_ext_ifacedef(name
, i
)
824 return '\n'.join(li(list(filter(None, ret
)), 8))
828 irq_offs
= 8 # XXX: DMA scovers 0-7?
829 for (name
, count
) in self
.ifacecount
:
830 for i
in range(count
):
831 if self
.is_on_fastbus(name
, i
):
833 res
= self
.data
[name
].mk_plic(i
, irq_offs
)
836 (txt
, irq_offs
) = res
838 self
.num_slow_irqs
= irq_offs
839 return '\n'.join(li(list(filter(None, ret
)), 4))
841 def mk_sloirqsdef(self
):
842 return " `define NUM_SLOW_IRQS {0}".format(self
.num_slow_irqs
)
844 def mk_fastclk_con(self
):
845 return self
._mk
_clk
_con
("fast")
847 def mk_slowclk_con(self
):
848 return self
._mk
_clk
_con
("slow")
850 def _mk_clk_con(self
, ctype
):
852 for (name
, count
) in self
.ifacecount
:
853 for i
in range(count
):
854 if self
.is_on_fastbus(name
, i
):
856 txt
= self
.data
[name
]._mk
_clk
_con
(name
, i
, ctype
)
858 return '\n'.join(li(list(filter(None, ret
)), 8))
860 def is_on_fastbus(self
, name
, i
):
861 #print "fastbus mode", self.fastbusmode, name, i
862 iname
= self
.data
[name
].iname().format(i
)
864 return iname
not in self
.fastbus
865 return iname
in self
.fastbus
868 class PFactory(object):
869 def getcls(self
, name
):
870 from uart
import uart
871 from quart
import quart
872 from sdmmc
import sdmmc
874 from eint
import eint
875 from rs232
import rs232
877 from eint
import eint
878 from jtag
import jtag
879 from spi
import spi
, mspi
880 from qspi
import qspi
, mqspi
881 from gpio
import gpio
882 from rgbttl
import rgbttl
883 from flexbus
import flexbus
885 for k
, v
in {'uart': uart
,
901 if name
.startswith(k
):
906 slowfactory
= PFactory()
908 if __name__
== '__main__':
912 i
= PeripheralIface('uart')
914 i
= PeripheralIface('gpioa')