1 from bsv
.peripheral_gen
.base
import PBase
6 size
= len(self
.peripheral
.pinspecs
)
7 return " `define NUM_EINTS %d" % size
9 def mkslow_peripheral(self
, size
=0):
10 size
= len(self
.peripheral
.pinspecs
)
11 return " Wire#(Bit#(%d)) wr_interrupt <- mkWire();" % size
13 def axi_slave_name(self
, name
, ifacenum
):
16 def axi_slave_idx(self
, idx
, name
, ifacenum
):
19 def axi_addr_map(self
, name
, ifacenum
):
22 def ifname_tweak(self
, pname
, typ
, txt
):
25 print "ifnameweak", pname
, typ
, txt
26 return "wr_interrupt[{0}] <= ".format(pname
)
28 def mk_pincon(self
, name
, count
):
29 ret
= [PBase
.mk_pincon(self
, name
, count
)]
30 size
= len(self
.peripheral
.pinspecs
)
31 ret
.append(eint_pincon_template
.format(size
))
32 ret
.append(" rule con_%s%d_io_in;" % (name
, count
))
33 ret
.append(" wr_interrupt <= ({")
34 for idx
, p
in enumerate(self
.peripheral
.pinspecs
):
36 sname
= self
.peripheral
.pname(pname
).format(count
)
37 ps
= "pinmux.peripheral_side.%s" % sname
38 comma
= '' if idx
== size
- 1 else ','
39 ret
.append(" {0}{1}".format(ps
, comma
))
41 ret
.append(" endrule")
46 eint_pincon_template
= '''\
47 // EINT is offset at end of other peripheral interrupts
49 for(Integer i=0;i<{0};i=i+ 1)begin
50 rule connect_int_to_plic(wr_interrupt[i]==1);
51 ff_gateway_queue[i+`NUM_SLOW_IRQS].enq(1);
52 plic.ifc_external_irq[i+`NUM_SLOW_IRQS].irq_frm_gateway(True);