1 from bsv
.peripheral_gen
.base
import PBase
6 return " import qspi :: *;"
9 return " interface QSPI_out qspi{0}_out;\n" + \
10 " method Bit#(1) qspi{0}_isint;"
12 def num_axi_regs32(self
):
15 def mkslow_peripheral(self
, size
=0):
16 return " Ifc_qspi qspi{0} <- mkqspi();"
18 def _mk_connection(self
, name
=None, count
=0):
19 return "qspi{0}.slave"
21 def pinname_out(self
, pname
):
22 return {'ck': 'out.clk_o',
30 def pinname_outen(self
, pname
):
33 'io0': 'out.io_enable[0]',
34 'io1': 'out.io_enable[1]',
35 'io2': 'out.io_enable[2]',
36 'io3': 'out.io_enable[3]',
39 def mk_pincon(self
, name
, count
):
40 ret
= [PBase
.mk_pincon(self
, name
, count
)]
41 # special-case for gpio in, store in a temporary vector
42 plen
= len(self
.peripheral
.pinspecs
)
43 ret
.append(" // XXX NSS and CLK are hard-coded master")
44 ret
.append(" // TODO: must add qspi slave-mode")
45 ret
.append(" // all ins done in one rule from 4-bitfield")
46 ret
.append(" rule con_%s%d_io_in;" % (name
, count
))
47 ret
.append(" {0}{1}.out.io_i({{".format(name
, count
))
48 for i
, p
in enumerate(self
.peripheral
.pinspecs
):
51 if not pname
.startswith('io'):
55 sname
= self
.peripheral
.pname(pname
).format(count
)
56 ps
= "pinmux.peripheral_side.%s_in" % sname
57 comma
= '' if i
== 5 else ','
58 ret
.append(" {0}{1}".format(ps
, comma
))
60 ret
.append(" endrule")
66 def plic_object(self
, pname
, idx
):
67 return "{0}.interrupts()[{1}]".format(pname
, idx
)
69 def mk_ext_ifacedef(self
, iname
, inum
):
70 name
= self
.get_iname(inum
)
71 return " method {0}_isint = {0}.interrupts[5];".format(name
)
73 def slowifdeclmux(self
):
74 return " method Bit#(1) {1}{0}_isint;"