1 from bsv
.peripheral_gen
.base
import PBase
7 return " import qspi :: *;"
10 return " interface QSPI_out qspi{0}_out;\n" + \
11 " method Bit#(1) qspi{0}_isint;"
13 def num_axi_regs32(self
):
16 def mkslow_peripheral(self
, size
=0):
17 return " Ifc_qspi qspi{0} <- mkqspi();"
19 def _mk_connection(self
, name
=None, count
=0):
20 return "qspi{0}.slave"
22 def pinname_out(self
, pname
):
23 return {'ck': 'out.clk_o',
31 def pinname_outen(self
, pname
):
34 'io0': 'out.io_enable[0]',
35 'io1': 'out.io_enable[1]',
36 'io2': 'out.io_enable[2]',
37 'io3': 'out.io_enable[3]',
40 def mk_pincon(self
, name
, count
):
41 ret
= [PBase
.mk_pincon(self
, name
, count
)]
42 # special-case for gpio in, store in a temporary vector
43 plen
= len(self
.peripheral
.pinspecs
)
44 ret
.append(" // XXX NSS and CLK are hard-coded master")
45 ret
.append(" // TODO: must add qspi slave-mode")
46 ret
.append(" // all ins done in one rule from 4-bitfield")
47 ret
.append(" rule con_%s%d_io_in;" % (name
, count
))
48 ret
.append(" {0}{1}.out.io_i({{".format(name
, count
))
49 for i
, p
in enumerate(self
.peripheral
.pinspecs
):
52 if not pname
.startswith('io'):
56 sname
= self
.peripheral
.pname(pname
).format(count
)
57 ps
= "pinmux.peripheral_side.%s_in" % sname
58 comma
= '' if i
== 5 else ','
59 ret
.append(" {0}{1}".format(ps
, comma
))
61 ret
.append(" endrule")
67 def plic_object(self
, pname
, idx
):
68 return "{0}.interrupts()[{1}]".format(pname
, idx
)
70 def mk_ext_ifacedef(self
, iname
, inum
):
71 name
= self
.get_iname(inum
)
72 return " method {0}_isint = {0}.interrupts[5];".format(name
)
74 def slowifdeclmux(self
):
75 return " method Bit#(1) {1}{0}_isint;"