1 from bsv
.peripheral_gen
.base
import PBase
7 return " import Uart16550 :: *;"
10 return " interface RS232_PHY_Ifc quart{0}_coe;\n" + \
11 " method Bit#(1) quart{0}_intr;"
13 def num_axi_regs32(self
):
16 def mkslow_peripheral(self
, size
=0):
17 return " Uart16550_AXI4_Lite_Ifc quart{0} <- \n" + \
18 " mkUart16550(clocked_by sp_clock,\n" + \
19 " reset_by sp_reset, sp_clock, sp_reset);"
21 def _mk_connection(self
, name
=None, count
=0):
22 return "quart{0}.slave_axi_uart"
24 def pinname_out(self
, pname
):
25 return {'tx': 'coe_rs232.stx_out',
26 'rts': 'coe_rs232.rts_out',
29 def pinname_in(self
, pname
):
30 return {'rx': 'coe_rs232.srx_in',
31 'cts': 'coe_rs232.cts_in'
34 def __disabled_mk_pincon(self
, name
, count
):
35 ret
= [PBase
.mk_pincon(self
, name
, count
)]
36 ret
.append(" rule con_%s%d_io_in;" % (name
, count
))
37 ret
.append(" {0}{1}.coe_rs232.modem_input(".format(name
, count
))
38 for idx
, pname
in enumerate(['rx', 'cts']):
39 sname
= self
.peripheral
.pname(pname
).format(count
)
40 ps
= "pinmux.peripheral_side.%s" % sname
41 ret
.append(" {0},".format(ps
))
42 ret
.append(" 1'b1,1'b0,1'b1")
44 ret
.append(" endrule")
51 def plic_object(self
, pname
, idx
):
52 return "{0}_interrupt.read".format(pname
)
54 def mk_plic(self
, inum
, irq_offs
):
55 name
= self
.get_iname(inum
)
56 ret
= [uart_plic_template
.format(name
, irq_offs
)]
57 (ret2
, irq_offs
) = PBase
.mk_plic(self
, inum
, irq_offs
)
59 return ('\n'.join(ret
), irq_offs
)
61 def mk_ext_ifacedef(self
, iname
, inum
):
62 name
= self
.get_iname(inum
)
63 return " method {0}_intr = {0}.irq;".format(name
)
65 def slowifdeclmux(self
, name
, count
):
66 sname
= self
.peripheral
.iname().format(count
)
67 return " method Bit#(1) %s_intr;" % sname
70 uart_plic_template
= """\
71 // PLIC {0} synchronisation with irq {1}
72 SyncBitIfc#(Bit#(1)) {0}_interrupt <-
73 mkSyncBitToCC(sp_clock, uart_reset);
74 rule plic_synchronize_{0}_interrupt_{1};
75 {0}_interrupt.send({0}.irq);