1 from bsv
.peripheral_gen
.base
import PBase
7 return " import qspi :: *;"
10 return " interface QSPI_out spi{0}_out;\n" + \
11 " method Bit#(1) spi{0}_isint;"
13 def num_axi_regs32(self
):
16 def mkslow_peripheral(self
):
17 return " Ifc_qspi spi{0} <- mkqspi();"
19 def _mk_connection(self
, name
=None, count
=0):
22 def pinname_out(self
, pname
):
23 return {'clk': 'out.clk_o',
25 'mosi': 'out.io_o[0]',
26 'miso': 'out.io_o[1]',
29 def pinname_outen(self
, pname
):
32 'mosi': 'out.io_enable[0]',
33 'miso': 'out.io_enable[1]',
36 def mk_pincon(self
, name
, count
):
37 ret
= [PBase
.mk_pincon(self
, name
, count
)]
38 # special-case for gpio in, store in a temporary vector
39 plen
= len(self
.peripheral
.pinspecs
)
40 ret
.append(" // XXX NSS and CLK are hard-coded master")
41 ret
.append(" // TODO: must add spi slave-mode")
42 ret
.append(" // all ins done in one rule from 4-bitfield")
43 ret
.append(" rule con_%s%d_io_in;" % (name
, count
))
44 ret
.append(" {0}{1}.out.io_i({{".format(name
, count
))
45 for idx
, pname
in enumerate(['mosi', 'miso']):
46 sname
= self
.peripheral
.pname(pname
).format(count
)
47 ps
= "pinmux.peripheral_side.%s_in" % sname
48 ret
.append(" {0},".format(ps
))
49 ret
.append(" 1'b0,1'b0")
51 ret
.append(" endrule")
54 def mk_ext_ifacedef(self
, iname
, inum
):
55 name
= self
.get_iname(inum
)
56 return " method {0}_isint = {0}.interrupts[5];".format(name
)
58 def slowifdeclmux(self
):
59 return " method Bit#(1) {1}{0}_isint;"