refactor peripheral_gen, split out interface classes
[pinmux.git] / src / bsv / peripheral_gen / spi.py
1 from bsv.peripheral_gen.base import PBase
2
3 class spi(PBase):
4
5 def slowimport(self):
6 return " import qspi :: *;"
7
8 def slowifdecl(self):
9 return " interface QSPI_out spi{0}_out;\n" + \
10 " method Bit#(1) spi{0}_isint;"
11
12 def num_axi_regs32(self):
13 return 13
14
15 def mkslow_peripheral(self):
16 return " Ifc_qspi spi{0} <- mkqspi();"
17
18 def _mk_connection(self, name=None, count=0):
19 return "spi{0}.slave"
20
21 def pinname_out(self, pname):
22 return {'clk': 'out.clk_o',
23 'nss': 'out.ncs_o',
24 'mosi': 'out.io_o[0]',
25 'miso': 'out.io_o[1]',
26 }.get(pname, '')
27
28 def pinname_outen(self, pname):
29 return {'clk': 1,
30 'nss': 1,
31 'mosi': 'out.io_enable[0]',
32 'miso': 'out.io_enable[1]',
33 }.get(pname, '')
34
35 def mk_pincon(self, name, count):
36 ret = [PBase.mk_pincon(self, name, count)]
37 # special-case for gpio in, store in a temporary vector
38 plen = len(self.peripheral.pinspecs)
39 ret.append(" // XXX NSS and CLK are hard-coded master")
40 ret.append(" // TODO: must add spi slave-mode")
41 ret.append(" // all ins done in one rule from 4-bitfield")
42 ret.append(" rule con_%s%d_io_in;" % (name, count))
43 ret.append(" {0}{1}.out.io_i({{".format(name, count))
44 for idx, pname in enumerate(['mosi', 'miso']):
45 sname = self.peripheral.pname(pname).format(count)
46 ps = "pinmux.peripheral_side.%s_in" % sname
47 ret.append(" {0},".format(ps))
48 ret.append(" 1'b0,1'b0")
49 ret.append(" });")
50 ret.append(" endrule")
51 return '\n'.join(ret)
52
53 def mk_ext_ifacedef(self, iname, inum):
54 name = self.get_iname(inum)
55 return " method {0}_isint = {0}.interrupts[5];".format(name)
56
57 def slowifdeclmux(self):
58 return " method Bit#(1) {1}{0}_isint;"
59
60